JPH08148504A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device excellent in high frequency characteristics in which high speed operation is attained with low power consumption by reducing the parasitic resistance and capacitance in a collector region. CONSTITUTION: A collector buried insulation layer 31 is formed on a supporting substrate 30 and a collector buried metal layer 32, comprising a first high melting point metal layer 32a and a first barrier metal layer 32b, is formed thereon. A collector region 33 is then formed on the collector buried metal layer 32 and a second barrier metal layer 34b and a second high melting point metal layer 34c are buried in a second groove 34a penetrating the collector region 33 thus forming a collector lead-out electrode 34 connected electrically with the collector buried metal layer 32 on the bottom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a bipolar transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art It is widely known that a bipolar transistor is one of the semiconductor devices excellent in high speed and high drivability, and a device structure has been devised to improve the device performance of the bipolar transistor. Came.

The collector of the bipolar transistor is required to have a low resistance and a small capacitance with the substrate of the opposite conductivity type for high frequency operation.

FIG. 16 is a partial sectional view showing the structure of a conventional bipolar transistor. In this figure, 1 is P
Substrate 2 made of a positive type silicon substrate, 2 is a collector burying layer formed on the substrate 1 and made of an N-type high concentration region having a thickness of about 3 μm, and 3 is a thickness formed on the collector burying layer 2. It is a 1 μm N-type collector epitaxial layer. Reference numeral 4 is a collector extraction layer formed of an N-type high concentration region that penetrates the collector epitaxial layer 3 and reaches the collector buried layer 2.

Reference numeral 5 denotes an element isolation region formed in the collector epitaxial layer 3 and reaching the substrate 1, which penetrates the collector epitaxial layer 3 and the collector buried layer 2.
A channel cut region 5b formed at the bottom of the first groove 5a reaching the substrate 1 and a filling material 5c made of a CVD oxide film, a polysilicon film or the like filled in the first groove 5a.
And a CVD oxide film 5d provided around this filling material.

Reference numeral 6 is a field oxide film having a thickness of about 0.5 μm formed on the collector epitaxial layer 3, 7 is a P-type external base region formed between the field oxide films 6, and 8 is this external base region 7. A P-type intrinsic base region sandwiched between and is an N-type emitter region formed on the intrinsic base region 7.

Reference numeral 10 denotes an external base electrode which is electrically connected to the external base region 7 made of a polysilicon film, and 11
Is formed on this external base electrode 10, and is formed by CVD, for example.
The first insulating film 12 made of an insulating material such as an oxide film is formed by CVD so as to cover the side wall of the external base electrode 10.
Sidewall spacers made of an insulator such as an oxide film, 1
3 is an emitter electrode formed on the emitter region 9 and made of a conductor such as a polysilicon film.

A first interlayer insulating film 14 is formed on the emitter electrode 13 and is made of an insulating material such as a CVD oxide film, and 15 is formed on the first interlayer insulating film 14.
A second interlayer insulating film made of an insulating material such as a VD oxide film, 16
Is an electrode lead-out hole which is an opening formed in the first interlayer insulating film 14, the second interlayer insulating film 15 and the field oxide film 6, and 17 is electrically connected to each electrode through the electrode lead-out hole 16. The wiring is made of a conductor such as aluminum and connected to.

A method of manufacturing the bipolar transistor configured as described above will be described below with reference to FIGS. 17 to 23 are manufacturing process diagrams sequentially showing manufacturing processes of a conventional bipolar transistor.

First, as shown in FIG. 17, 3 × 10 of N-type antimony or arsenic or the like is formed at a depth of about 3 μm of the substrate 1.
Collector buried layer 2 diffused to a high concentration of ²⁰ co / cm ³
And then a collector epitaxial layer 3 containing N-type impurities such as phosphorus or arsenic is grown on the surface to a thickness of 1 μm.

Next, as shown in FIG. 18, a thermal oxide film 18 having a thickness of about 50 nm is formed on the surface of the collector epitaxial layer 3, and then a nitride film 19 having a thickness of about 0.2 μm is deposited. A CVD oxide film 20 having a thickness of about 1 μm is deposited. Next, a resist mask having an opening only in the region to be the element isolation region 5 is formed by a normal photo-etching technique, and the thermal oxide film 18, the nitride film 19 and the CVD oxide film 20 are etched. Next, the collector epitaxial layer 3 and the collector burying layer 2 are etched using the CVD oxide film 20 as a mask, and the first groove 5a reaching the substrate 1 is opened. Then, a thermal oxide film (not shown) of about 0.1 μm is formed around the first groove 5a by performing heat treatment in a steam atmosphere. This thermal oxidation is sacrificial oxidation for removing the etching damage of the first groove 5a. next,
P-type impurities such as boron are ion-implanted at an accelerating voltage of 50 KeV and an implantation amount of 1 × 10 ¹³ / cm ² to form a channel cut region 5b, and then the thermal oxide film of the first groove 5a is removed.

Next, the CVD oxide film 5 having a thickness of about 0.1 μm is formed.
After depositing d, a filling material 5c such as a polysilicon film or a CVD oxide film is deposited to a thickness of, for example, 1.6 μm, and then an etchback method is performed to fill the first groove 5a with the filling material 5c. At this time, the nitride film 19 protects the surface of the filling material 5c during etching back. If the filling material 5c is a CVD oxide film, the CVD oxide film 5d need not be provided. Next, the nitride film 19 and the thermal oxide film 18 are sequentially removed, and the thermal oxidation method or C
A field oxide film 6 having a thickness of about 0.5 μm is formed by the VD method (FIG. 19).

Next, as shown in FIG. 20, the nitride film 2
1 is deposited and only the region to be the collector extraction layer 4 is opened. N-type impurities such as phosphorus are ion-implanted through the openings 22 to form the collector extraction layer 4 which is a high concentration region.

Next, as shown in FIG. 21, the opening 22 is covered with an oxide film formed by thermal oxidation or the like, and then the nitride film 21 is removed to form a field oxide film 6 on a region which will be a base region 8 later. After removing by etching, a polysilicon film is deposited, and P-type impurities such as boron are ion-implanted into the polysilicon film at an acceleration voltage of 10 KeV and an implantation amount of 4 × 10 ¹⁵ / cm ² . After that, C is formed on the polysilicon film.
A first insulating film 11 made of a VD oxide film is deposited by about 0.2 μm. Next, after forming a resist pattern in the shape of the base extraction electrode 10, the first insulating film 11 and the polysilicon film are etched, the resist is removed, and the base extraction electrode 10 is formed. Then, for example, BF ₂ which is a P-type impurity for the intrinsic base is accelerated into the region 23 which will be an intrinsic base region and an emitter region later at an accelerating voltage of 30 KeV and an implantation amount of 8 × 1.
Ion implantation is performed at 0 ¹³ / cm ² .

Next, as shown in FIG. 22, a CVD oxide film having a thickness of about 0.2 μm is deposited on the entire surface by the CVD method, and then the entire surface is etched, so that the width of the sidewall of the base extraction electrode 10 is reduced to zero. The sidewall spacer 12 having a thickness of 0.15 μm is formed.

Next, as shown in FIG. 23, a polysilicon film to be the emitter electrode 13 is formed on the entire surface by, for example, about 0.2.
μm deposited, and arsenic, which is an N-type impurity, is accelerated into this polysilicon film at an acceleration voltage of 50 KeV and an implantation amount of 1 × 10 ¹⁶ / cm ^2.
Then, the emitter electrode 13 is formed by ion implantation, forming a resist mask to be the emitter electrode 13 and etching the resist mask, and removing the resist mask. Next, a CVD oxide film with no impurities added, for example, with a thickness of about 0.1
After depositing μm, CVD with impurities such as phosphorus and boron added
An oxide film is deposited to a thickness of 1.6 μm, for example. This composite CV
After depositing the first interlayer insulating film 14 which is a D oxide film,
By performing a heat treatment at a temperature of 00 to 900 ° C. for several tens of minutes, the first interlayer insulating film 14 is fluidized to improve the flatness, and the external base electrode 10 and the emitter electrode 13 are each formed of polysilicon. Are diffused to form an external base region 7, an intrinsic base region 8 and an emitter region 9.

Next, after depositing a CVD oxide film which is the second interlayer insulating film 15 without addition of impurities, an electrode lead-out hole 16 is formed on each electrode, and a metal film such as aluminum is deposited, A wiring pattern is patterned to complete the bipolar transistor shown in FIG.

[0018]

However, in the conventional bipolar transistor configured as described above, since the collector buried layer 2 is formed of the high concentration diffusion layer, it is difficult to reduce the collector resistance value. There is a limit. Further, in order to operate the bipolar transistor at a high frequency, the isolation between the elements is made into a trench isolation in which an insulator is embedded in the first groove 5a to reduce the substrate capacitance between the collector epitaxial layer 3 and the semiconductor substrate 1. Nevertheless, there is a substrate capacitance between the collector buried layer 2 and the semiconductor substrate 1. Therefore, there is a problem that the collector resistance value and the substrate capacitance cannot be sufficiently reduced, and the low power consumption and high speed of the semiconductor device cannot be achieved.

The present invention has been made in order to solve such a problem. By lowering the values of parasitic resistance and parasitic capacitance generated in the collector region, excellent high frequency characteristics are achieved, and high speed operation and low power consumption are achieved. It is an object of the present invention to obtain a semiconductor device and a method for manufacturing the semiconductor device.

[0020]

In a semiconductor device according to claim 1 of the present invention, a collector buried insulating layer made of an insulator formed on a substrate, and a collector buried insulating layer formed on a surface of the collector buried insulating layer. A high-melting-point metal layer or a silicide film is formed in a collector-embedded metal layer formed of a melting-point metal layer or a silicide film, a collector region formed on the surface of the collector-embedded metal layer, and a groove formed through the collector region. It is characterized in that it is provided with a collector lead electrode which is buried and is electrically connected to the collector buried metal layer at the bottom of the groove.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein an insulator is provided in a groove that penetrates the collector region and the collector-buried metal layer to reach the collector-buried insulating layer. It is characterized by having an element isolation region in which is embedded.

Furthermore, a semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the interface between the collector-buried metal layer and the collector region, or the collector-buried metal layer and the collector-buried insulating layer is used. Interface with
Alternatively, a barrier metal layer is provided at the interface between the collector extraction electrode and the collector region.

Further, in the method of manufacturing a semiconductor device according to claim 4 of the present invention, a step of forming a groove in the first semiconductor substrate and filling the groove with a refractory metal layer or a silicide film, and the step of forming the groove A step of depositing a collector-embedded metal layer made of a refractory metal layer or a silicide film on the surface of the formed first semiconductor substrate, and a step of depositing an insulating layer on the collector-embedded metal layer or the second semiconductor substrate And a step of bonding the collector-buried metal layer formed on the first semiconductor substrate via the insulating layer so that one main surface of the second semiconductor substrate faces each other, and the first semiconductor substrate And forming a collector region by etching the back surface of the substrate to form a thin film until the refractory metal layer or the silicide film in the groove is exposed.

A method of manufacturing a semiconductor device according to a fifth aspect of the present invention includes a step of forming a groove in the first semiconductor substrate and filling the groove with a refractory metal layer or a silicide film.
A step of depositing a collector-buried metal layer made of a refractory metal layer or a silicide film on the surface of the first semiconductor substrate in which the groove is formed, and the collector in the outer peripheral region where no element is formed on the first semiconductor substrate. A step of removing the buried metal layer, a step of depositing an insulating layer on the first semiconductor substrate or the second semiconductor substrate after the step of removing the collector buried metal layer, and a step of depositing the insulating layer via the insulating layer. The collector-buried metal layer formed on the first semiconductor substrate and the second
And a step of laminating the semiconductor substrate so that the main surfaces thereof face each other, and the back surface of the first semiconductor substrate is etched to form a thin film until the refractory metal layer or the silicide film in the groove is exposed to form a collector region. And a step of performing.

Further, in the method of manufacturing a semiconductor device according to claim 6 of the present invention, a step of forming a groove in the first semiconductor substrate, filling the groove with a refractory metal layer or a silicide film, and forming the groove Depositing a collector-embedded metal layer made of a refractory metal layer or a silicide film on the surface of the formed first semiconductor substrate, and patterning the collector-embedded metal layer on the first semiconductor substrate into a desired pattern And a step of depositing an insulating layer on the surface of the first semiconductor substrate or the surface of the second semiconductor substrate on which the desired pattern is formed, and forming on the first semiconductor substrate via the insulating layer. The collector-buried metal layer and the second
And a step of laminating the semiconductor substrate so that the main surfaces thereof face each other, and the back surface of the first semiconductor substrate is etched to form a thin film until the refractory metal layer or the silicide film in the groove is exposed to form a collector region. And a step of performing.

[0026]

In the semiconductor device according to the first aspect of the present invention, the collector extraction is made of a collector-embedded metal layer on the lower surface of the collector region and a refractory metal layer or a silicide film electrically connected to the collector-embedded metal layer. Since the electrodes are formed, the collector resistance can be reduced. Further, since the collector-embedded insulating layer is formed between the collector-embedded metal layer and the substrate, the parasitic capacitance can be reduced.

Further, in the semiconductor device according to the second aspect of the present invention, the elements are separated by the element isolation region formed by burying an insulator in a groove penetrating the collector burying metal layer and reaching the collector burying insulating layer. In addition, since the collector-buried metal layer is also separated at the same time, the manufacturing process of the semiconductor device becomes easy.

Further, in the semiconductor device according to claim 3 of the present invention, the interface between the collector-buried metal layer and the collector region, the interface between the collector-buried metal layer and the collector-buried insulating layer, or the collector extraction electrode and the collector region. Since the barrier metal layer is formed at the interface with the collector buried metal layer and the collector region, or the collector buried metal layer and the collector buried insulating layer, or the adhesion between the collector extraction electrode and the collector region is improved. .

Further, in the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, a groove is formed in the first semiconductor substrate, the refractory metal layer or the silicide film is buried in the groove, and then the groove is formed. A collector region is formed by thinning from the back surface of the substrate, and the end point of this thinning process is
By making the refractory metal layer or the silicide film buried in the groove exposed, the end point of thinning can be easily determined, and the thickness of the collector region, the first semiconductor substrate, and the first semiconductor substrate can be determined. Variations among semiconductor substrates can be suppressed.

Further, in the method of manufacturing a semiconductor device according to a fifth aspect of the present invention, the collector-embedded metal layer is removed from an outer peripheral region of the first semiconductor substrate where the element is not formed, and the collector-embedded metal layer is an insulating layer. The covering improves the adhesion of the collector-buried metal layer and prevents peeling during the process.

Further, in the method of manufacturing a semiconductor device according to the sixth aspect of the present invention, the collector-embedded metal layer is formed into a small pattern and is covered with an insulating layer to improve adhesion, and the collector-embedded metal layer is peeled off. Prevent that.

[0032]

【Example】

Example 1. FIG. 1 is a partial cross-sectional view showing a bipolar transistor according to an embodiment of the present invention. In the figure, the same parts as those of the conventional one are designated by the same reference numerals, and detailed description thereof will be omitted.

In this figure, 30 is a support substrate as a second semiconductor substrate made of an N-type silicon substrate, 31 is a CV formed on the support substrate 30 and having a thickness of, for example, about 1 μm.
Collector embedded insulating layer made of an insulator such as D oxide film, 3
Reference numeral 2 denotes a collector-embedded metal layer formed on the collector-embedded insulating layer 31, which includes a first refractory metal layer 32a and a first barrier metal layer 32b formed on the first refractory metal layer 32a. In this embodiment, the first refractory metal layer 32a is made of W having a thickness of 1.5 μm, and the first barrier metal layer 32b is made of TiN having a thickness of 0.1 μm.
Is used.

Reference numeral 33 denotes a collector region made of the first semiconductor substrate 1 (see FIGS. 2 and 3) made of an N-type semiconductor formed on the surface of the collector-buried metal layer 32, and 34 penetrates the collector region 33. Then, with the collector extraction electrode, which is a groove-type electrode electrically connected to the collector-buried metal layer 32, the second groove 34a reaching the collector-buried metal layer 32 from the surface of the collector region 33, and the second groove 34a
Second barrier metal layer 3 formed on the peripheral wall of the groove 34a of
4b and a second refractory metal layer 34c filling the second groove 34a in which the second barrier metal layer 34b is formed. In the present embodiment, the second barrier metal layer 34b is formed of the second refractory metal layer 34b. The first barrier metal layer 32b and the second
The refractory metal layer 34c is made of the same material as that of the first refractory metal layer 32a.

In the bipolar transistor described above, the collector buried metal layer 32 made of the first refractory metal layer 32a having a low resistance is formed between the collector region 33 and the collector buried insulating layer 31, so that the collector current is reduced. Flows through the collector-embedded metal layer 32, so that the parasitic resistance value of the collector region 33 is reduced and the voltage drop due to the parasitic resistance is reduced as compared with the conventional bipolar transistor. Therefore, high speed operation of the transistor is possible, high frequency characteristics of the transistor are improved, and low power consumption can be achieved.

Further, in the bipolar transistor of this embodiment, the collector buried metal layer 32 is penetrated,
First trench 5a reaching the collector-embedded insulating layer 31
Element isolation is performed by the element isolation region 5 in which the filling material 5c made of an insulator is embedded, so that the collector embedded metal layer 32 can be formed on the entire bottom surface of the collector region 33. Therefore, when the buried collector layer 2 is formed of a diffusion layer as in the conventional bipolar transistor shown in FIG. 16, the collector epitaxial layer 3 and the first substrate 1 are used in a reverse bias state, and therefore the depletion capacitance is reduced. However, this capacitance does not occur in the bipolar transistor of this embodiment, the capacitance between the collector region 33 and the support substrate 30 can be greatly reduced, and high frequency operation becomes possible.

That is, for example, the emitter size is 0.5 μ
m × 0.9 μm, collector size 3.2 μm × 5.4
In the case of a μm transistor, the conventional bipolar transistor had a collector resistance of about 100Ω and a collector-substrate capacitance of about 5 PF, but the bipolar transistor of this embodiment has a collector resistance of about 60Ω and a collector-substrate capacitance. Can be reduced to about 1 PF.

When a diffusion layer is used for the collector extraction layer 4 as in the conventional bipolar transistor as shown in FIG. 16, it is necessary to diffuse the impurities to at least the thickness of the collector epitaxial layer 3 so that the impurity concentration of the substrate is increased. On the surface, the diffusion layer spreads in the plane direction about twice the thickness of the collector epitaxial layer 3, and
In order to maintain the breakdown voltage and the like with respect to the collector extraction layer 4, it is necessary to secure a certain distance from other diffusion layers, which has been a major obstacle in downsizing the semiconductor device. In the second groove 34a
The collector extraction electrode 34 is formed by the groove type electrode in which the second barrier metal layer 34b and the second refractory metal layer are embedded in
The width of the second groove 34a can be made smaller than that of the collector extraction layer 4 formed of the diffusion layer by forming
Further, since it is not necessary to secure a constant distance from other diffusion layers, it is possible to reduce the size of the device.

Next, a method of manufacturing the bipolar transistor in this embodiment will be described with reference to FIGS. 2 to 9 are manufacturing process sectional views sequentially showing the manufacturing process of the bipolar transistor.

First, as shown in FIG. 2, the specific resistance is 1
In the N-type semiconductor substrate 1 of Ω · cm, for example, a depth of about 1 μm is formed in a predetermined region where the collector extraction electrode 34 is formed.
A second groove 34a of m is formed, and a second barrier metal layer 34b made of a TiN film is deposited on the peripheral wall of the second groove 34a and the surface of the semiconductor substrate 1 by a sputtering method or a CVD method. Then, a second refractory metal layer 34c made of refractory metal such as a W film is deposited by about 1.5 μm.
The inside of the second groove 34a is filled with the second refractory metal layer 34c.

Next, the second refractory metal layer 34c and the second refractory metal layer 34c
Of the barrier metal layer 34b is etched back to leave the second refractory metal layer 34c and the second barrier metal layer 34b only in the second groove 34a, and then the first refractory metal layer 34b is formed on the surface of the semiconductor substrate 1 again. A TiN film which is a barrier metal layer 32b and a W film which is a first refractory metal layer 32a are sequentially deposited to a thickness of about 0.1 μm and about 0.5 μm to form a collector burying metal layer 32. Then, a CVD oxide film having a thickness of about 1 μm is deposited by the CVD method to form a collector-embedded insulating layer 31.

At this time, the second refractory metal layer 34c is formed.
Although the flatness of the second groove 34a on the second groove 34a is inferior to that of the above method, and the adhesion force of wafer bonding in a later step is reduced,
Second barrier metal layer 34b and second refractory metal layer 3
It is also possible to leave 4c on the semiconductor substrate 1 without being etched back and use it as the collector-embedded metal layer 32.

Next, as shown in FIG.
(Silicon on Insulator) The semiconductor substrate 1 and the supporting substrate 30 are bonded to each other by using a bonding technique used for manufacturing a wafer. That is, after cleaning the surface of the collector-embedded insulating layer 31 and the surface of the support substrate 30 on the semiconductor substrate 1, the substrates 1 and 30 are stacked at room temperature,
By performing annealing at 1100 ° C. for 2 hours in an oxygen atmosphere, the semiconductor substrate 1 and the supporting substrate 30 are bonded together via the collector-embedded metal layer 32 and the collector-embedded insulating layer 31.

Next, as shown in FIG. 4, the back surface of the bonded substrates on the semiconductor substrate 1 side is formed into a second groove 34a with a second groove.
Barrier metal layer 34b or second refractory metal layer 34c of
To a thin film by grinding or polishing until exposed. Here, for example, when polishing is used, the substrate to be polished is rotated with a specific polishing cloth-abrasive having a large friction coefficient with respect to metal. At this time, the rotating motor current changes according to the coefficient of friction of the material to be polished, so that when the metal is exposed on the substrate surface, the motor current increases, and the end point of polishing can be determined by detecting this motor current. Therefore, the thickness of the semiconductor substrate 1 can be easily processed to the depth 34a of the second groove, and the variation in the thickness of the collector region, which is the thickness of the semiconductor substrate 1 between wafers, can be suppressed. Further, by adjusting the polishing depending on the exposed state of the metal layer of the collector extraction electrode 34 of the semiconductor substrate 1, it is possible to suppress the variation in the thickness of the collector region in the wafer.

Next, as shown in FIG. 5, a thermal oxide film 18 having a thickness of about 50 nm is formed on the semiconductor substrate 1 to be the collector region 33, and then a nitride film 19 having a thickness of about 0.2 μm is deposited. Then, a CVD oxide film 20 having a thickness of about 1 μm is deposited. Next, a resist mask having openings only in the regions to be the element isolation regions 5 is formed by a normal photo-etching technique, and the thermal oxide film 18 and the nitride film 19 and the CVD oxide film 20 are etched. Next, using this CVD oxide film 20 as a mask,
The collector region 33 and the collector-buried metal layer 32 are etched, and the first trench 5a reaching the collector-buried insulating layer 31 is opened.

Next, as shown in FIG. 6, heat treatment is performed in a steam atmosphere to form a thermal oxide film (not shown) of about 0.1 μm around the first groove 5a.
This thermal oxidation is sacrificial oxidation for removing the etching damage of the first groove 5a. Next, after removing the thermal oxide film, a CVD oxide film 5d having a thickness of about 0.1 μm is deposited, and then a filling material 5 such as a polysilicon film or a CVD oxide film is deposited.
After thickly depositing c of 1.6 μm, for example, an etch-back method is performed to fill the first groove 5a with the filling material 5c. At this time, the nitride film 19 protects the surface of the filling material 5c during the etching back. If the filling material 5c is a CVD oxide film, CV
It is not necessary to provide the D oxide film 5d. Next, the nitride film 1
9 and the thermal oxide film 18 are sequentially removed to complete the element isolation region 5. In the element isolation region 5, the channel cut region is not necessary because the bottom of the first groove 5a reaches the collector buried insulating layer 31.

Then, a field oxide film 6 having a thickness of about 0.5 μm is formed by a thermal oxidation method or a CVD method.

The subsequent steps shown in FIGS. 7 to 9 are as follows.
This is exactly the same as the method of manufacturing the conventional bipolar transistor shown in FIGS.

In the above-described bipolar transistor manufacturing method, the collector extraction electrode 34 is formed on the semiconductor substrate 1.
After being formed, the collector region 33 is bonded to the support substrate 30 and polished or etched from the back surface of the semiconductor substrate 1 until the collector extraction electrode 34 is exposed.
Can be accurately controlled and the end point of polishing or etching can be easily determined by knowing the exposed state of the collector extraction electrode 34.

Although the adhesion between Si forming the collector region 33 and W forming the refractory metal layers 32a and 34c is weak, the collector region 33 and the first refractory metal layer 32a are not formed.
By providing a first barrier metal layer 32b at the interface with the second barrier metal layer 34b at the interface between the collector region 33 and the second refractory metal layer 34c of the collector extraction electrode 34, Adhesion between the collector region 33 and the refractory metal layers 32a and 34c is improved to prevent the semiconductor substrate 1 and the refractory metal layer 32a from peeling off during the wafer process, and to prevent W and Si from being formed during the heat treatment in the subsequent process. It has the effect of suppressing the reaction and preventing the deterioration of the resistance of the device.

In this embodiment, TiN is used as the material for the barrier metal layers 32b and 34b. However, the material is not limited to TiN, nitrides of transition metals, carbides and borides. , And a silicide film or the like.

Further, although the first refractory metal layer 32a of the collector-embedded metal layer 32 is made of a W film and the first barrier metal layer 32b is made of a TiN film in this embodiment, the refractory metal is mentioned. It goes without saying that the collector-embedded metal layer 32 is not limited to the W film, and may have a single-layer structure made of a silicide film or the like. Further, when the silicide film is used as described above, a third barrier metal layer such as a TiN film is further formed at the interface between the silicide film to be the collector buried metal layer 32 and the collector buried insulating layer 31. Adhesion can be improved as compared with the case of a single layer of a silicide film. Further, in the first embodiment, the collector-buried insulating layer 31 is deposited on the collector-buried metal layer 32 on the semiconductor substrate 1 and then bonded to the supporting substrate 30, but the collector-buried insulating layer is provided on the supporting substrate 30. After depositing 31, the semiconductor substrate 1 may be attached.

Embodiment 2 FIG. A method of manufacturing a bipolar transistor, which is Embodiment 2 of the present invention, will be described with reference to FIG. FIG. 10 is a top view showing one step of the method for manufacturing the bipolar transistor of the second embodiment, in which the first refractory metal layer 32a which is the collector-embedded metal layer 32 and the first barrier metal layer 32b are sequentially deposited. The steps up to are the same as in Example 1.

Next, as shown in FIG. 10, after applying a resist on the entire surface of the semiconductor substrate 1, only the ineffective region 35, which is a region on the outermost periphery of the semiconductor substrate 1 where no element is formed, is exposed and developed. After removing the resist in the ineffective region 35 by etching with the resist as a mask, the first refractory metal layer 32a and the first barrier metal layer 32b in the ineffective region 35 are left, leaving the effective region 36 in which elements are formed. After the removal, the resist is removed. The step of removing the resist in the invalid area 35 can also be performed by dropping the rinse liquid on the invalid area 35.

Next, C, which becomes the collector-embedded insulating layer 31, is formed.
A VD oxide film is deposited on the entire surface. As a result, in the invalid region 35 of the semiconductor substrate 1, the CVD is performed on the silicon.
Since the oxide film is directly deposited, the collector-buried metal layer 32 on the effective region 36 is covered with the collector-buried insulating layer 31 formed in the entire regions 35 and 36. Therefore, the semiconductor substrate 1 and the collector-embedded metal layer 32 are
It is possible to improve the adhesion to the semiconductor substrate 1 and to prevent the collector embedded metal layer 32 from peeling off during the wafer process.

The steps after forming the collector-embedded insulating layer 31 are exactly the same as those in the first embodiment.

Example 3. In the semiconductor device manufacturing method according to the third embodiment of the present invention, the collector-embedded metal layer 32 is used.
To a desired pattern and removing the collector-embedded metal layer 32 in regions 37 other than those required, to form the collector-embedded metal layer 32 into a small pattern, and the collector-embedded insulating layer 31 is formed on this small pattern.
And the collector-embedded metal layer 32 is covered, the adhesion is further improved as compared with the second embodiment.

Next, a method of manufacturing this semiconductor device will be described below with reference to FIGS. 11 to 13 are sectional views of manufacturing steps sequentially showing the method of manufacturing the bipolar transistor of this embodiment.

First, as shown in FIG. 11, as described in Example 1 above, after the collector-buried metal layer 32 is formed, a photoresist is applied to the entire surface, and the photoresist is exposed and developed using a photomask to collect the collector. A region 37 which does not require the buried metal layer 32, in this figure, a region 37 where the element isolation region 5 is to be formed is removed. That is, the collector-buried metal layer 32 is patterned into a desired pattern formed in a region required by the collector-buried metal layer 32. After that, CV is formed on the collector-embedded metal layer 32 by the CVD method.
A collector buried insulating layer 31 made of a D oxide film is formed. Therefore, the collector-embedded metal layer 32 having a desired pattern is covered with the collector-embedded insulating layer 31, the adhesion between the semiconductor substrate 1 and the collector-embedded metal layer 32 is improved, and peeling during the process is prevented. Subsequent steps shown in FIGS. 12 to 15 are exactly the same as the steps shown in FIGS. 1 to 9 described in the previous embodiment.

Also, in this embodiment, the region where the collector-buried metal layer 32 is to be removed in the region where the element isolation region 5 is to be formed is formed slightly smaller than the element isolation region in consideration of the pattern shift.

[0061]

In the semiconductor device according to the first aspect of the present invention, since the collector burying layer and the collector extraction electrode are formed of the refractory metal layer and the silicide film, the collector resistance and the parasitic capacitance between the collector substrates are reduced. There is an effect that it is possible to obtain a semiconductor device that can be reduced, has excellent high frequency characteristics, and operates at high speed with low power consumption.

Further, in the semiconductor device according to the second aspect of the present invention, since the collector-buried metal layer is separated by the element isolation region, the number of manufacturing steps can be reduced.

Further, in the semiconductor device according to claim 3 of the present invention, the collector-buried metal layer and the collector region,
Alternatively, since the barrier metal layer is formed at the interface between the collector-embedded metal layer and the collector-embedded insulating layer, or the collector lead-out electrode and the collector region, the adhesion is improved and the collector-embedded metal layer and the collector lead-out electrode are separated. And the yield of semiconductor devices can be improved.

In the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, the end point can be easily determined in the step of thinning the first semiconductor substrate to be the collector region, and the thickness of the collector region can be accurately controlled. It has the effect that it can be formed well.

Further, in the method of manufacturing a semiconductor device according to claim 5 of the present invention, the metal layer in the outer peripheral region of the first semiconductor substrate on which the element is not formed is removed, and the collector-buried metal layer is formed of an insulating layer. By covering, the adhesiveness of the collector-buried metal layer can be improved, peeling can be prevented during the process, and the yield of semiconductor devices can be improved.

Further, in the method of manufacturing a semiconductor device according to claim 6 of the present invention, since the collector-buried metal layer is formed into a desired small pattern and is covered with an insulating layer, the adhesion is further improved. There is an effect that peeling can be prevented and the yield of semiconductor devices can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device that is Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step in the semiconductor device fabrication method of the first embodiment of the present invention.

FIG. 10 is a top view showing a step of the method of manufacturing the semiconductor device which is Embodiment 2 of the present invention.

FIG. 11 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 16 is a sectional view showing a configuration of a conventional semiconductor device.

FIG. 17 is a cross-sectional view showing a step in the conventional semiconductor device manufacturing method.

FIG. 18 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device.

FIG. 20 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device.

FIG. 21 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device.

FIG. 22 is a cross-sectional view showing a step in the conventional semiconductor device manufacturing method.

FIG. 23 is a cross-sectional view showing a step in the conventional semiconductor device manufacturing method.

[Explanation of symbols]

1 semiconductor substrate, 5 element isolation regions, 5c filler, 5
d CVD oxide film, 30 support substrate, 31 collector buried insulating layer, 32 collector buried metal layer, 32a first refractory metal layer, 32b first barrier metal layer, 3
3 collector region, 34 collector extraction electrode, 34a
Second groove, 34b second barrier metal layer, 34c
Second refractory metal layer, 35 ineffective region, 36 effective region.

Claims (6)

[Claims] 1. A collector-buried insulating layer made of an insulator formed on a substrate, a collector-buried metal layer made of a refractory metal layer or a silicide film formed on the surface of the collector-buried insulating layer, and a collector-buried metal layer. A refractory metal layer or a silicide film is embedded in a collector region formed on the surface of the metal layer and a trench formed through the collector region, and electrically connected to the collector-embedded metal layer at the bottom of the trench. A semiconductor device, comprising: 2. A device isolation region formed by burying an insulator in a trench that penetrates the collector region and the collector-buried metal layer and reaches the collector-buried insulating layer. Semiconductor device. 3. A barrier metal layer is provided at the interface between the collector-buried metal layer and the collector region, at the interface between the collector-buried metal layer and the collector-buried insulating layer, or at the interface between the collector extraction electrode and the collector region. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 4. A step of forming a groove in a first semiconductor substrate and burying a refractory metal layer or a silicide film in the groove,
A step of depositing a collector-embedded metal layer made of a refractory metal layer or a silicide film on the surface of the first semiconductor substrate in which the groove is formed; and an insulating layer on the collector-embedded metal layer or the second semiconductor substrate. A step of depositing, a step of adhering the collector-buried metal layer formed on the first semiconductor substrate via the insulating layer so that one main surface of the second semiconductor substrate faces each other, 2. A method of manufacturing a semiconductor device, comprising the step of etching the back surface of the semiconductor substrate to form a thin film until the refractory metal layer or the silicide film in the groove is exposed to form a collector region. 5. A step of forming a groove in the first semiconductor substrate and burying a refractory metal layer or a silicide film in the groove,
A step of depositing a collector-buried metal layer made of a refractory metal layer or a silicide film on the surface of the first semiconductor substrate in which the groove is formed; A step of removing the buried metal layer, a step of depositing an insulating layer on the first semiconductor substrate or the second semiconductor substrate after the step of removing the collector buried metal layer, and a step of depositing the insulating layer via the insulating layer. The collector-buried metal layer formed on the first semiconductor substrate and the second
And a step of laminating the semiconductor substrate so that the main surfaces thereof face each other, and the back surface of the first semiconductor substrate is etched to form a thin film until the refractory metal layer or the silicide film in the groove is exposed to form a collector region. A method of manufacturing a semiconductor device, comprising: 6. A step of forming a groove in the first semiconductor substrate and burying a refractory metal layer or a silicide film in the groove,
A step of depositing a collector-buried metal layer made of a refractory metal layer or a silicide film on the surface of the first semiconductor substrate in which the groove is formed, and a collector-buried metal layer on the first semiconductor substrate having a desired pattern. Patterning step, depositing an insulating layer on the surface of the first semiconductor substrate or the surface of the second semiconductor substrate on which the desired pattern is formed, and the first semiconductor substrate via the insulating layer A step of adhering the collector-embedded metal layer formed above to the one main surface of the second semiconductor substrate so as to face each other; and etching the back surface of the first semiconductor substrate to form a refractory metal layer in the groove or And a step of forming a collector region by thinning the silicide film until it is exposed.