CN117832254A - GaN-based HEMT device and manufacturing method - Google Patents
GaN-based HEMT device and manufacturing method Download PDFInfo
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- CN117832254A CN117832254A CN202211197566.9A CN202211197566A CN117832254A CN 117832254 A CN117832254 A CN 117832254A CN 202211197566 A CN202211197566 A CN 202211197566A CN 117832254 A CN117832254 A CN 117832254A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 18
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- 229910002704 AlGaN Inorganic materials 0.000 claims description 11
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 47
- 229910002601 GaN Inorganic materials 0.000 description 46
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Manufacturing & Machinery (AREA)
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Abstract
The invention provides a GaN-based HEMT device and a manufacturing method thereof, wherein the method comprises the following steps: forming an epitaxial lamination on a substrate, forming a grid electrode, a drain electrode and a source electrode on the epitaxial lamination, forming a shielding ring layer surrounding an active region of a device on the substrate, forming a first metal interconnection layer and a second metal interconnection layer to realize short circuit of the substrate and the source electrode, forming a passivation protection layer on the second metal interconnection layer, and forming a source electrode and substrate sharing bonding pad, a drain electrode bonding pad and a grid electrode bonding pad based on the second metal interconnection layer and the passivation protection layer. According to the GaN-based HEMT device and the manufacturing method, the substrate is in short connection with the source electrode of the device through the formation of the interconnection structure in the chip, the substrate is grounded without being independently arranged, the ratio of the source electrode pad to the drain electrode pad to the area of the chip is improved, the current conduction capacity is improved, parasitic parameters are further reduced, the current distribution uniformity is improved, the heat distribution of the device is improved, and the reliability of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a GaN-based HEMT device and a manufacturing method thereof.
Background
The third generation semiconductor material gallium nitride (GaN) is an ideal candidate material for high-voltage and high-frequency application because of the wider forbidden bandwidth and higher electron saturation velocity. The gallium nitride semiconductor has an ultrahigh critical breakdown electric field, can realize higher power density, is very suitable for manufacturing a High Electron Mobility Transistor (HEMT), and has the advantages of high voltage resistance, high frequency, high speed, low on-resistance and the like.
The structure of a conventional GaN-based HEMT device is schematically shown in fig. 1, a GaN layer 2' and an AlGaN layer 3' are formed on a substrate 1' to form an AlGaN/GaN heterojunction, and a source electrode 4', a gate electrode 5' and a drain electrode 6' are formed on the AlGaN/GaN heterojunction, wherein contact regions of the source electrode 4' and the drain electrode 6' and the AlGaN/GaN heterojunction are ohmic contact regions 7'. In order to improve the anti-electromagnetic interference capability of the device and ensure that the advantage of the GaN-based device in high frequency and high power density can be effectively exerted in system application, a structure of adding a shielding ring around an active area of a front device of a Si substrate is proposed in patent, as shown in fig. 2, the structure comprises a substrate 1', a buffer layer 8', a HEMT layer 9', a source electrode 4', a grid electrode 5', a drain electrode 6' and a shielding ring 10', and the GaN-based device added with the shielding ring 10' needs to be welded to a PCB 11' in a flip-chip manner during packaging, so that parasitic inductance is minimized, and a packaging scheme is shown in fig. 3. As shown in fig. 4, the planar layout of the device PAD (PAD) is shown that the shielding ring 10 'is disposed in the active region of the chip edge 17', the substrate PAD 13 'is connected to the shielding ring 10', and the source PAD 14', the gate PAD 15', the drain PAD 16 'and the substrate PAD 13' are isolated by an insulating layer, wherein the substrate needs to be individually grounded to the substrate ground electrode 12 'through the substrate PAD 13', which occupies a larger chip area, and is a disadvantage for a GaN-based device with high current density.
Therefore, how to provide a GaN-based HEMT device and a manufacturing method thereof, so as to solve the problems that in the prior art, the GaN-based device needs to be separately arranged, the substrate bonding pad is grounded, and a larger chip area is occupied, which is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing a GaN-based HEMT device and a manufacturing method thereof, so as to solve the problems in the prior art that the GaN-based device needs to be individually arranged with a substrate pad to be grounded, and occupies a larger chip area.
To achieve the above and other related objects, the present invention provides a method for manufacturing a GaN-based HEMT device, including the steps of:
providing a substrate, forming an epitaxial lamination on the substrate, and forming a grid electrode, a source electrode and a drain electrode on the epitaxial lamination;
forming a first dielectric layer above the epitaxial stack, wherein the first dielectric layer covers the gate, the source and the drain, and a first conductive connecting column is formed in the first dielectric layer, penetrates through the first dielectric layer in the vertical direction and is connected with the top surface of the source;
forming an annular groove which penetrates through the first dielectric layer and the epitaxial lamination and extends to the surface of the substrate, wherein the grid electrode, the source electrode and the drain electrode are all located in a region surrounded by the annular groove;
forming a first metal interconnection layer above the first dielectric layer, wherein the first metal interconnection layer is connected with the top surface of the first conductive connecting column, a shielding ring layer is formed on the side wall of the inner side of the annular groove, the top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring extends to the surface of the substrate;
forming a second dielectric layer above the first dielectric layer and the substrate, wherein the second dielectric layer covers the first metal interconnection layer and the shielding ring layer, and a second conductive connecting column and a third conductive connecting column are formed in the second dielectric layer, the second conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the first metal interconnection layer, and the third conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the shielding ring layer;
forming a second metal interconnection layer above the second dielectric layer, wherein the second metal interconnection layer comprises an interconnection structure, and the interconnection structure is connected with the top ends of the second conductive connecting columns and the top ends of the third conductive connecting columns;
forming a passivation protection layer on the second metal interconnection layer, and forming a first opening, a second opening and a third opening in the passivation protection layer, wherein the part of the second metal interconnection layer exposed by the first opening is used as a source electrode and substrate sharing bonding pad, the part of the second metal interconnection layer exposed by the second opening is used as a drain electrode bonding pad, and the part of the second metal interconnection layer exposed by the third opening is used as a gate electrode bonding pad.
Optionally, the shielding ring layer is stepped.
Optionally, the area of the source and substrate sharing pad is larger than the area of the gate pad, and the area of the drain pad is larger than the area of the gate pad.
Optionally, the top surface of the shielding ring layer is flush with the top surface of the first metal interconnection layer.
Optionally, the epitaxial stack includes a GaN channel layer and an AlGaN barrier layer on the GaN channel layer.
The invention also provides a GaN-based HEMT device, which comprises:
a substrate;
an epitaxial stack on the substrate;
the grid electrode, the source electrode and the drain electrode are positioned on the epitaxial lamination;
the first dielectric layer is positioned on the epitaxial lamination, the first dielectric layer covers the grid electrode, the source electrode and the drain electrode, a first conductive connecting column is arranged in the first dielectric layer, and the first conductive connecting column penetrates through the first dielectric layer in the vertical direction and is connected with the top surface of the source electrode;
the first metal interconnection layer is positioned on the first dielectric layer and is connected with the top surface of the first conductive connecting column;
the shielding ring layer is positioned at the outer side of an active region formed by the grid electrode, the source electrode and the drain electrode, the top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring layer extends to the surface of the substrate;
the second dielectric layer is positioned on the first dielectric layer and the substrate, the second dielectric layer coats the first metal interconnection layer and the shielding ring layer, a second conductive connecting column and a third conductive connecting column are arranged in the second dielectric layer, the second conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the first metal interconnection layer, and the third conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the shielding ring layer;
the second metal interconnection layer is positioned on the second dielectric layer and comprises an interconnection structure, and the interconnection structure is connected with the top ends of the second conductive connecting columns and the top ends of the third conductive connecting columns;
the passivation protection layer is positioned on the second metal interconnection layer, a first opening, a second opening and a third opening are arranged in the passivation protection layer, the part of the second metal interconnection layer exposed by the first opening is used as a source electrode and substrate sharing bonding pad, the part of the second metal interconnection layer exposed by the second opening is used as a drain electrode bonding pad, and the part of the second metal interconnection layer exposed by the third opening is used as a gate electrode bonding pad.
Optionally, the shielding ring layer is stepped.
Optionally, the area of the source and substrate sharing pad is larger than the area of the gate pad, and the area of the drain pad is larger than the area of the gate pad.
Optionally, the top surface of the shielding ring layer is flush with the top surface of the first metal interconnection layer.
Optionally, the epitaxial stack includes a GaN channel layer and an AlGaN barrier layer on the GaN channel layer.
As described above, in the GaN-based HEMT device and the manufacturing method thereof, the substrate and the source electrode of the device are in short circuit by forming the interconnection structure in the chip, the substrate bonding pad is not required to be arranged independently to realize the grounding of the silicon substrate, and the occupation ratio of the source electrode bonding pad and the drain electrode bonding pad to the area of the chip is improved; the area ratio of the source electrode and the drain electrode is increased, so that the current conduction capability can be improved, parasitic parameters can be further reduced, the current distribution uniformity can be improved, the heat distribution of the device can be improved, and the reliability of the device can be improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional GaN-based HEMT device.
Fig. 2 is a schematic structural diagram of a GaN-based HEMT device with a shielding ring.
Fig. 3 shows a schematic package diagram of a GaN-based HEMT device with a shield ring.
Fig. 4 shows a plan layout of a bonding pad of a GaN-based HEMT device with a shield ring.
Fig. 5 is a process flow diagram of a method of fabricating a GaN-based HEMT device of the invention.
Fig. 6 is a schematic diagram illustrating an epitaxial stack formed on a substrate and a gate, a source and a drain formed on the epitaxial stack in the method for manufacturing a GaN-based HEMT device of the present invention.
Fig. 7 is a schematic diagram illustrating a first dielectric layer formed on an epitaxial stack and a first conductive connection post formed in the first dielectric layer in the method for manufacturing a GaN-based HEMT device of the present invention.
Fig. 8 is a schematic diagram illustrating formation of a ring-shaped trench in the method for manufacturing a GaN-based HEMT device of the invention.
Fig. 9 is a schematic diagram illustrating formation of a first metal interconnection layer and a shielding ring layer in the method for manufacturing a GaN-based HEMT device of the present invention.
Fig. 10 is a schematic diagram illustrating formation of a second dielectric layer and formation of a second conductive connection pillar and a third conductive connection pillar in the second dielectric layer in the method for manufacturing a GaN-based HEMT device of the present invention.
Fig. 11 is a schematic diagram illustrating a second metal interconnection layer formed on a second dielectric layer in the manufacturing method of the GaN-based HEMT device of the invention.
Fig. 12 shows a plan layout of a bonding pad of the GaN-based HEMT device of the invention.
Description of element reference numerals
1' substrate
2' GaN layer
3' AlGaN layer
4' source electrode
5' grid electrode
6' drain electrode
7' ohmic contact region
8' buffer layer
9' HEMT layer
10' shielding ring
11' PCB board
12' substrate grounding electrode
13' substrate pad
14' source pad
15' gate pad
16' drain electrode bonding pad
17' chip edge
1. Substrate and method for manufacturing the same
2. Epitaxial lamination
200. Buffer layer
201 HEMT layer
3. Grid electrode
4. Source electrode
5. Drain electrode
6. Insulating layer
7. A first dielectric layer
8. First conductive connecting column
9. Annular groove
10. Shielding ring layer
11. First metal interconnection layer
12. A second dielectric layer
13. Second conductive connecting column
14. Third conductive connecting column
15. Second metal interconnection layer
150. Interconnect structure
16. Source and substrate sharing pad
17. Drain electrode bonding pad
18. Gate pad
19. Chip edge
S1 to S7 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The embodiment provides a method for manufacturing a GaN-based HEMT device, referring to FIG. 5, which is a process flow chart of the method, and includes the following steps:
s1: providing a substrate, forming an epitaxial lamination on the substrate, and forming a grid electrode, a source electrode and a drain electrode on the epitaxial lamination;
s2: forming a first dielectric layer above the epitaxial stack, wherein the first dielectric layer covers the gate, the source and the drain, and a first conductive connecting column is formed in the first dielectric layer, penetrates through the first dielectric layer in the vertical direction and is connected with the top surface of the source;
s3: forming an annular groove which penetrates through the first dielectric layer and the epitaxial lamination and extends to the surface of the substrate, wherein the grid electrode, the source electrode and the drain electrode are all located in a region surrounded by the annular groove;
s4: forming a first metal interconnection layer above the first dielectric layer, wherein the first metal interconnection layer is connected with the top surface of the first conductive connecting column, a shielding ring layer is formed on the side wall of the inner side of the annular groove, the top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring extends to the surface of the substrate;
s5: forming a second dielectric layer above the first dielectric layer and the substrate, wherein the second dielectric layer covers the first metal interconnection layer and the shielding ring layer, and a second conductive connecting column and a third conductive connecting column are formed in the second dielectric layer, the second conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the first metal interconnection layer, and the third conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the shielding ring layer;
s6: forming a second metal interconnection layer above the second dielectric layer, wherein the second metal interconnection layer comprises an interconnection structure, and the interconnection structure is connected with the top ends of the second conductive connecting columns and the top ends of the third conductive connecting columns;
s7: forming a passivation protection layer on the second metal interconnection layer, and forming a first opening, a second opening and a third opening in the passivation protection layer, wherein the part of the second metal interconnection layer exposed by the first opening is used as a source electrode and substrate sharing bonding pad, the part of the second metal interconnection layer exposed by the second opening is used as a drain electrode bonding pad, and the part of the second metal interconnection layer exposed by the third opening is used as a gate electrode bonding pad.
First, referring to fig. 6, step S1 is performed: a substrate 1 is provided, an epitaxial stack 2 is formed on the substrate, and a gate 3, a source 4 and a drain 5 are formed on the epitaxial stack 2.
As an example, the substrate 1 may be any suitable semiconductor material, and in this embodiment, a silicon wafer is used as the substrate 1.
As an example, the epitaxial stack 2 comprises a buffer layer 200 and a HEMT layer 201 located above the buffer layer 200, the HEMT layer 201 comprising a GaN channel layer and an AlGaN barrier layer located above the GaN channel layer.
By way of example, the method of forming the epitaxial stack 2 includes physical vapor deposition, chemical vapor deposition, or other suitable method.
As an example, the method for forming the gate electrode 3, the source electrode 4 and the drain electrode 5 on the epitaxial stack 2 includes:
a gate metal layer is formed on the epitaxial layer stack 2, then a mask layer is formed on the gate metal layer and patterned, and a preset area of the gate metal layer is etched based on the patterned mask layer to form a gate electrode 3.
As an example, the material of the gate metal layer may be any suitable gate material, preferably TiN in this embodiment.
And secondly, forming an insulating layer 6 on the epitaxial lamination layer 2, and then etching the insulating layer 6 to a preset depth at a preset position of the insulating layer 6 to form a source groove and a drain groove.
As an example, the material of the insulating layer 6 includes silicon nitride, silicon dioxide, aluminum oxide or other suitable insulating materials, and in this embodiment, silicon nitride is preferred.
And thirdly, forming a source-drain metal layer above the insulating layer 6, wherein the source-drain metal layer covers the insulating layer 6, the source groove and the drain groove, then forming a mask layer above the source-drain metal layer and patterning, etching out the preset position of the source-drain metal layer based on the patterned mask layer, forming a source electrode 4 at the source groove, forming a drain electrode 5 at the drain groove, and isolating the grid electrode 3, the source electrode 4 and the drain electrode 5 through the insulating layer 6.
As an example, the source-drain metal layer may have a single-layer structure or a multi-layer composite laminated structure, and in this embodiment, the source-drain metal layer has a laminated structure of a Ti layer, an Al layer, a Ti layer, and a TiN layer.
As an example, after forming the source electrode 4 and the drain electrode 5, a step of rapid annealing is further included, through which a source ohmic contact and a drain ohmic contact are formed.
In some other embodiments, the preparation sequence of the source electrode, the drain electrode and the gate electrode can be selected according to practical situations, for example, the source electrode and the drain electrode can be prepared first, and then the gate electrode can be prepared; or the source electrode, the drain electrode and the gate electrode are prepared simultaneously, which is not limited by the embodiment.
Next, referring to fig. 7, step S2 is performed: a first dielectric layer 7 is formed over the epitaxial stack 2, the first dielectric layer 7 covers the gate electrode 3, the source electrode 4 and the drain electrode 5, and a first conductive connection post 8 is formed in the first dielectric layer 7, and the first conductive connection post 8 penetrates through the first dielectric layer 7 in a vertical direction and is connected to a top surface of the source electrode 4.
By way of example, the first dielectric layer 7 is prepared using existing deposition processes including, but not limited to, silicon oxide.
As an example, the method of forming the first conductive connection post 8 includes forming a via hole in the first dielectric layer 7 by etching, laser drilling, or other suitable method, and then filling a conductive metal in the via hole to form the first conductive connection post 8.
Next, referring to fig. 8, step S3 is performed: an annular trench 9 is formed, the annular trench 9 penetrates through the first dielectric layer 7 and the epitaxial stack 2 and extends to the surface of the substrate 1, and the gate electrode 3, the source electrode 4 and the drain electrode 5 are all located in a region surrounded by the annular trench 9.
As an example, in actual manufacturing, a semiconductor device is typically composed of a plurality of semiconductor cells, one of which includes one of the source electrodes 4, one of the drain electrodes 5, the gate electrode 3 between the source electrode 4 and the drain electrode 5, and the corresponding active region thereof. In this embodiment, when a plurality of semiconductor unit cell arrays form a semiconductor device, adjacent semiconductor unit cells share the source electrode 4 or the drain electrode 5.
As an example, the preset positions of the first dielectric layer 7 and the epitaxial stack 2 are etched away by dry etching or wet etching, and further comprising etching away the preset positions of the insulating layer 6 to form the annular trench 9.
As an example, the annular groove 9 is stepped to form a stepped shield ring layer 10 later (see fig. 9 later).
Next, referring to fig. 9, step S4 is performed: a first metal interconnection layer 11 is formed above the first dielectric layer 7, the first metal interconnection layer 11 is connected with the top surface of the first conductive connection post 8, a shielding ring layer 10 is formed on the side wall of the inner side of the annular groove 9, the top end of the shielding ring layer 10 extends to the top surface of the first dielectric layer 7, and the bottom end of the shielding ring layer 10 extends to the surface of the substrate 1.
As an example, the material of the first metal interconnection layer 11 includes copper, aluminum, nickel, gold, silver, titanium or other suitable conductive material, and is formed by deposition, electroplating or other suitable process, and since the present embodiment provides a plurality of semiconductor cells, the first metal interconnection layer 11 is connected to a plurality of the sources 4 to form a source bus.
By way of example, the material of the shield ring layer 10 may include copper, aluminum, nickel, gold, silver, titanium, or other suitable conductive material, formed by deposition, electroplating, or other suitable process.
As an example, the shielding ring layer 10 is arranged above the substrate 1, the epitaxial stack layer 2 and the first dielectric layer 7 in a step shape, which is beneficial to forming ohmic contact with the substrate 1 and reducing contact resistance.
As an example, the top surface of the shield ring layer 10 is flush with the top surface of the first metal interconnection layer 11.
As an example, the shielding ring layer 10 is annularly arranged in the active region of the GaN-based HEMT device, which plays a role of electromagnetic shielding, improves the capability of anti-electromagnetic interference of the device, and ensures that the advantages of high frequency and high power density of the GaN-based HEMT device are effectively exerted in system application.
Next, referring to fig. 10, step S5 is performed: a second dielectric layer 12 is formed above the first dielectric layer 7 and the substrate 1, the second dielectric layer 12 encapsulates the first metal interconnection layer 11 and the shielding ring layer 10, a second conductive connection column 13 and a third conductive connection column 14 are formed in the second dielectric layer 12, the second conductive connection column 13 penetrates through the second dielectric layer 12 in the vertical direction to be connected with the first metal interconnection layer 11, and the third conductive connection column 14 penetrates through the second dielectric layer 12 in the vertical direction to be connected with the shielding ring layer 10.
By way of example, the second dielectric layer 12 is prepared using existing deposition processes including, but not limited to, silicon oxide.
As an example, the method of forming the second conductive connection post 13 and the third conductive connection post 14 includes forming a via hole in the second dielectric layer 12 using etching, laser drilling, or other suitable method, and then filling a conductive metal in the via hole to form the second conductive connection post 13 and the third conductive connection post 14.
Next, referring to fig. 11, step S6 is performed: a second metal interconnection layer 15 is formed above the second dielectric layer 12, and the second metal interconnection layer 15 includes an interconnection structure 150, where the interconnection structure 150 is connected to the top ends of the second conductive connection pillars 13 and the top ends of the third conductive connection pillars 14.
By way of example, the material of the second metal interconnect layer 15 may include copper, aluminum, nickel, gold, silver, titanium, or other suitable conductive material, formed by deposition, electroplating, or other suitable process.
As an example, after the second metal interconnection layer 15 is formed, the substrate 1 is electrically connected to the source electrode 4 through the shielding ring layer 10, the third conductive connection pillar 14, the interconnection structure 150, the second conductive connection pillar 13, the first metal interconnection layer 11 and the first conductive connection pillar 8, that is, the substrate is directly connected to the source electrode through the manner of interconnection inside the device, and therefore, a substrate pad is not required to be separately provided to realize substrate grounding, so that difficulty of a packaging process is reduced.
Next, step S7 is performed: a passivation protection layer is formed on the second metal interconnection layer 15, and a first opening, a second opening and a third opening are formed in the passivation protection layer, wherein a portion of the second metal interconnection layer 15 exposed by the first opening serves as a source and substrate common pad 16, a portion of the second metal interconnection layer 15 exposed by the second opening serves as a drain pad 17, and a portion of the second metal interconnection layer 15 exposed by the third opening serves as a gate pad 18.
As an example, the second metal interconnection layer 15 includes at least three parts, wherein a first part is the interconnection structure 150, the substrate and source common pad 16 is formed based on the interconnection structure 150, a second part is used to form the drain pad 17, a third part is used to form the gate pad 18, that is, a part of the interconnection structure 150 exposed by the first opening is used as the substrate and source common pad 16, a region of the second part of the second metal interconnection layer 15 exposed by the second opening is used as the drain pad 17, the drain pad 17 is electrically connected to the drain 5, a region of the third part of the second metal interconnection layer 15 exposed by the third opening is used as the gate pad 18, and the gate pad 18 is electrically connected to the gate 3.
As an example, in an ideal case, the opening of the passivation protection layer may be consistent with the second metal interconnection layer 15, but limited by factors such as accuracy and reliability of the packaging process, and a soldering manner, the pad size is smaller than the second metal interconnection layer 15.
As an example, referring to fig. 12, a plan layout diagram of a substrate and source common pad 16, a drain pad 17 and a gate pad 18 of the present embodiment is shown, wherein a shielding ring layer 10 is looped around an active region of a chip edge 19, and the substrate and source common pad 16, the drain pad 17 and the gate pad 18 are located in the active region, because the substrate 1 is connected to the source 4 inside the device, and no separate substrate pad grounding is required.
As an example, compared with the prior art of fig. 4 in which the substrate pad is separately disposed, the area of the source/drain pad occupies about one half of the total pad area, and the present invention is equivalent to "dividing" the area of the substrate pad into the source pad and the drain pad, so that the area of the source/substrate shared pad 16 is larger than the area of the gate pad 18, the area of the drain pad 17 is larger than the area of the gate pad 18, the area of the source/drain pad can reach three-fourths or more of the total pad area, the ratio of the source/drain pad to the chip area is increased, the current conduction capability of the source/drain pad is improved, and the parasitic parameters introduced by the package can be further reduced; and the uniformity of current distribution can be improved, which is beneficial to improving the heat distribution of the device and improving the reliability of the device.
To this end, a GaN-based HEMT device is manufactured, please refer to fig. 11 to 12, which includes a substrate 1, an epitaxial stack layer 2, a gate electrode 3, a source electrode 4, a drain electrode 5, a first dielectric layer 7, a first metal interconnection layer 11, a shielding ring layer 10, a second dielectric layer 12, a second metal interconnection layer 15, and a passivation protection layer, wherein the epitaxial stack layer 2 is located on the substrate 1; the gate electrode 3, the source electrode 4 and the drain electrode 5 are positioned on the epitaxial stack 2; the first dielectric layer 7 is located on the epitaxial stack 2, the first dielectric layer 7 covers the gate 3, the source 4 and the drain 5, a first conductive connection column 8 is disposed in the first dielectric layer 7, and the first conductive connection column 8 penetrates through the first dielectric layer 7 in the vertical direction and is connected with the top surface of the source 4; the first metal interconnection layer 11 is located on the first dielectric layer 7 and connected with the top surface of the first conductive connection post 8; the shielding ring layer 10 is located outside the active region formed by the gate electrode 3, the source electrode 4 and the drain electrode 5, the top end of the shielding ring layer 10 extends to the top surface of the first dielectric layer 7, and the bottom end of the shielding ring layer 10 extends to the surface of the substrate 1; the second dielectric layer 12 is located on the first dielectric layer 7 and the substrate 1, the second dielectric layer 7 encapsulates the first metal interconnection layer 11 and the shielding ring layer 10, a second conductive connection column 13 and a third conductive connection column 14 are disposed in the second dielectric layer 12, the second conductive connection column 13 penetrates through the second dielectric layer 12 in the vertical direction to be connected with the first metal interconnection layer 11, and the third conductive connection column 14 penetrates through the second dielectric layer 12 in the vertical direction to be connected with the shielding ring layer 10; the second metal interconnection layer 15 is located on the second dielectric layer 12, the second metal interconnection layer 15 includes an interconnection structure 150, and the interconnection structure 150 is connected to the top ends of the second conductive connection pillars 13 and the top ends of the third conductive connection pillars 14; the passivation layer is located on the second metal interconnection layer 15, a first opening, a second opening and a third opening are provided in the passivation layer, a portion of the second metal interconnection layer 15 exposed by the first opening is used as a source and substrate shared pad 16, a portion of the second metal interconnection layer 15 exposed by the second opening is used as a drain pad 17, and a portion of the second metal interconnection layer 15 exposed by the third opening is used as a gate pad 18.
As an example, the substrate 1 may be any suitable semiconductor material, and in this embodiment, a silicon wafer is used as the substrate 1.
In this example, the epitaxial stack 2 includes a buffer layer 200 and a HEMT layer 201 over the buffer layer 200, the HEMT layer 201 including a GaN channel layer and an AlGaN barrier layer over the GaN channel layer.
As an example, an insulating layer 6 is further included, the insulating layer 6 being used to isolate the gate electrode 3, the drain electrode 4 and the source electrode 5.
As an example, a semiconductor device is composed of a plurality of semiconductor cells, one of which comprises one of the source electrodes 4, one of the drain electrodes 5, the gate electrode 3 between the source electrode 4 and the drain electrode 5, and its corresponding active region. In this embodiment, when a plurality of semiconductor unit cell arrays form a semiconductor device, adjacent semiconductor unit cells share the source electrode 4 or the drain electrode 5.
As an example, the shielding ring layer 10 is arranged above the substrate 1, the epitaxial stack layer 2 and the first dielectric layer 7 in a step shape, which is beneficial to forming ohmic contact with the substrate 1 and reducing contact resistance.
As an example, the top surface of the shield ring layer 10 is flush with the top surface of the first metal interconnection layer 11.
As an example, the shielding ring layer 10 is annularly arranged in the active region of the GaN-based HEMT device, which plays a role of electromagnetic shielding, improves the capability of anti-electromagnetic interference of the device, and ensures that the advantages of high frequency and high power density of the GaN-based HEMT device are effectively exerted in system application.
As an example, the substrate 1 is electrically connected to the source electrode 4 through the shielding ring layer 10, the third conductive connection pillar 14, the interconnection structure 150, the second conductive connection pillar 13, the first metal interconnection layer 11 and the first conductive connection pillar 8, that is, the substrate is directly connected to the source electrode by means of interconnection inside the device, and substrate grounding is achieved without a separate substrate pad, so that difficulty of a packaging process is reduced.
As an example, the second metal interconnection layer includes at least three parts, wherein a first part is the interconnection structure 150, the substrate and source common pad 16 is disposed based on the interconnection structure 150, a second part is used to dispose the drain pad 17, a third part is used to dispose the gate pad 18, that is, a part of the interconnection structure 150 exposed by the first opening is used as the substrate and source common pad 16, a region of the second part of the second metal interconnection layer 15 exposed by the second opening is used as the drain pad 17, the drain pad 17 is electrically connected to the drain 5, a region of the third part of the second metal interconnection layer 15 exposed by the third opening is used as the gate pad 18, and the gate pad 18 is electrically connected to the gate 3.
As an example, the shielding ring layer 10 is disposed around the active area of the chip edge 19, the substrate and source common pad 16, the drain pad 17 and the gate pad 18 are disposed in the active area, the area of the source and substrate common pad 16 is larger than the area of the gate pad 18, and the area of the drain pad 17 is larger than the area of the gate pad 18.
As an example, compared with the prior art of fig. 4 in which the substrate pad is separately disposed, the area of the source/drain pad occupies about one half of the total pad area, and the method is equivalent to "dividing" the area of the substrate pad into the source pad and the drain pad, wherein the area of the source/drain pad can reach three-fourths or more of the total pad area, the ratio of the source/drain pad to the chip area is improved, the current conduction capability of the source/drain pad is improved, and parasitic parameters introduced by packaging can be further reduced; and the uniformity of current distribution can be improved, which is beneficial to improving the heat distribution of the device and improving the reliability of the device.
In summary, in the GaN-based HEMT device and the manufacturing method of the invention, the substrate and the source electrode of the device are shorted by forming the interconnection structure in the chip, the substrate is not required to be grounded by arranging the substrate bonding pad alone, the ratio of the source electrode bonding pad to the area of the chip is improved, the current conduction capability is improved, the parasitic parameter is further reduced, the current distribution uniformity is improved, the heat distribution of the device is improved, and the reliability of the device is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The manufacturing method of the GaN-based HEMT device is characterized by comprising the following steps of:
providing a substrate, forming an epitaxial lamination on the substrate, and forming a grid electrode, a source electrode and a drain electrode on the epitaxial lamination;
forming a first dielectric layer above the epitaxial stack, wherein the first dielectric layer covers the gate, the source and the drain, and a first conductive connecting column is formed in the first dielectric layer, penetrates through the first dielectric layer in the vertical direction and is connected with the top surface of the source;
forming an annular groove which penetrates through the first dielectric layer and the epitaxial lamination and extends to the surface of the substrate, wherein the grid electrode, the source electrode and the drain electrode are all located in a region surrounded by the annular groove;
forming a first metal interconnection layer above the first dielectric layer, wherein the first metal interconnection layer is connected with the top surface of the first conductive connecting column, a shielding ring layer is formed on the side wall of the inner side of the annular groove, the top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring extends to the surface of the substrate;
forming a second dielectric layer above the first dielectric layer and the substrate, wherein the second dielectric layer covers the first metal interconnection layer and the shielding ring layer, and a second conductive connecting column and a third conductive connecting column are formed in the second dielectric layer, the second conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the first metal interconnection layer, and the third conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the shielding ring layer;
forming a second metal interconnection layer above the second dielectric layer, wherein the second metal interconnection layer comprises an interconnection structure, and the interconnection structure is connected with the top ends of the second conductive connecting columns and the top ends of the third conductive connecting columns;
forming a passivation protection layer on the second metal interconnection layer, and forming a first opening, a second opening and a third opening in the passivation protection layer, wherein the part of the second metal interconnection layer exposed by the first opening is used as a source electrode and substrate sharing bonding pad, the part of the second metal interconnection layer exposed by the second opening is used as a drain electrode bonding pad, and the part of the second metal interconnection layer exposed by the third opening is used as a gate electrode bonding pad.
2. The method for manufacturing the GaN-based HEMT device of claim 1, wherein: the shielding ring layer is in a step shape.
3. The method for manufacturing the GaN-based HEMT device of claim 1, wherein: the area of the source electrode and substrate shared bonding pad is larger than that of the grid bonding pad, and the area of the drain electrode bonding pad is larger than that of the grid bonding pad.
4. The method for manufacturing the GaN-based HEMT device of claim 1, wherein: the top surface of the shielding ring layer is flush with the top surface of the first metal interconnection layer.
5. The method for manufacturing the GaN-based HEMT device of claim 1, wherein: the epitaxial stack includes a GaN channel layer and an AlGaN barrier layer on the GaN channel layer.
6. A GaN-based HEMT device, comprising:
a substrate;
an epitaxial stack on the substrate;
the grid electrode, the source electrode and the drain electrode are positioned on the epitaxial lamination;
the first dielectric layer is positioned on the epitaxial lamination, the first dielectric layer covers the grid electrode, the source electrode and the drain electrode, a first conductive connecting column is arranged in the first dielectric layer, and the first conductive connecting column penetrates through the first dielectric layer in the vertical direction and is connected with the top surface of the source electrode;
the first metal interconnection layer is positioned on the first dielectric layer and is connected with the top surface of the first conductive connecting column;
the shielding ring layer is positioned at the outer side of an active region formed by the grid electrode, the source electrode and the drain electrode, the top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring layer extends to the surface of the substrate;
the second dielectric layer is positioned on the first dielectric layer and the substrate, the second dielectric layer coats the first metal interconnection layer and the shielding ring layer, a second conductive connecting column and a third conductive connecting column are arranged in the second dielectric layer, the second conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the first metal interconnection layer, and the third conductive connecting column penetrates through the second dielectric layer in the vertical direction to be connected with the shielding ring layer;
the second metal interconnection layer is positioned on the second dielectric layer and comprises an interconnection structure, and the interconnection structure is connected with the top ends of the second conductive connecting columns and the top ends of the third conductive connecting columns;
the passivation protection layer is positioned on the second metal interconnection layer, a first opening, a second opening and a third opening are arranged in the passivation protection layer, the part of the second metal interconnection layer exposed by the first opening is used as a source electrode and substrate sharing bonding pad, the part of the second metal interconnection layer exposed by the second opening is used as a drain electrode bonding pad, and the part of the second metal interconnection layer exposed by the third opening is used as a gate electrode bonding pad.
7. The GaN-based HEMT device of claim 6, wherein: the shielding ring layer is in a step shape.
8. The GaN-based HEMT device of claim 6, wherein: the area of the source electrode and substrate shared bonding pad is larger than that of the grid bonding pad, and the area of the drain electrode bonding pad is larger than that of the grid bonding pad.
9. The GaN-based HEMT device of claim 6, wherein: the top surface of the shielding ring layer is flush with the top surface of the first metal interconnection layer.
10. The GaN-based HEMT device of claim 6, wherein: the epitaxial stack includes a GaN channel layer and an AlGaN barrier layer on the GaN channel layer.
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