CN105914133A - Variable doped junction terminal preparation method - Google Patents
Variable doped junction terminal preparation method Download PDFInfo
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- CN105914133A CN105914133A CN201610300050.0A CN201610300050A CN105914133A CN 105914133 A CN105914133 A CN 105914133A CN 201610300050 A CN201610300050 A CN 201610300050A CN 105914133 A CN105914133 A CN 105914133A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 23
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 238000003754 machining Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 9
- 239000007924 injection Substances 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 13
- 238000002513 implantation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004223 radioprotective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention discloses a variable doped junction terminal preparation method. An etching barrier layer is processed on the surface of a dielectric layer to form an echelonment medium morphology and then form the junction terminal of a grading structure through ion implantation. Through strictly controlling the etching speed ratio of two layers of medium, the variable doped junction terminal preparation method realizes step height accurate control and avoids the injection medium film thickness changing caused by etching ratio drifting. The injection dosage of each area of the junction terminal may be accurately controlled, and the number of times of ion injection in the device processing is reduced.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of varying doping knot terminal preparation method.
Background technology
SiC material energy gap is big, breakdown electric field is high, saturation drift velocity and thermal conductivity big, these material superior functions
Become making high power, high frequency, high temperature resistant, the ideal material of radioprotective device.The advantage of carborundum is to make
High tension apparatus, therefore to give full play to its material advantage must improve terminal protection efficiency as far as possible.
The theoretical protective efficacy of knot terminal forms of protection is the highest, uses the blocking-up of the silicon carbide device of junction termination technique
Voltage can be close to theoretical limit.But junction termination technique efficiency is affected very big by doping content and interface charge, especially boundary
The density of surface charge is difficult to accurately control in dielectric growth process.Current solution is to be formed by repeatedly ion implanting
Multiple knot terminals, make the dopant dose in whole terminal protection district from inside to outside be gradually lowered and then obtain higher terminal protection
Efficiency.But such a process increases the number of times of ion implanting.
Summary of the invention
Goal of the invention: it is an object of the invention to provide a kind of varying doping knot terminal preparation side that can reduce ion implanting number of times
Method.
Technical scheme: for reaching this purpose, the present invention by the following technical solutions:
Varying doping of the present invention knot terminal preparation method, comprises the following steps:
S1: grow the first dielectric layer on silicon carbide epitaxial layers；
S2: sequentially formed the dielectric layer of N shell separate unit scalariform on first medium layer, N are positive integer；
Wherein the dielectric layer of the 1st layer of separate unit scalariform is obtained by following steps: grow second dielectric layer on first medium layer,
Go out the first etch stop layer in second dielectric layer Surface Machining, and logical overetched method remove part the first etch stop layer,
The most removed first etch stop layer is still covered by second dielectric layer, then leads to overetched method and removes second medium
The region not covered by the first etch stop layer in Ceng, retains the region covered by the first etch stop layer in second dielectric layer,
Finally remove the first etch stop layer, form the dielectric layer of the 1st layer of separate unit scalariform, thus form the 1st ion implanted region；
Wherein the dielectric layer of i-th layer of separate unit scalariform is obtained by following steps, and 1 < i < N and i is integer: at the i-th medium
Grow i+1 dielectric layer on layer, form the dielectric layer of i-th layer of separate unit scalariform, thus form the i-th ion implanted region；
Wherein the dielectric layer of n-th layer separate unit scalariform is obtained by following steps: growth regulation N+1 medium on N dielectric layer
Layer, processes N etch stop layer at N+1 dielectric layer surface, and logical overetched method removes part N etching
Barrier layer, the most removed N etch stop layer is still covered by N+1 dielectric layer, then leads to overetched method and goes
Except the region not covered by N etch stop layer in N+1 dielectric layer, retain in N+1 dielectric layer by N etching resistance
The region that barrier covers, finally removes N etch stop layer, forms the dielectric layer of n-th layer separate unit scalariform, thus is formed
N ion implanted region.
S3: whole wafer is carried out ion implanting；
S4: remove all of dielectric layer of crystal column surface.
Further, in described step S2, the speed to second dielectric layer etching is 5 of the speed to the etching of first medium layer
More than Bei.
Further, in described step S2, the speed to the etching of N+1 dielectric layer is the speed to the etching of N dielectric layer
More than 5 times.
Further, in described step S2, in the dielectric layer of separate unit scalariform, the angular range of step is 0 °～90 °.
Further, described i-th etch stop layer uses photoresist or metallic film to make as material.
Further, described All Media layer all uses silicon oxide or silicon nitride to make.
Further, described N is 3.
Beneficial effect: the present invention defines stepped medium pattern by repeatedly dielectric growth and etching, then is noted by ion
Enter to define the knot terminal of grading structure.Being precisely controlled of shoulder height is realized by controlling the etch-rate ratio of two layer medium,
Avoid the injected media Thickness Variation caused by etch rate drift.The knot terminal each region implantation dosage realized is permissible
Precisely controlled, and decrease the number of times that device fabrication intermediate ion injects.
Accompanying drawing explanation
Fig. 1 be the present invention detailed description of the invention on silicon carbide epitaxial layers, grow the first dielectric layer after the structure that obtains
Schematic diagram；
Fig. 2 be the present invention detailed description of the invention on first medium layer, grow showing of the structure that obtains after second dielectric layer
It is intended to；
Fig. 3 be the present invention detailed description of the invention in obtain after second dielectric layer Surface Machining goes out the first etch stop layer
The schematic diagram of structure；
Fig. 4 be the present invention detailed description of the invention in remove the schematic diagram of the structure obtained after part the first etch stop layer；
Fig. 5 be the present invention detailed description of the invention in remove the region not covered by the first etch stop layer in second dielectric layer
After the schematic diagram of structure that obtains；
Fig. 6 be the present invention detailed description of the invention in remove the first etch stop layer after the schematic diagram of structure that obtains；
Fig. 7 is showing of the structure that obtains after growth regulation three dielectric layer in second dielectric layer in the detailed description of the invention of the present invention
It is intended to；
Fig. 8 is showing of the structure that obtains after growth regulation four dielectric layer on the 3rd dielectric layer in the detailed description of the invention of the present invention
It is intended to；
Fig. 9 be the present invention detailed description of the invention in obtain after the 4th dielectric layer surface processes the second etch stop layer
The schematic diagram of structure；
Figure 10 be the present invention detailed description of the invention in remove the second etch stop layer after the schematic diagram of structure that obtains；
Figure 11 be the present invention detailed description of the invention in remove the district not covered by the second etch stop layer in the 4th dielectric layer
The schematic diagram of the structure obtained behind territory；
Figure 12 be the present invention detailed description of the invention in remove the second etch stop layer after the schematic diagram of structure that obtains；
Figure 13 be the present invention detailed description of the invention in form the schematic diagram of structure with three ion implanted regions；
Figure 14 be the present invention detailed description of the invention in remove the schematic diagram of the structure obtained after crystal column surface All Media layer；
Figure 15 be the present invention detailed description of the invention in adjust the signal of the structure obtained after step angle in second dielectric layer
Figure；
Figure 16 be the present invention the etching of detailed description of the invention medium after bottom step after residual fraction the 4th dielectric layer
The schematic diagram of the structure arrived；
Figure 17 be the present invention detailed description of the invention in remove after silicon carbide epitaxial layers surface element subregional All Media layer
Carry out the schematic diagram of ion implanting.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical scheme is further elaborated.
The invention discloses a kind of varying doping knot terminal preparation method, comprise the following steps:
S1: grow the first dielectric layer 2 on silicon carbide epitaxial layers 1, as shown in Figure 1；
S2: grow second dielectric layer 3 on first medium layer 2, as shown in Figure 2；In second dielectric layer 3 Surface Machining
Go out the first etch stop layer 4, as it is shown on figure 3, and logical overetched method remove part the first etch stop layer 4, as
Shown in Fig. 4, the most removed first etch stop layer 4 is still covered by second dielectric layer 3, then leads to overetched side
Method removes the region not covered by the first etch stop layer 4 in second dielectric layer 3, as it is shown in figure 5, retain second medium
The region covered by the first etch stop layer 4 in layer 3, finally removes the first etch stop layer 4, as shown in Figure 6, shape
Become the second dielectric layer 3 of separate unit scalariform, namely the dielectric layer of ground floor separate unit scalariform, thus form the first ion implanted region
8, as shown in figure 13；Then, growth regulation three dielectric layer 5 in second dielectric layer 3, as it is shown in fig. 7, form separate unit
3rd dielectric layer 5 of scalariform, namely the dielectric layer of second layer separate unit scalariform, thus form the second ion implanted region 9, as
Shown in Figure 13；Then, growth regulation four dielectric layer 6 on the 3rd dielectric layer 5, as shown in Figure 8, then at the 4th dielectric layer
6 Surface Machining go out the second etch stop layer 7, as it is shown in figure 9, and logical overetched method removal part the second etching resistance
Barrier 7, as shown in Figure 10, the most removed second etch stop layer 7 is still covered by the 4th dielectric layer 6, then leads to
The region not covered by the second etch stop layer 7 in overetched method removal the 4th dielectric layer 6, as shown in figure 11,
Retain the region covered by the second etch stop layer 7 in the 4th dielectric layer 6, finally remove the second etch stop layer 7, as
Shown in Figure 12, form the 4th dielectric layer 6 of separate unit scalariform, namely the dielectric layer of third layer separate unit scalariform, thus form the
Three ion implanted regions 10, as shown in figure 13；
S3: whole wafer is carried out ion implanting；
S4: remove all of dielectric layer of crystal column surface, first ion implanted region the 8, second ion implanted region 9 and the 3rd from
The merging of sub-injection region 10 defines injection region 11, as shown in figure 14.
In step S2, the speed to second dielectric layer 3 etching is more than 5 times to the speed that first medium layer 2 etches,
To ensure that the second dielectric layer 3 part above the first ion implanted region 8 is removed completely, and exact residence is situated between first
On matter layer 2；Speed to the 4th dielectric layer 6 etching is more than 5 times to the speed that the 3rd dielectric layer 5 etches, to protect
Demonstrate,prove the 4th dielectric layer 6 part above the second ion implanted region 9 to remove completely, and exact residence is at the 3rd dielectric layer
On 5.
Owing to second dielectric layer the 3, the 3rd dielectric layer 5 and the 4th dielectric layer 6 are all in separate unit scalariform, namely injection mask is
Separate unit scalariform, the degree of depth causing first ion implanted region the 8, second ion implanted region 9 and the 3rd ion implanted region 10 is each not
Identical.
This varying doping terminal protection implementation method is not limited to realize three grades of steps, can be raw by repeating two-layered medium
Length, mask lithography, high selectivity etching realizes multi-stage stairs formula knot terminal and injects mask, injects finally by single ion
Form the junction termination technique of multistage dopant dose.
Furthermore, it is possible to by adjusting medium engraving method, it is achieved structure as shown in figure 15, namely adjust separate unit scalariform
Second dielectric layer 3 in the angle [alpha] of step so that it is changing in the range of 0 °～90 °, this angle can ensure that
Subsequent medium growth can be good the whole step of covering and make injection region intersection step thicknesses gradual and then make
It is gradual that final injection region 11 intersection injects the degree of depth.
Can also be by adjusting etching condition, it is achieved structure as shown in figure 16, can be residual bottom step after medium etching
Stay part the 4th dielectric layer 6, this part the 4th dielectric layer 6 makes original steep steps become to releive, it is to avoid step
The sudden change between injection region 11 of the precipitous implantation dosage brought.
Can also by medium etching remove except silicon carbide epitaxial layers 1 surface element subregional All Media layer, obtain as
Structure shown in Figure 17, is so capable of the most highly doped dosage by ion implanting gradual equal to implantation dosage and dosage
Knot terminal injecting structure.
Claims (7)
1. a varying doping knot terminal preparation method, it is characterised in that: comprise the following steps:
S1: at silicon carbide epitaxial layers (1) upper growth the first dielectric layer (2)；
S2: sequentially formed the dielectric layer of N shell separate unit scalariform on first medium layer (2), N is positive integer；
Wherein the dielectric layer of the 1st layer of separate unit scalariform is obtained by following steps: in the upper growth second of first medium layer (2)
Dielectric layer (3), goes out the first etch stop layer (4), and logical overetched method in second dielectric layer (3) Surface Machining
Removing part the first etch stop layer (4), the most removed first etch stop layer (4) is still covered by second medium
Layer (3), then leads to overetched method and removes and do not covered by the first etch stop layer (4) in second dielectric layer (3)
Region, retains the region covered by the first etch stop layer (4) in second dielectric layer (3), finally removes the first etching
Barrier layer (4), forms the dielectric layer of the 1st layer of separate unit scalariform, thus forms the 1st ion implanted region；
Wherein the dielectric layer of i-th layer of separate unit scalariform is obtained by following steps, and 1 < i < N and i is integer: at the i-th medium
Grow i+1 dielectric layer on layer, form the dielectric layer of i-th layer of separate unit scalariform, thus form the i-th ion implanted region；
Wherein the dielectric layer of n-th layer separate unit scalariform is obtained by following steps: growth regulation N+1 medium on N dielectric layer
Layer, processes N etch stop layer at N+1 dielectric layer surface, and logical overetched method removes part N etching
Barrier layer, the most removed N etch stop layer is still covered by N+1 dielectric layer, then leads to overetched method and goes
Except the region not covered by N etch stop layer in N+1 dielectric layer, retain in N+1 dielectric layer by N etching resistance
The region that barrier covers, finally removes N etch stop layer, forms the dielectric layer of n-th layer separate unit scalariform, thus is formed
N ion implanted region；
S3: whole wafer is carried out ion implanting；
S4: remove all of dielectric layer of crystal column surface.
Varying doping the most according to claim 1 knot terminal preparation method, it is characterised in that: in described step S2,
The speed etching second dielectric layer (3) is more than 5 times to the speed that first medium layer (2) etches.
Varying doping the most according to claim 1 knot terminal preparation method, it is characterised in that: in described step S2,
Speed to the etching of N+1 dielectric layer is more than 5 times to the speed that N dielectric layer etches.
Varying doping the most according to claim 1 knot terminal preparation method, it is characterised in that: in described step S2,
In the dielectric layer of separate unit scalariform, the angular range of step is 0 °～90 °.
Varying doping the most according to claim 1 knot terminal preparation method, it is characterised in that: described i-th etching resistance
Barrier uses photoresist or metallic film to make as material.
Varying doping the most according to claim 1 knot terminal preparation method, it is characterised in that: described All Media layer
Silicon oxide or silicon nitride is all used to make.
Varying doping the most according to claim 1 knot terminal preparation method, it is characterised in that: described N is 3.
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| CN201610300050.0A CN105914133B (en) | 2016-05-09 | 2016-05-09 | A kind of varying doping knot terminal preparation method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565222A (en) * | 2018-06-15 | 2018-09-21 | 江苏矽导集成科技有限公司 | A kind of variety lateral doping junction termination structures production method of SiC device |
| CN108598150A (en) * | 2018-04-25 | 2018-09-28 | 西安理工大学 | A kind of variety lateral doping-knot terminal extends composite terminal structure and its manufacturing method |
| CN108831920A (en) * | 2018-06-15 | 2018-11-16 | 江苏矽导集成科技有限公司 | A kind of junction termination structures production method of SiC device |
| CN111192821A (en) * | 2018-12-12 | 2020-05-22 | 深圳方正微电子有限公司 | Junction terminal structure of silicon carbide power device, manufacturing method of junction terminal structure and silicon carbide power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108598150A (en) * | 2018-04-25 | 2018-09-28 | 西安理工大学 | A kind of variety lateral doping-knot terminal extends composite terminal structure and its manufacturing method |
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| CN108831920A (en) * | 2018-06-15 | 2018-11-16 | 江苏矽导集成科技有限公司 | A kind of junction termination structures production method of SiC device |
| CN111192821A (en) * | 2018-12-12 | 2020-05-22 | 深圳方正微电子有限公司 | Junction terminal structure of silicon carbide power device, manufacturing method of junction terminal structure and silicon carbide power device |
| CN111192821B (en) * | 2018-12-12 | 2023-04-14 | 深圳方正微电子有限公司 | Junction terminal structure of silicon carbide power device, manufacturing method of junction terminal structure and silicon carbide power device |
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