CN105914133B - A kind of varying doping knot terminal preparation method - Google Patents
A kind of varying doping knot terminal preparation method Download PDFInfo
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- CN105914133B CN105914133B CN201610300050.0A CN201610300050A CN105914133B CN 105914133 B CN105914133 B CN 105914133B CN 201610300050 A CN201610300050 A CN 201610300050A CN 105914133 B CN105914133 B CN 105914133B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
The invention discloses a kind of varying doping knot terminal preparation methods to form ladder-like medium pattern, then the knot terminal of grading structure is formd by ion implanting by processing etch stop layer in dielectric layer surface.The present invention passes through the etch-rate ratio of two layers of medium of strict control, realizes being precisely controlled for step height, avoids the injected media Thickness Variation as caused by etch rate drift.Each region implantation dosage of the knot terminal realized is available to be accurately controlled, and reduces the number of device fabrication intermediate ion injection.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of varying doping knot terminal preparation method.
Background technique
SiC material forbidden bandwidth is big, breakdown electric field is high, saturation drift velocity and thermal conductivity are big, these material superior functions
Become the ideal material of production high power, high frequency, high temperature resistant, anti-radiation device.The advantage of silicon carbide is to make high pressure
Device, therefore terminal protection efficiency must be improved as far as possible in order to give full play to its material advantage.
The theoretical protection efficiency of knot terminal terminal protection form is very high, using the resistance of the silicon carbide device of junction termination technique
Power-off pressure can be close to theoretical limit.But junction termination technique efficiency is influenced very greatly by doping concentration and interface charge, especially boundary
The density of surface charge is difficult to accurately control in dielectric growth process.Current solution be formed by multiple ion implanting it is more
A knot terminal gradually decreases the dopant dose in entire terminal protection area from inside to outside and then obtains higher terminal protection effect
Rate.But such a process increases the numbers of ion implanting.
Summary of the invention
Goal of the invention：The object of the present invention is to provide the varying doping knot terminal preparations that one kind can reduce ion implanting number
Method.
Technical solution：To reach this purpose, the present invention uses following technical scheme：
Varying doping knot terminal preparation method of the present invention, includes the following steps：
S1：One dielectric layer of growth regulation on silicon carbide epitaxial layers；
S2：The dielectric layer of N layers of separate unit scalariform is sequentially formed on first medium layer, N is positive integer；
Wherein the dielectric layer of the 1st layer of separate unit scalariform is obtained by following steps：Second medium is grown on first medium layer
Layer, processes the first etch stop layer in second medium layer surface, and leads to the overetched method removal etching of part first and stop
Layer, the first etch stop layer not being removed are still covered by second dielectric layer, then lead to overetched method removal second and are situated between
The region not covered by the first etch stop layer in matter layer retains the area covered in second dielectric layer by the first etch stop layer
Domain finally removes the first etch stop layer, forms the dielectric layer of the 1st layer of separate unit scalariform, to form the 1st ion implanted region；
Wherein the dielectric layer of i-th layer of separate unit scalariform is obtained by following steps, and 1<i<N and i are integer：In the i-th dielectric layer
Upper growth regulation i+1 dielectric layer, forms the dielectric layer of i-th layer of separate unit scalariform, to form the i-th ion implanted region；
Wherein the dielectric layer of n-th layer separate unit scalariform is obtained by following steps：The growth regulation N+1 medium on N dielectric layer
Layer, processes N etch stop layer in N+1 dielectric layer surface, and leads to overetched method removal part N etching and stop
Layer, the N etch stop layer not being removed are still covered by N+1 dielectric layer, then lead to overetched method removal N+1 and are situated between
The region not covered by N etch stop layer in matter layer retains the region covered in N+1 dielectric layer by N etch stop layer,
N etch stop layer is finally removed, the dielectric layer of n-th layer separate unit scalariform is formed, to form N ion implanted region.
S3：Ion implanting is carried out to whole wafer；
S4：Remove all dielectric layers of crystal column surface.
Further, in the step S2, the rate to second dielectric layer etching is 5 to the rate of first medium layer etching
Times or more.
Further, in the step S2, the rate to the etching of N+1 dielectric layer is 5 to the rate of N dielectric layer etching
Times or more.
Further, in the step S2, in the dielectric layer of separate unit scalariform, the angular range of step is 0 °~90 °.
Further, i-th etch stop layer is made of photoresist or metallic film as material.
Further, the All Media layer is all made of silica or silicon nitride is made.
Further, the N is 3.
Beneficial effect：The present invention forms ladder-like medium pattern by multiple dielectric growth and etching, then passes through ion
Injection forms the knot terminal of grading structure.By controlling accurate control of the etch-rate of two layers of medium than realizing step height
System, avoids the injected media Thickness Variation as caused by etch rate drift.Each region implantation dosage of the knot terminal realized can
With precisely controlled, and reduce the number of device fabrication intermediate ion injection.
Detailed description of the invention
Fig. 1 is the structure obtained after one dielectric layer of growth regulation on silicon carbide epitaxial layers in a specific embodiment of the invention
Schematic diagram；
Fig. 2 is to grow the structure obtained after second dielectric layer in a specific embodiment of the invention on first medium layer
Schematic diagram；
Fig. 3 is obtained after second medium layer surface processes the first etch stop layer in a specific embodiment of the invention
Structure schematic diagram；
Fig. 4 is the signal that the structure obtained after the first etch stop layer of part is removed in a specific embodiment of the invention
Figure；
Fig. 5 is that the area not covered by the first etch stop layer in second dielectric layer is removed in a specific embodiment of the invention
The schematic diagram of the structure obtained behind domain；
Fig. 6 is the schematic diagram that the structure obtained after the first etch stop layer is removed in a specific embodiment of the invention；
Fig. 7 is the structure obtained after three dielectric layer of growth regulation in second dielectric layer in a specific embodiment of the invention
Schematic diagram；
Fig. 8 is the structure obtained after four dielectric layer of growth regulation on third dielectric layer in a specific embodiment of the invention
Schematic diagram；
Fig. 9 is obtained after the 4th dielectric layer surface processes the second etch stop layer in a specific embodiment of the invention
Structure schematic diagram；
Figure 10 is the schematic diagram that the structure obtained after the second etch stop layer is removed in a specific embodiment of the invention；
Figure 11 is to remove in the 4th dielectric layer not covered by the second etch stop layer in a specific embodiment of the invention
The schematic diagram of the structure obtained behind region；
Figure 12 is the schematic diagram that the structure obtained after the second etch stop layer is removed in a specific embodiment of the invention；
Figure 13 is that the schematic diagram for having the structure there are three ion implanted region is formed in a specific embodiment of the invention；
Figure 14 is the signal that the structure obtained after crystal column surface All Media layer is removed in a specific embodiment of the invention
Figure；
Figure 15 is that showing for the structure obtained after step angle in second dielectric layer is adjusted in a specific embodiment of the invention
It is intended to；
Figure 16 be in a specific embodiment of the invention medium etching after after the 4th dielectric layer of the bottom of the steps residual fraction
The schematic diagram of obtained structure；
Figure 17 is the removal subregional All Media layer of silicon carbide epitaxial layers surface element in a specific embodiment of the invention
The schematic diagram of ion implanting is carried out afterwards.
Specific embodiment
With reference to the accompanying drawing, technical solution of the present invention is further elaborated.
The invention discloses a kind of varying doping knot terminal preparation methods, include the following steps：
S1：One dielectric layer 2 of growth regulation on silicon carbide epitaxial layers 1, as shown in Figure 1；
S2：Second dielectric layer 3 is grown on first medium layer 2, as shown in Figure 2；Is processed on 3 surface of second dielectric layer
One etch stop layer 4, as shown in figure 3, and lead to overetched method removal the first etch stop layer of part 4, as shown in figure 4, not
The first etch stop layer 4 being removed is still covered by second dielectric layer 3, then leads to overetched method removal second dielectric layer
The region not covered by the first etch stop layer 4 in 3, as shown in figure 5, retaining in second dielectric layer 3 by the first etch stop layer 4
The region of covering finally removes the first etch stop layer 4, as shown in fig. 6, forming the second dielectric layer 3, Ye Ji of separate unit scalariform
The dielectric layer of one layer of separate unit scalariform, to form the first ion implanted region 8, as shown in figure 13；Then, in second dielectric layer 3
Three dielectric layer 5 of growth regulation, as shown in fig. 7, forming the third dielectric layer 5 of separate unit scalariform namely the medium of second layer separate unit scalariform
Layer, to form the second ion implanted region 9, as shown in figure 13；Then, four dielectric layer 6 of growth regulation on third dielectric layer 5, such as
Shown in Fig. 8, then on 6 surface of the 4th dielectric layer the second etch stop layer 7 is processed, as shown in figure 9, and leading to overetched method
Except the second etch stop layer of part 7, as shown in Figure 10, the second etch stop layer 7 not being removed is still covered by the 4th medium
Then layer 6 leads to overetched method and removes the region not covered by the second etch stop layer 7 in the 4th dielectric layer 6, such as Figure 11 institute
Show, retain the region covered in the 4th dielectric layer 6 by the second etch stop layer 7, finally remove the second etch stop layer 7, such as schemes
Shown in 12, the 4th dielectric layer 6 of separate unit scalariform namely the dielectric layer of third layer separate unit scalariform are formed, to form third ion
Injection region 10, as shown in figure 13；
S3：Ion implanting is carried out to whole wafer；
S4：Remove all dielectric layers of crystal column surface, the first ion implanted region 8, the second ion implanted region 9 and third ion
Injection region 10, which merges, forms injection region 11, as shown in figure 14.
It is 5 times or more of the rate etched to first medium layer 2 to the rate that second dielectric layer 3 etches in step S2, with
Guarantee that part of the second dielectric layer 3 above the first ion implanted region 8 completely removes, and exact residence is in first medium layer 2
On；Rate to the etching of the 4th dielectric layer 6 is 5 times or more of the rate etched to third dielectric layer 5, to guarantee the 4th dielectric layer
6 part above the second ion implanted region 9 completely removes, and exact residence is on third dielectric layer 5.
Since second dielectric layer 3, third dielectric layer 5 and the 4th dielectric layer 6 are in separate unit scalariform, namely injection exposure mask is single
It is step-like, cause the depth of the first ion implanted region 8, the second ion implanted region 9 and third ion implanted region 10 different.
This varying doping terminal protection implementation method is not limited to realize three-level step, can be by repeating two-layered medium
Growth, mask lithography, high selectivity ratio etching realize that multi-stage stairs formula knot terminal injects exposure mask, inject shape finally by single ion
At the junction termination technique of multistage dopant dose.
Furthermore, it is possible to realize structure as shown in figure 15, namely adjust separate unit scalariform by adjusting medium engraving method
The angle [alpha] of step in second dielectric layer 3 changes it in the range of 0 °~90 °, this angle can guarantee that subsequent medium is raw
Length the entire step of good covering and can make injection region intersection step thicknesses gradual so that final injection region
It is gradual that 11 intersections inject depth.
Can also realize structure as shown in figure 16 by adjusting etching condition, after medium etching the bottom of the steps can be residual
The 4th dielectric layer 6 of part is stayed, this 4th dielectric layer 6 of part makes original steep steps become to releive, and it is precipitous to avoid step
Mutation of the bring implantation dosage between injection region 11.
The removal removal subregional All Media layer of 1 surface element of silicon carbide epitaxial layers can also be etched by medium, obtained
Structure as shown in figure 17, in this way by ion implanting can be realized highest dopant dose equal to implantation dosage and dosage it is gradual
Knot terminal injecting structure.
Claims (6)
1. a kind of varying doping knot terminal preparation method, it is characterised in that：Include the following steps：
S1：One dielectric layer of growth regulation (2) on silicon carbide epitaxial layers (1)；
S2：The dielectric layer of N layers of separate unit scalariform is sequentially formed on first medium layer (2), N is positive integer；
Wherein the dielectric layer of the 1st layer of separate unit scalariform is obtained by following steps：Second dielectric layer is grown on first medium layer (2)
(3), the first etch stop layer (4) are processed on second dielectric layer (3) surface, and leads to overetched method removal part first and loses
It carves barrier layer (4), the first etch stop layer (4) not being removed is still covered by second dielectric layer (3), then leads to overetched
Method removes the region not covered by the first etch stop layer (4) in second dielectric layer (3), retains quilt in second dielectric layer (3)
The region of first etch stop layer (4) covering, finally removes the first etch stop layer (4), forms the medium of the 1st layer of separate unit scalariform
Layer, to form the 1st ion implanted region；
Wherein the dielectric layer of i-th layer of separate unit scalariform is obtained by following steps, and 1<i<N and i are integer：It is raw on the i-th dielectric layer
Long i+1 dielectric layer, forms the dielectric layer of i-th layer of separate unit scalariform, to form the i-th ion implanted region；
Wherein the dielectric layer of n-th layer separate unit scalariform is obtained by following steps：The growth regulation N+1 dielectric layer on N dielectric layer,
N+1 dielectric layer surface processes N etch stop layer, and leads to overetched method removal part N etch stop layer, not by
The N etch stop layer of removal is still covered by N+1 dielectric layer, then leads in overetched method removal N+1 dielectric layer
The region not covered by N etch stop layer retains the region covered in N+1 dielectric layer by N etch stop layer, finally goes
Except N etch stop layer, the dielectric layer of n-th layer separate unit scalariform is formed, to form N ion implanted region；
S3：Ion implanting is carried out to whole wafer；
S4：Remove all dielectric layers of crystal column surface.
2. varying doping knot terminal preparation method according to claim 1, it is characterised in that：In the step S2, to second
The rate of dielectric layer (3) etching is 5 times or more to the rate of first medium layer (2) etching.
3. varying doping knot terminal preparation method according to claim 1, it is characterised in that：In the step S2, to N+1
The rate of dielectric layer etching is 5 times or more to the rate of N dielectric layer etching.
4. varying doping knot terminal preparation method according to claim 1, it is characterised in that：In the step S2, separate unit rank
In the dielectric layer of shape, the angular range of step is 0 °~90 °.
5. varying doping knot terminal preparation method according to claim 1, it is characterised in that：The All Media layer is all made of
Silica or silicon nitride are made.
6. varying doping knot terminal preparation method according to claim 1, it is characterised in that：The N is 3.
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| CN108598150B (en) * | 2018-04-25 | 2021-06-15 | 西安理工大学 | Transverse variable doping-junction terminal extension composite terminal structure and manufacturing method thereof |
| CN108565222A (en) * | 2018-06-15 | 2018-09-21 | 江苏矽导集成科技有限公司 | A kind of variety lateral doping junction termination structures production method of SiC device |
| CN108831920A (en) * | 2018-06-15 | 2018-11-16 | 江苏矽导集成科技有限公司 | A kind of junction termination structures production method of SiC device |
| CN111192821B (en) * | 2018-12-12 | 2023-04-14 | 深圳方正微电子有限公司 | Junction terminal structure of silicon carbide power device, manufacturing method of junction terminal structure and silicon carbide power device |
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| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US6162584A (en) * | 1998-05-07 | 2000-12-19 | Taiwan Semiconductor Manufacturing Company | Method of fabricating polysilicon structures with different resistance values for gate electrodes, resistors and capacitor plates in an integrated circuit |
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