CN102623350A - Manufacturing method for semiconductor devices with super junction structures - Google Patents
Manufacturing method for semiconductor devices with super junction structures Download PDFInfo
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- CN102623350A CN102623350A CN2012101046840A CN201210104684A CN102623350A CN 102623350 A CN102623350 A CN 102623350A CN 2012101046840 A CN2012101046840 A CN 2012101046840A CN 201210104684 A CN201210104684 A CN 201210104684A CN 102623350 A CN102623350 A CN 102623350A
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Abstract
The invention discloses a manufacturing method for semiconductor devices with super junction structures. Second conductive type columns are achieved through a tilt angle implantation technology; the concentration, width and depth of the second conductive type columns can be more easily controlled by adjusting the implantation dose, the implantation energy and the implantation angle; and the width of the second conductive type columns can be greatly decreased; so that the width of whole P-N column pairs is reduced, simultaneously, the proportion of the width of first conductive type columns accounting for the width of P-N column pairs is increased, and the purpose of reducing on-resistance is reduced. First conductive type epitaxial layers are filled in deep grooves, and the first conductive type epitaxial layers and first conductive type mesa areas among the second conductive type columns form the first conductive type columns to improve the current flow path together when devices power on, accordingly, the flow path of current is increased greatly, and further the on-resistance is effectively reduced.
Description
Technical field
The present invention relates to a kind of manufacturing approach of semiconductor device, especially a kind of manufacturing approach with semiconductor device of super-junction structure.
Background technology
In mesohigh power semiconductor field, super-junction structure (Super Junction) contrasts conventional power MOSFET device by extensive employing, and super-junction structure can obtain the excellent more device withstand voltage and the tradeoff of conducting resistance.Super-junction structure is formed in the drift region of device, and this drift region comprises N conductivity type columns (N post) and P conductivity type columns (P post), and N post and P post are alternately in abutting connection with a plurality of P-N posts of forming being set to forming super-junction structure.The N post has the N conductive type impurity, and the P post has the P conductive type impurity, and the impurity level of the impurity level of N post and P post is consistent.When the MOSFET device with super-junction structure ends; N post and P post in the super-junction structure are exhausted respectively; Depletion layer extends from the P-N junction interface of each N post and P intercolumniation; Because the impurity level in the N post equates with impurity level in the P post, so depletion layer extends and exhausts N post and P post fully, thus the support device withstand voltage.
If think further to reduce the conducting resistance of device; The resistivity that reduces the semiconductor substrate drift region is one of important channel; And want to guarantee the device withstand voltage ability simultaneously and be suitable for the big process window of producing, then need dwindle the cellular size, dwindle the width that the cellular size just need be dwindled each super-junction structure in the active area; The width of each super-junction structure is again the width sum of the width and the N post of P post; In the middle of P post and N post, have only have one group of conductivity type columns of identical conduction type with device drift region could be as the path of current flowing, therefore; If can effectively dwindle the width that has that group conductivity type columns of films of opposite conductivity with the drift region, just can guarantee does not influence break-over of device resistance under to the prerequisite of width dwindling total P-N post.
Yet in actual manufacturing process, the width of P post receives the restriction of manufacturing process to a great extent.Use maximum " repeatedly extension, photoetching, injection technology " to be example with present, the P post that forms a width and be 6um, the degree of depth and be 36um only needs 6 extensions, photoetching, injections to get final product; If forming a width is 3um, the degree of depth is that the extension number of times that the P post of 36um then needs will be increased to more than 10 times, and manufacturing cost also can increase greatly.
In U.S. Pat 7601597, mention first etching deep trench; Can effectively avoid the use of repeatedly extension, photoetching, injection though use P type extension to fill the method that forms P post in the super-junction structure then; But in actual process, in the time of forming very narrow P post, because the depth-to-width ratio of required groove is very high; Therefore high to the Capability Requirement of etching and extension fill process, actual cost still can increase greatly.
Chinese patent 200680013510.6 mentioned a kind of modes of using the inclination angle to inject realize the method for super-junction structure P post; Though might produce narrow P post; But use the filling insulating material deep trench owing to inject the back; The part of fill insulant can not can not make full use of chip area as the current flowing path, therefore also is unfavorable for reducing the conducting resistance of device.
Summary of the invention
To the above-mentioned deficiency that exists in the prior art; The applicant improves through research, and a kind of manufacturing approach with semiconductor device of super-junction structure is provided, and this method technology difficulty is low; Processing step is simple, can produce the ultra junction-semiconductor device with minimum cellular width.
Technical scheme of the present invention is following:
A kind of manufacturing approach with semiconductor device of super-junction structure comprises the steps:
(a) semiconductor substrate with first conduction type is provided; Said semiconductor substrate has corresponding first interarea and second interarea; Comprise the first conduction type drift region and the first conductivity type substrate layer between first interarea of semiconductor substrate and second interarea, the impurity concentration of the said first conduction type drift region is less than the impurity concentration of the first conductivity type substrate layer;
(b) deposit hard mask layer on first interarea of said semiconductor substrate; Optionally shelter and the etching hard mask layer, form the hard mask open of a plurality of etching grooves;
(c) through said hard mask open; Utilize the anisotropic etching method in the first conduction type drift region, to etch a plurality of deep trench; Said deep trench is extended by first interarea vertically downward; The degree of depth is no more than the degree of depth of the first conduction type drift region, and said each deep trench all has the first side wall and second sidewall, and the spacing between the said the first side wall and second sidewall is M; And each deep trench all has the bottom, and said deep trench is divided into a plurality of first conduction type table sections with the first conduction type drift region;
(d) mode of injecting through the inclination angle ion is injected second conductive type impurity to the first side wall and second sidewall of said deep trench respectively; Thereby form second conductivity type columns in the first conduction type table section between adjacent deep trenches; The degree of depth of said second conductivity type columns is no more than the degree of depth of deep trench; Comprise two second conductivity type columns in the same first conduction type table section, the spacing of said two second conductivity type columns is N, and N=M;
(e) hard mask layer on removal first interarea;
(f) utilize epitaxial growth technology; Growth first conductive type epitaxial layer in said deep trench and above first interarea; The first conductive type impurity concentration of said first conductive type epitaxial layer equates with the first conductive type impurity concentration of the first conduction type table section, the common formation of first conductive type epitaxial layer in the said deep trench and the first conduction type table section between the adjacent deep trenches first conductivity type columns;
(g) first conductive type epitaxial layer on first interarea is removed in planarization and polishing first interarea, has the super-junction structure that is constituted in abutting connection with first conductivity type columns of arranging and second conductivity type columns by alternately thereby in semiconductor substrate, form;
(h) on above-mentioned first interarea with super-junction structure semiconductor substrate; Through conventional semiconductor technology; Obtain semiconductor device corresponding elements zone and neighboring area, the element area of said semiconductor device is plane MOS structure or groove type MOS structure;
For the manufacturing approach of N type semiconductor device, said first conduction type is the N type, and said second conduction type is the P type; For the manufacturing approach of P type semiconductor device, said first conduction type is the P type, and said second conduction type is the N type.
Its further technical scheme is:
In the said step (d), be infused in injection second conductive type impurity in the first conduction type table section between the said deep trench through the inclination angle ion, second conductive type impurity is not injected in said deep trench bottom.
In the said step (f), the impurity concentration of first conductive type epitaxial layer of institute's intussusception growth equates with the impurity concentration of the first conduction type drift region in the deep trench.
In the said step (d), second conductivity type columns in the first conduction type table section has the identical degree of depth, width and impurity concentration.
In the said step (d), need successively to accomplish the inclination angle ion implantation technology to the first side wall and second sidewall of deep trench respectively.
In the said step (d), the second conductive type impurity kind of injecting through the inclination angle ion comprises boron or boron difluoride.
In the said step (d), the injection incident angle that said inclination angle ion injects is between 0 degree and 45 degree.
Said hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
The material of said semiconductor substrate comprises silicon.
Useful technique effect of the present invention is:
One, in the manufacturing approach of super-junction structure of the present invention; Second conductivity type columns is to realize through the technology that the inclination angle ion injects, and therefore, can control concentration, width and the degree of depth of second conductivity type columns more easily through adjustment implantation dosage, injection energy and implant angle; Can reduce the width of second conductivity type columns greatly; Thereby dwindle whole P-N post to width in, increase by the first conductivity type columns width and account for the ratio of P-N post width, reach the purpose that reduces conducting resistance.
Two, in the manufacturing approach of super-junction structure of the present invention; Be filled with first conductive type epitaxial layer in the deep trench; Common formation first conductivity type columns of the first conduction type drift region between said first conductive type epitaxial layer and said second conductivity type columns; The path of current flowing is provided when break-over of device jointly, has increased the current flowing path greatly, thereby effectively reduced conducting resistance.
Three, the manufacturing approach of super-junction structure of the present invention, its manufacturing process is simple, and is with low cost, is suitable for producing in batches.
Description of drawings
Fig. 1～Fig. 8 is the cutaway view in semiconductor device practical implementation each stage of technology of the present invention, and wherein: Fig. 1 is the cutaway view of semiconductive material substrate of the present invention.
Fig. 2 is the cutaway view after the hard mask open that forms etching groove on semiconductor substrate first interarea.
Fig. 3 is the cutaway view after the formation deep trench.
Fig. 4 carries out the inclination angle ion to the deep trench the first side wall to inject the cutaway view after forming the P post.
Fig. 5 carries out the inclination angle ion to deep trench second sidewall to inject the cutaway view after forming the P post.
Fig. 6 reaches the cutaway view behind the growth N type epitaxial loayer on the first interarea surface in deep trench.
Fig. 7 is the cutaway view behind the lip-deep N type of removal first interarea epitaxial loayer.
Fig. 8 is the cutaway view of the device element area after the complete plane MOS structure of formation.
Embodiment
Further specify below in conjunction with the accompanying drawing specific embodiments of the invention.
Following examples are example with N type super node MOSFET device, and said method, semi-conductor device manufacturing method with super-junction structure comprises the steps:
A, the semiconductor substrate with N type conduction type (material comprises silicon) is provided; Said semiconductor substrate has corresponding first interarea (semiconductor substrate upper surface) and second interarea (semiconductor substrate lower surface); Comprise N type drift region and N+ substrate layer between first interarea of semiconductor substrate and second interarea, the impurity concentration of N+ substrate layer is greater than the impurity concentration of N type drift region; As shown in Figure 1.
B, on first interarea of said semiconductor substrate deposit hard mask layer (LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride); Optionally shelter then and the said hard mask layer of etching, form the hard mask open of etching groove; As shown in Figure 2.
C, through said hard mask open, utilize anisotropic dry etch process to etch a plurality of deep trench, said deep trench is extended in N type drift region by first interarea vertically downward; The degree of depth is T1; And T1 is less than the thickness of N type drift region, and said each deep trench all has the first side wall S1 and the second sidewall S2, and the width of said deep trench is M; And each deep trench all has the bottom, and said deep trench is divided into a plurality of N type table sections with N type drift region; As shown in Figure 3.
D, inject p type impurity (kind is boron or boron difluoride BF2) to the first side wall S1 of said deep trench and the second sidewall S2 respectively through the inclination angle ion implantation technology; Form the P post in the N type table section of said p type impurity between adjacent deep trenches; The degree of depth of said P post is T2, and wherein T2 is slightly less than T1, and does not inject p type impurity in the bottom of said deep trench; In same N type table section, comprise two P posts; Said two P posts are close to the first side wall S1 and the second sidewall S2 of the deep trench of N type table section both sides respectively, and two P intercolumniations in the same N type table section are N, wherein M=N; Like Fig. 4 and shown in Figure 5.
Hard mask layer on e, removal first interarea.
F, utilize the epitaxial growth technology N type epitaxial loayer of growing in said deep trench and above first interarea; The impurity concentration of said N type epitaxial loayer is identical with the impurity concentration of N type table section, N type drift region, and N type epitaxial loayer and N type table section in the said deep trench constitute the N post jointly; As shown in Figure 6.
The N type epitaxial loayer on first interarea is removed in g, planarization and cut open light first interarea, has the super-junction structure that is constituted in abutting connection with the N post of arranging and P post by alternately thereby in semiconductor substrate, form; As shown in Figure 7.
H, on above-mentioned first interarea with super-junction structure semiconductor substrate, obtain semiconductor device corresponding elements zone and neighboring area through conventional semiconductor technology, the element area of said semiconductor device can be plane MOS structure or groove type MOS structure.
The manufacturing approach of said plane MOS structure can be with reference to disclosed manufacturing approach among the ZL01807673.4; The manufacturing approach of said groove type MOS structure can be with reference to disclosed manufacturing approach among the ZL200510110709.8.What element area adopted in the present embodiment is plane MOS structure; As shown in Figure 8.
The first side wall S1 of deep trench and the second sidewall S2 are being carried out the inclination angle ion respectively when injecting; The incident angle that injects is θ (between 0 degree and 45 degree); The path and the angle between its normal that promptly inject are θ; The setting of θ is to decide according to the width M of deep trench and the degree of depth T1 of deep trench, specifically, follows the trigonometric function relation of right-angled triangle between θ, M, the T1 three.When injecting, at first the first side wall S1 is injected, make p type impurity inject uniformly in the N type table section in the first side wall S1 outside; Thereby in the N type table section in the first side wall S1 outside, form the P post; Then, with angle same the second sidewall S2 is injected again, make p type impurity inject in the N type table section in the second sidewall S2 outside uniformly; Thereby in the N type table section in the second sidewall S2 outside, form the P post; P type impurity in above-mentioned two groups of P posts is below first interarea and between the deep trench sidewall bottom, and evenly continuous distribution in the N type table section of next-door neighbour's deep trench sidewall, and has the identical degree of depth, width and impurity concentration; Like Fig. 4 and shown in Figure 5.
Because the angle θ that the inclination angle ion injects can come to set flexibly according to the degree of depth and the width of deep trench; Simultaneously, through setting the width that energy that ion injects can change the P post, through setting the impurity concentration that dosage that ion injects can change the P post; Therefore; The degree of depth of P post, width and concentration can come to set flexibly according to the performance parameters demand of actual product, and because the P post injects through ion forms, so can be with the width of P post dwindling by a relatively large margin; Thereby obtain the littler right width of P-N post, greatly reduce the conducting resistance of device.
Has filled N type epitaxial loayer through epitaxial growth technology in the deep trench, the concentration of said N type epitaxial loayer is identical with N type table section concentration between the deep trench, and both have formed the N post that constitutes super-junction structure jointly; When break-over of device was worked, the N post was that electric current provides circulation path, and circulation path is wide more; The conducting resistance of device is low more, and therefore, the semiconductor device with super-junction structure through manufacturing approach manufacturing provided by the invention has lower conducting resistance; And manufacturing process is simple; With low cost, be suitable for producing in batches, improved cost performance of product greatly.
The foregoing description is to describe with the manufacturing approach of N type semiconductor device.The present invention also can be used for the manufacturing approach of P type semiconductor device, only need in the said method conduction type by the P type change the N type into, the N type changes the P type into and gets final product.
Above-described only is preferred implementation of the present invention, the invention is not restricted to above embodiment.Be appreciated that other improvement and variation that those skilled in the art directly derive or associate under the prerequisite that does not break away from basic design of the present invention, all should think to be included within protection scope of the present invention.
Claims (9)
1. the manufacturing approach with semiconductor device of super-junction structure is characterized in that comprising the steps:
(a) semiconductor substrate with first conduction type is provided; Said semiconductor substrate has corresponding first interarea and second interarea; Comprise the first conduction type drift region and the first conductivity type substrate layer between first interarea of semiconductor substrate and second interarea, the impurity concentration of the said first conduction type drift region is less than the impurity concentration of the first conductivity type substrate layer;
(b) deposit hard mask layer on first interarea of said semiconductor substrate; Optionally shelter and the etching hard mask layer, form the hard mask open of a plurality of etching grooves;
(c) through said hard mask open; Utilize the anisotropic etching method in the first conduction type drift region, to etch a plurality of deep trench; Said deep trench is extended by first interarea vertically downward; The degree of depth is no more than the degree of depth of the first conduction type drift region, and said each deep trench all has the first side wall and second sidewall, and the spacing between the said the first side wall and second sidewall is M; And each deep trench all has the bottom, and said deep trench is divided into a plurality of first conduction type table sections with the first conduction type drift region;
(d) mode of injecting through the inclination angle ion is injected second conductive type impurity to the first side wall and second sidewall of said deep trench respectively; Thereby form second conductivity type columns in the first conduction type table section between adjacent deep trenches; The degree of depth of said second conductivity type columns is no more than the degree of depth of deep trench; Comprise two second conductivity type columns in the same first conduction type table section, the spacing of said two second conductivity type columns is N, and N=M;
(e) hard mask layer on removal first interarea;
(f) utilize epitaxial growth technology; Growth first conductive type epitaxial layer in said deep trench and above first interarea; The first conductive type impurity concentration of said first conductive type epitaxial layer equates with the first conductive type impurity concentration of the first conduction type table section, the common formation of first conductive type epitaxial layer in the said deep trench and the first conduction type table section between the adjacent deep trenches first conductivity type columns;
(g) first conductive type epitaxial layer on first interarea is removed in planarization and polishing first interarea, has the super-junction structure that is constituted in abutting connection with first conductivity type columns of arranging and second conductivity type columns by alternately thereby in semiconductor substrate, form;
(h) on above-mentioned first interarea with super-junction structure semiconductor substrate; Through conventional semiconductor technology; Obtain semiconductor device corresponding elements zone and neighboring area, the element area of said semiconductor device is plane MOS structure or groove type MOS structure;
For the manufacturing approach of N type semiconductor device, said first conduction type is the N type, and said second conduction type is the P type; For the manufacturing approach of P type semiconductor device, said first conduction type is the P type, and said second conduction type is the N type.
2. according to the said manufacturing approach of claim 1 with semiconductor device of super-junction structure; It is characterized in that: in the said step (d); Be infused in injection second conductive type impurity in the first conduction type table section between the said deep trench through the inclination angle ion, second conductive type impurity is not injected in said deep trench bottom.
3. according to the said manufacturing approach of claim 1 with semiconductor device of super-junction structure; It is characterized in that: in the said step (f), the impurity concentration of first conductive type epitaxial layer of institute's intussusception growth equates with the impurity concentration of the first conduction type drift region in the deep trench.
4. according to the said manufacturing approach with semiconductor device of super-junction structure of claim 1, it is characterized in that: in the said step (d), second conductivity type columns in the first conduction type table section has the identical degree of depth, width and impurity concentration.
5. according to the said manufacturing approach of claim 1, it is characterized in that: in the said step (d), need successively to accomplish the inclination angle ion implantation technology to the first side wall and second sidewall of deep trench respectively with semiconductor device of super-junction structure.
6. according to the said manufacturing approach with semiconductor device of super-junction structure of claim 1, it is characterized in that: in the said step (d), the second conductive type impurity kind of injecting through the inclination angle ion comprises boron or boron difluoride.
7. according to the said manufacturing approach with semiconductor device of super-junction structure of claim 1, it is characterized in that: in the said step (d), the injection incident angle that said inclination angle ion injects is between 0 degree and 45 degree.
8. according to the said manufacturing approach with semiconductor device of super-junction structure of claim 1, it is characterized in that: said hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
9. according to the said manufacturing approach with semiconductor device of super-junction structure of claim 1, it is characterized in that: the material of said semiconductor substrate comprises silicon.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103730355A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Method for manufacturing super junction structure |
| CN104409334A (en) * | 2014-11-06 | 2015-03-11 | 中航（重庆）微电子有限公司 | Method for preparing super junction device |
| CN105006484A (en) * | 2015-06-12 | 2015-10-28 | 无锡新洁能股份有限公司 | Super-junction semiconductor device and manufacture method thereof |
| CN106328532A (en) * | 2015-07-02 | 2017-01-11 | 北大方正集团有限公司 | Manufacturing method and structure of epitaxial wafer for super-junction device |
| CN106340458A (en) * | 2016-10-11 | 2017-01-18 | 无锡同方微电子有限公司 | Manufacturing method for reducing manufacturing cost of deep-groove type super junction MOSFET |
| CN109564932A (en) * | 2016-08-08 | 2019-04-02 | 三菱电机株式会社 | Semiconductor device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103730355A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Method for manufacturing super junction structure |
| CN103730355B (en) * | 2013-12-27 | 2016-05-11 | 西安龙腾新能源科技发展有限公司 | A kind of manufacture method of super-junction structure |
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| CN106328532A (en) * | 2015-07-02 | 2017-01-11 | 北大方正集团有限公司 | Manufacturing method and structure of epitaxial wafer for super-junction device |
| CN106328532B (en) * | 2015-07-02 | 2020-06-09 | 北大方正集团有限公司 | Manufacturing method and structure of super junction device epitaxial wafer |
| CN109564932A (en) * | 2016-08-08 | 2019-04-02 | 三菱电机株式会社 | Semiconductor device |
| CN106340458A (en) * | 2016-10-11 | 2017-01-18 | 无锡同方微电子有限公司 | Manufacturing method for reducing manufacturing cost of deep-groove type super junction MOSFET |
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