WO2017118028A1 - Dispositif de protection contre les surtensions - Google Patents

Dispositif de protection contre les surtensions Download PDF

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Publication number
WO2017118028A1
WO2017118028A1 PCT/CN2016/095630 CN2016095630W WO2017118028A1 WO 2017118028 A1 WO2017118028 A1 WO 2017118028A1 CN 2016095630 W CN2016095630 W CN 2016095630W WO 2017118028 A1 WO2017118028 A1 WO 2017118028A1
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WO
WIPO (PCT)
Prior art keywords
well layer
surge
protection device
well
deep
Prior art date
Application number
PCT/CN2016/095630
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English (en)
Chinese (zh)
Inventor
骆生辉
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深圳市槟城电子有限公司
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Filing date
Publication date
Application filed by 深圳市槟城电子有限公司 filed Critical 深圳市槟城电子有限公司
Publication of WO2017118028A1 publication Critical patent/WO2017118028A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Definitions

  • the present invention relates to the field of overvoltage protection products, and more particularly to a surge protection device.
  • TSS transient suppression diode
  • TVS is a voltage clamp type protection device.
  • THYRISTOR SURGE SUPPRESSOR (TSS) is a voltage switching protection device.
  • the unidirectional TVS needs to be used in series with the TSS.
  • the unidirectional TVS clamps the surge voltage to the Protects the electronics from operating within the normal operating voltage range; when subjected to a reverse surge, the TSS releases the surge voltage close to a short circuit, preventing the protected electronic device from being damaged by excessive reverse voltage.
  • the object of the present invention is to provide a surge protection device capable of providing forward surge protection and reverse surge protection for a circuit, and having higher integration, simple structure and low cost.
  • an embodiment of the present invention provides a surge protection device, including:
  • the N-type substrate is provided with a back surface P well layer on the entire back surface, a front surface P well layer on the front surface of the N type substrate, and an N+ implantation region on one side of the front surface P well layer.
  • the front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on a side where the N+ implant region is provided.
  • a front deep N-well is disposed under the front shallow P-well layer.
  • the back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed on a side where the N+ implant region is provided.
  • a back deep N-well is provided on the back shallow P well layer.
  • the back deep P well layer is provided with a plurality of separate deep P wells.
  • the N+ injection zone is provided in plurality.
  • a short circuit hole is disposed between the plurality of N+ implant regions, and the short circuit hole has a large impedance.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 1 is a schematic cross-sectional view of a surge protection device according to Embodiment 1 of the present invention.
  • FIG. 2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a surge protection device according to Embodiment 2 of the present invention.
  • FIG. 4 is a cross-sectional view showing a surge protection device according to Embodiment 3 of the present invention.
  • FIG. 5 is a cross-sectional view showing a surge protection device according to Embodiment 4 of the present invention.
  • FIG. 6 is a cross-sectional view of a surge protection device according to a fifth embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a surge protection device according to Embodiment 1 of the present invention.
  • the surge protection device 1 of the present embodiment includes: a metal layer 11 of an external conductor, an N-type substrate, and a back surface P well layer on the entire back surface of the N-type substrate, the N-type substrate
  • the front side is provided with a front P-well layer, and one side of the front P-well layer is provided with an N+ implanted region.
  • the N+ implant region is provided with a plurality of electrodes for adjusting the sustain current and the sustain voltage of the device.
  • a short circuit hole 12 is provided between the plurality of N+ implant regions, and the short circuit hole 12 has a large impedance. The shorting holes are used to improve the anti-interference ability of the device. Since the device area is too large, if there is no short-circuit hole, the device will concentrate current in one part, while the other part has no current, which will adversely affect the performance of the device.
  • FIG. 2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention. The working process of the surge protection device provided by the present invention will be described below with reference to FIG. 1 and FIG.
  • the reverse PN junction formed by the N-type substrate-back P well undergoes avalanche breakdown, thereby discharging the surge current.
  • the structure on the right side of the device is N+ implant-front P-type-substrate-back P-well, which will not turn on due to high withstand voltage. So when a positive surge comes, the surge is vented through the front P-well-N-substrate-back P-well region on the left side of the device. At this point, the device exhibits TVS performance. When the surge is over, the device shuts down immediately and there is no problem with freewheeling.
  • the reverse diode formed by the N+ implant-front P well has a high withstand voltage
  • the reverse diode formed by the N-type substrate-front P well has a low withstand voltage
  • the N-type liner Avalanche breakdown occurs in the bottom-front P-well, and a leakage current forms a voltage drop through the short-circuit hole after breakdown.
  • the voltage drop is greater than the forward voltage drop of the front P-well-N+ implant, the PNPN structure formed by the backside P-well-N-substrate-front P-well-N+ implant produces positive feedback.
  • the surge passes, the device is turned off immediately due to the low potential of the back P-well, and there is no problem of freewheeling.
  • the working circuit of the device is equivalent to the circuit in which TVS and TSS are connected in parallel in FIG.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 3 is a cross-sectional view of a surge protection device according to Embodiment 2 of the present invention.
  • the surge protection device of this embodiment includes: an N-type substrate having a back surface P well layer on the entire back surface, and a front surface P well layer on the front surface of the N type substrate
  • the front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on the side where the N+ implant region is provided.
  • the first embodiment corresponding to FIG. 1 has the following differences: the front P-well layer is a front deep P well layer and a front shallow P well layer on both sides, and the front shallow P well layer is disposed on the N+ implant. The side of the district. The remaining components are the same as those in the first embodiment, and are not described herein again.
  • the advantages are:
  • the reverse PN junction formed by the N-type substrate-back P well undergoes avalanche breakdown, thereby discharging the surge current.
  • the front deep P-well-N-substrate-backside P-well structure has a small negative-resistance characteristic, which can effectively reduce the residual voltage and improve the surge discharge capability.
  • the structure on the right side of the device is N+ implant-front shallow P-well-N-substrate-back P-well, which will not turn on due to high withstand voltage. So when a positive surge comes, the surge is vented through the front deep P-well-N-substrate-back P-well region on the left side of the device. At this point, the device exhibits TVS performance. When the surge is over, the device shuts down immediately and there is no problem with freewheeling.
  • the reverse diode formed by the N+ implant-front deep P-well has a high withstand voltage
  • the reverse diode formed by the N-type substrate-front shallow P-well has a low withstand voltage
  • N The substrate-formal shallow P-well undergoes avalanche breakdown, and a leakage current forms a voltage drop through the short-circuit hole after breakdown.
  • the PNPN structure formed by the backside P-N-substrate-front shallow P-N+ implant produces positive feedback.
  • the surge passes, the device is turned off immediately due to the low potential of the back P-well, and there is no problem of freewheeling.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 4 is a cross-sectional view of a surge protection device according to Embodiment 3 of the present invention.
  • the surge protection device of this embodiment includes: an N-type substrate having a back surface P well layer on the entire back surface, and a front surface P well layer on the front surface of the N type substrate An N+ implant region is disposed on a right side of the front P well layer, and the back P well layer is a back deep P well layer and a back shallow P well layer respectively disposed on both sides, and the back deep P well layer is disposed There is the side of the N+ injection zone.
  • the embodiment 1 corresponding to FIG. 1 has the following difference: the back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed in the The side of the N+ injection zone.
  • the remaining components are the same as those in the first embodiment, and are not described herein again.
  • the advantage is that when the device is affected In the case of a reverse surge, the deep P-well layer on the back side can increase the surge bleed capacity of the device and reduce residual voltage.
  • the back deep P well layer is provided with a plurality of separate deep P wells.
  • the advantage is that the junction area of the back deep P-well-N substrate is increased, and the reverse surge bleed capability of the device is further improved.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.
  • FIG. 6 is a cross-sectional view of a surge protection device according to Embodiment 5 of the present invention.
  • the surge protection device of this embodiment includes: an N-type substrate, and the back surface of the N-type substrate is provided with a back deep P well layer and a back shallow P well layer respectively on both sides, a back deep P well layer is disposed on a side where the N+ implant region is disposed, and the front surface of the N type substrate is provided with a front deep P well layer and a front shallow P well layer respectively on both sides, and the front shallow P well layer An N+ implant region is disposed thereon, and a front deep N well is disposed under the front shallow P well layer, and a back deep N well is disposed on the back shallow P well layer.
  • the third embodiment corresponding to FIG. 4 has the following difference: a front deep N well is disposed under the front shallow P well layer, and a back deep N well is disposed on the back shallow P well layer.
  • the remaining components are the same as those in the third embodiment, and are not described here.
  • the advantage is that the breakdown voltage when the device is subjected to the reverse surge can be adjusted by adjusting the front deep N-well; the breakdown voltage when the device is subjected to the forward surge can be adjusted by adjusting the back deep N-well, At the same time, the forward surge capability of the device is further improved, and the residual voltage is reduced.
  • the surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application.
  • the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

L'invention concerne un dispositif de protection contre les surtensions qui comprend : un substrat de type N ayant une couche de puits P arrière sur toute sa surface arrière et une couche de puits P avant sur une surface avant du substrat de type N, un côté de la couche de puits P avant étant pourvu de régions à implantation N+. Un TVS et un TSS sont intégrés, de sorte que le dispositif affiche des caractéristiques TVS lorsqu'il est soumis à une surtension directe, et qu'il affiche des caractéristiques TSS lorsqu'il est soumis à une surtension inverse, permettant ainsi de résoudre le problème dans des applications dans lesquelles un TVS et un TSS connectés en série doivent être utilisés. Le dispositif de protection contre les surtensions présente un niveau d'intégration élevé et un faible coût de production, facilite la connexion à un circuit externe, et peut être appliqué de façon aisée et commode.
PCT/CN2016/095630 2016-01-05 2016-08-17 Dispositif de protection contre les surtensions WO2017118028A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610009821.0A CN105552873B (zh) 2016-01-05 2016-01-05 一种浪涌防护器件
CN201610009821.0 2016-01-05

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WO2017118028A1 true WO2017118028A1 (fr) 2017-07-13

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Cited By (3)

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CN108922885A (zh) * 2018-08-06 2018-11-30 上海长园维安微电子有限公司 一种大功率单向tvs器件
CN110459593A (zh) * 2019-08-01 2019-11-15 富芯微电子有限公司 一种低钳位电压单向tvs器件及其制造方法
CN112614782A (zh) * 2020-12-15 2021-04-06 扬州杰利半导体有限公司 一种单向负阻浪涌防护芯片的制造方法

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CN105552873B (zh) * 2016-01-05 2024-03-29 深圳市槟城电子股份有限公司 一种浪涌防护器件
CN106783949A (zh) * 2016-12-19 2017-05-31 东莞市阿甘半导体有限公司 单向tvs结构及其制造方法
CN108428697A (zh) * 2017-11-09 2018-08-21 上海长园维安微电子有限公司 一种低电容双向带负阻tvs器件
CN111223914A (zh) * 2019-07-01 2020-06-02 上海维安半导体有限公司 一种具有负阻特性的半导体放电管及其制造方法
CN117116936B (zh) * 2023-09-25 2024-04-26 深圳长晶微电子有限公司 单向浪涌防护装置及其制作方法

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US5401984A (en) * 1991-06-11 1995-03-28 Texas Instruments Incorporated Semiconductor component for transient voltage limiting
CN2181754Y (zh) * 1994-01-19 1994-11-02 东南大学 平面型硅抗电涌器件
WO2004004007A2 (fr) * 2002-06-29 2004-01-08 Bourns Ltd Protection contre la surtension
CN101552465A (zh) * 2008-04-04 2009-10-07 半导体元件工业有限责任公司 瞬变电压抑制器和方法
CN102496619A (zh) * 2011-12-26 2012-06-13 天津环联电子科技有限公司 一种发光二极管的保护器件芯片及生产工艺
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CN105552873A (zh) * 2016-01-05 2016-05-04 深圳市槟城电子有限公司 一种浪涌防护器件
CN205283121U (zh) * 2016-01-05 2016-06-01 深圳市槟城电子有限公司 一种浪涌防护器件
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CN205385026U (zh) * 2016-01-15 2016-07-13 上海瞬雷电子科技有限公司 双向放电管芯片

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Publication number Priority date Publication date Assignee Title
CN108922885A (zh) * 2018-08-06 2018-11-30 上海长园维安微电子有限公司 一种大功率单向tvs器件
CN110459593A (zh) * 2019-08-01 2019-11-15 富芯微电子有限公司 一种低钳位电压单向tvs器件及其制造方法
CN110459593B (zh) * 2019-08-01 2024-05-28 富芯微电子有限公司 一种低钳位电压单向tvs器件及其制造方法
CN112614782A (zh) * 2020-12-15 2021-04-06 扬州杰利半导体有限公司 一种单向负阻浪涌防护芯片的制造方法

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