TWI615987B - Solar cell and method for manufacturing the same - Google Patents
Solar cell and method for manufacturing the same Download PDFInfo
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- TWI615987B TWI615987B TW104142229A TW104142229A TWI615987B TW I615987 B TWI615987 B TW I615987B TW 104142229 A TW104142229 A TW 104142229A TW 104142229 A TW104142229 A TW 104142229A TW I615987 B TWI615987 B TW I615987B
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- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 46
- 239000000956 alloy Substances 0.000 claims abstract description 46
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 198
- 230000008569 process Effects 0.000 claims description 21
- 239000011241 protective layer Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 239000011135 tin Substances 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 5
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
一種太陽能電池包含一基板、一第一摻雜層、一第二摻雜層、一鈍化層、一種子層及一合金層。該基板具有相對應的一第一表面與一第二表面。該第一摻雜層設置於該第一表面上，並包含一低摻雜區及一高摻雜區。該第二摻雜層設置於該第二表面上，並與該第一摻雜層的摻雜類型不同。該鈍化層設置於該第一摻雜層上，並具有一鈍化層開口，以裸露出該高摻雜區。該種子層設置於裸露的該高摻雜區上。該合金層設置於裸露的該高摻雜區與該種子層之間，其中該高摻雜區之寬度大於該合金層之寬度，且該高摻雜區的深度大於該低摻雜區的深度。 A solar cell comprises a substrate, a first doped layer, a second doped layer, a passivation layer, a sublayer and an alloy layer. The substrate has a corresponding first surface and a second surface. The first doped layer is disposed on the first surface and includes a low doped region and a highly doped region. The second doped layer is disposed on the second surface and is different from the doping type of the first doped layer. The passivation layer is disposed on the first doped layer and has a passivation layer opening to expose the highly doped region. The seed layer is disposed on the exposed highly doped region. The alloy layer is disposed between the exposed high doped region and the seed layer, wherein a width of the highly doped region is greater than a width of the alloy layer, and a depth of the highly doped region is greater than a depth of the low doped region .
Description
本發明是有關於一種太陽能電池及其製造方法，且特別是有關於一種電鍍太陽能電池及其製造方法，其合金層設置於高摻雜區上。 The present invention relates to a solar cell and a method of fabricating the same, and more particularly to an electroplated solar cell and a method of fabricating the same, wherein an alloy layer is disposed on a highly doped region.
已知的矽晶太陽能電池結構，主要包含：一基板、一與該基板形成p-n接面的射極層、一位於該射極層上的抗反射層，以及用於傳導電流的一正面電極與一背面電極。該正面電極包括至少一匯流電極(busbar electrode)，及數個橫向連接該匯流電極的指狀電極(finger electrode)。在製作上，可利用電鍍方式形成前述電極。進行電鍍前，必須先於該抗反射層的適當部位開孔，使該射極層的部分表面露出，該抗反射層的開孔形狀通常相當於電極形成後的形狀。後續再以電鍍方式製成電極。 The known twin solar cell structure mainly comprises: a substrate, an emitter layer forming a pn junction with the substrate, an anti-reflection layer on the emitter layer, and a front electrode for conducting current A back electrode. The front electrode includes at least one busbar electrode, and a plurality of finger electrodes laterally connected to the bus electrode. In the fabrication, the electrodes can be formed by electroplating. Before plating, it is necessary to open a hole in an appropriate portion of the anti-reflection layer to expose a part of the surface of the emitter layer. The shape of the opening of the anti-reflection layer generally corresponds to the shape after the electrode is formed. The electrodes are then electroplated.
以電鍍方式所製作之太陽能電池的電極通常以金屬合金層作為最底層之歐姆接觸層，接著再以電鍍方式形成所需之電極。所述金屬合金層是將金屬透過高溫退火的方式與其下之矽形成金屬合金層，主要有兩個好處，其一是可使歐姆接觸特性獲得提升，其二是可作為銅的擴散阻擋層，避免銅擴散至矽基板而形成載子複合中心。 The electrode of the solar cell fabricated by electroplating usually has a metal alloy layer as the bottommost ohmic contact layer, and then electroplated to form a desired electrode. The metal alloy layer is a metal alloy layer formed by passing the metal through high-temperature annealing and the underlying layer thereof. There are two main advantages, one of which is to improve the ohmic contact characteristics, and the other is to act as a diffusion barrier for copper. Avoid copper diffusion to the germanium substrate to form a carrier recombination center.
然而，金屬合金層有時會產生射極層分流(emitter shunting)的情況，進而導致太陽能電池的效率驟降，這是由於金屬合金層穿透射極層剖面(emitter profile)所造成。 However, the metal alloy layer sometimes produces an emitter shunting, which in turn leads to a sharp drop in the efficiency of the solar cell due to the metal alloy layer passing through the emitter profile.
因此，便有需要提供一種太陽能電池及其製造方法，能夠解決前述的問題。 Therefore, there is a need to provide a solar cell and a method of manufacturing the same that can solve the aforementioned problems.
本發明之一目的是提供一種太陽能電池，其合金層設置於裸露的高摻雜區上。 It is an object of the present invention to provide a solar cell having an alloy layer disposed on a bare highly doped region.
依據上述之目的，本發明提供一種太陽能電池包含一基板、一第一摻雜層、一第二摻雜層、一鈍化層、一種子層及一合金層。該基板具有相對應的一第一表面與一第二表面。該第一摻雜層設置於該第一表面上，包含一低摻雜區及一高摻雜區。該第二摻雜層設置於該第二表面上，與該第一摻雜層的摻雜類型不同。該鈍化層設置於該第一摻雜層上，並具有一鈍化層開口，以裸露出該高摻雜區的至少一部分區域。該種子層設置於裸露的該高摻雜區上。該合金層設置於裸露的該高摻雜區與該種子層之間，其中該高摻雜區之寬度大於該合金層之寬度，且該高摻雜區的深度大於該低摻雜區的深度。 According to the above objective, the invention provides a solar cell comprising a substrate, a first doped layer, a second doped layer, a passivation layer, a sublayer and an alloy layer. The substrate has a corresponding first surface and a second surface. The first doped layer is disposed on the first surface and includes a low doped region and a highly doped region. The second doped layer is disposed on the second surface, different from the doping type of the first doped layer. The passivation layer is disposed on the first doped layer and has a passivation layer opening to expose at least a portion of the highly doped region. The seed layer is disposed on the exposed highly doped region. The alloy layer is disposed between the exposed high doped region and the seed layer, wherein a width of the highly doped region is greater than a width of the alloy layer, and a depth of the highly doped region is greater than a depth of the low doped region .
因實作上，該合金層(例如矽化鎳)的形成不易控制，導致合金層之寬度或深度易超出射極層剖面而造成分流現象。本實施例之特點為：該合金層設置於裸露的該高摻雜區上，該高摻雜區之寬度大於該合金層之寬度，且該高摻雜區的深度大於該低摻雜區的深度。主要目的為該高摻雜區之寬度大於該合金層之寬度時，可確保該合金層形成的時候在歐姆接觸區域的邊緣不會發生射極層分流的現象。該高摻雜區之深度大於該低摻雜區之深度時，則可避免該合金層形成的時候在射極層剖面的邊緣發生射極層分流的現象。 In practice, the formation of the alloy layer (for example, nickel telluride) is difficult to control, resulting in the width or depth of the alloy layer easily exceeding the cross section of the emitter layer to cause a shunt phenomenon. The embodiment is characterized in that the alloy layer is disposed on the exposed high doped region, the width of the highly doped region is greater than the width of the alloy layer, and the depth of the highly doped region is greater than the low doped region. depth. The main purpose is that when the width of the highly doped region is larger than the width of the alloy layer, it is ensured that the electrode layer is not shunted at the edge of the ohmic contact region when the alloy layer is formed. When the depth of the highly doped region is greater than the depth of the low doped region, the phenomenon that the emitter layer is shunted at the edge of the cross section of the emitter layer when the alloy layer is formed can be avoided.
1‧‧‧太陽能電池 1‧‧‧Solar battery
10‧‧‧基板 10‧‧‧Substrate
101‧‧‧第一表面 101‧‧‧ first surface
102‧‧‧第二表面 102‧‧‧ second surface
11‧‧‧第一摻雜層 11‧‧‧First doped layer
110‧‧‧低摻雜區 110‧‧‧Low doped area
111‧‧‧高摻雜區 111‧‧‧Highly doped area
12‧‧‧第二摻雜層 12‧‧‧Second doped layer
13‧‧‧鈍化層 13‧‧‧ Passivation layer
130‧‧‧鈍化層開口 130‧‧‧passivation opening
14‧‧‧合金層 14‧‧‧ alloy layer
15‧‧‧傳導層 15‧‧‧Transmission layer
150‧‧‧種子層 150‧‧‧ seed layer
151‧‧‧導電層 151‧‧‧ Conductive layer
152‧‧‧保護層 152‧‧‧Protective layer
16‧‧‧背面電極 16‧‧‧Back electrode
17‧‧‧鈍化層 17‧‧‧ Passivation layer
W1、W2、W3、W3’、W4‧‧‧寬度 W1, W2, W3, W3', W4‧‧‧ width
D1、D2‧‧‧深度 D1, D2‧‧ depth
S200~S216‧‧‧步驟 S200~S216‧‧‧Steps
圖1為本發明之一實施例之太陽能電池之剖面示意圖。 1 is a schematic cross-sectional view of a solar cell according to an embodiment of the present invention.
圖1A為本發明之又一實施例之太陽能電池之剖面示意圖。 1A is a schematic cross-sectional view showing a solar cell according to still another embodiment of the present invention.
圖2為本發明之另一實施例之太陽能電池之剖面示意圖。 2 is a schematic cross-sectional view showing a solar cell according to another embodiment of the present invention.
圖3為本發明之一實施例之太陽能電池製造方法之流程圖。 3 is a flow chart of a method of fabricating a solar cell according to an embodiment of the present invention.
圖4a至圖4j為本發明之一實施例之太陽能電池製造方法之剖面示 意圖。 4a to 4j are cross-sectional views showing a method of manufacturing a solar cell according to an embodiment of the present invention; intention.
為讓本發明之上述目的、特徵和特點能更明顯易懂，茲配合圖式將本發明相關實施例詳細說明如下。 The above described objects, features, and characteristics of the present invention will become more apparent from the aspects of the invention.
請參考圖1，其顯示本發明之一實施例之太陽能電池1。該太陽能電池1包含一基板10、一第一摻雜層11、一第二摻雜層12、一鈍化層13及一合金層14。該基板10具有相對應的一第一表面101與一第二表面102。該第一摻雜層11設置於該第一表面上，包含一低摻雜區110及一高摻雜區111。該第二摻雜層12設置於該第二表面102上，並與該第一摻雜層11的摻雜類型不同，亦即該第二摻雜層12與該第一摻雜層11具有不同之電性，例如P+型或N+型。該鈍化層13設置於該第一摻雜層11上，並具有一鈍化層開口130，以裸露出該高摻雜區111的至少一部分區域。該合金層14設置於裸露的該高摻雜區111上。 Please refer to FIG. 1, which shows a solar cell 1 according to an embodiment of the present invention. The solar cell 1 includes a substrate 10, a first doped layer 11, a second doped layer 12, a passivation layer 13, and an alloy layer 14. The substrate 10 has a corresponding first surface 101 and a second surface 102. The first doped layer 11 is disposed on the first surface and includes a low doped region 110 and a highly doped region 111. The second doping layer 12 is disposed on the second surface 102 and is different from the doping type of the first doping layer 11 , that is, the second doping layer 12 is different from the first doping layer 11 . Electrical properties, such as P+ or N+. The passivation layer 13 is disposed on the first doped layer 11 and has a passivation layer opening 130 to expose at least a portion of the highly doped region 111. The alloy layer 14 is disposed on the exposed highly doped region 111.
在本實施例中，該基板10位於該第一摻雜層11與該第二摻雜層12之間。例如該基板10可為N型基板，則該第一摻雜層11之低摻雜區110可為P+型，該第一摻雜層11之高摻雜區111可為P++型，且該第二摻雜層12可為N+型。該第一摻雜層11(P+型及P++型)與該基板10(N型)之間形成p-n接面，即為該太陽能電池1之射極層。需要說明的是，該射極層通常位於該太陽能電池1的受光面，但在其他實施例中，該射極層亦可位於該太陽能電池1的非受光面。此外，在另一實施例中，該基板10可為P型基板，則相應的該低摻雜區110可為N+型、該高摻雜區111可為N++型，且該第二摻雜層12可為P+型。 In this embodiment, the substrate 10 is located between the first doped layer 11 and the second doped layer 12 . For example, the substrate 10 may be an N-type substrate, and the low doped region 110 of the first doped layer 11 may be a P+ type, and the highly doped region 111 of the first doped layer 11 may be a P++ type, and the first The two doped layers 12 may be of the N+ type. The first doped layer 11 (P+ type and P++ type) and the substrate 10 (N type) form a p-n junction, which is the emitter layer of the solar cell 1. It should be noted that the emitter layer is usually located on the light receiving surface of the solar cell 1. However, in other embodiments, the emitter layer may also be located on the non-light receiving surface of the solar cell 1. In addition, in another embodiment, the substrate 10 can be a P-type substrate, and the corresponding low doped region 110 can be of the N+ type, and the highly doped region 111 can be of the N++ type, and the second doped layer 12 can be P+ type.
在本實施例中，該基板10可為一矽基板，且該合金層14可為一矽化鎳層。請再參考圖1，該太陽能電池1更包含一傳導層15，其設置於該合金層14上。該傳導層15包含一種子層150、一導電層151及一保護層152，其依序設置於該合金層14上，例如該種子層150為鎳所製，該導電層151為銅所製， 以及該保護層152為錫或銀所組成，亦即該傳導層15由鎳、銅、錫或銀所組成。詳言之，該種子層150及該合金層14可組合而作為歐姆接觸層，該導電層151可設置於該歐姆接觸金屬層上，且該保護層152可作為焊接用金屬層並設置於該導電層151上，此外，藉由該保護層152的包覆亦可防止導電層151中的銅產生氧化。在本實施例中，該導電層151之寬度W3大於該種子層150之寬度W4，如圖1所示。在另一實施例中，該導電層151之寬度W3’等於該種子層150之寬度W4，如圖2所示。 In this embodiment, the substrate 10 can be a germanium substrate, and the alloy layer 14 can be a nickel-deposited layer. Referring to FIG. 1 again, the solar cell 1 further includes a conductive layer 15 disposed on the alloy layer 14. The conductive layer 15 includes a sub-layer 150, a conductive layer 151 and a protective layer 152, which are sequentially disposed on the alloy layer 14. For example, the seed layer 150 is made of nickel, and the conductive layer 151 is made of copper. And the protective layer 152 is composed of tin or silver, that is, the conductive layer 15 is composed of nickel, copper, tin or silver. In detail, the seed layer 150 and the alloy layer 14 may be combined as an ohmic contact layer, the conductive layer 151 may be disposed on the ohmic contact metal layer, and the protective layer 152 may be used as a metal layer for soldering and disposed on the layer On the conductive layer 151, in addition, the copper in the conductive layer 151 can be prevented from being oxidized by the coating of the protective layer 152. In this embodiment, the width W3 of the conductive layer 151 is greater than the width W4 of the seed layer 150, as shown in FIG. In another embodiment, the width W3' of the conductive layer 151 is equal to the width W4 of the seed layer 150, as shown in FIG.
請再參考圖1與圖2，該傳導層15及該合金層14之組合可稱為該太陽能電池1之正面電極。該太陽能電池1更包含一背面電極16，其設置於該第二摻雜層12上。 Referring to FIG. 1 and FIG. 2 again, the combination of the conductive layer 15 and the alloy layer 14 may be referred to as a front electrode of the solar cell 1. The solar cell 1 further includes a back electrode 16 disposed on the second doped layer 12.
請參考圖1A，在又一實施例中，該太陽能電池於該第二摻雜層12上還包含一鈍化層17，故該背面電極16係貫穿該鈍化層17與該第二摻雜層12電性連結。需要說明的是，該背面電極16亦可如圖2所示之態樣。 Referring to FIG. 1A , in another embodiment, the solar cell further includes a passivation layer 17 on the second doped layer 12 , so that the back surface electrode 16 extends through the passivation layer 17 and the second doped layer 12 . Electrical connection. It should be noted that the back electrode 16 can also be in the form shown in FIG. 2 .
因實作上，該合金層(例如矽化鎳)的形成不易控制，導致合金層之寬度或深度易超出射極層剖面而造成分流現象。本實施例之特點為：該合金層14設置於裸露的該高摻雜區111上，該高摻雜區111之寬度W1大於該合金層14之寬度W2，且該高摻雜區111的深度D1大於該低摻雜區110的深度D2。 In practice, the formation of the alloy layer (for example, nickel telluride) is difficult to control, resulting in the width or depth of the alloy layer easily exceeding the cross section of the emitter layer to cause a shunt phenomenon. The embodiment is characterized in that the alloy layer 14 is disposed on the exposed highly doped region 111. The width W1 of the highly doped region 111 is greater than the width W2 of the alloy layer 14, and the depth of the highly doped region 111 is D1 is greater than the depth D2 of the low doped region 110.
主要目的為該高摻雜區111之寬度W1大於該合金層14之寬度W2時，可確保該合金層14形成的時候在歐姆接觸區域的邊緣不會發生射極層分流的現象。例如，該合金層14之寬度為20微米時，則該高摻雜區111之寬度必須大於20微米。另外，理想中該高摻雜區111之寬度W1小於該合金層14寬度W2之四倍。 The main purpose is that when the width W1 of the highly doped region 111 is larger than the width W2 of the alloy layer 14, it is ensured that the formation of the alloy layer 14 does not occur at the edge of the ohmic contact region. For example, when the width of the alloy layer 14 is 20 microns, the width of the highly doped region 111 must be greater than 20 microns. Further, it is desirable that the width W1 of the highly doped region 111 is less than four times the width W2 of the alloy layer 14.
再者，該高摻雜區111之深度D1大於該低摻雜區110之深度D2時，則可在歐姆接觸區域附近形成較深的射極層剖面，亦可避免該合金層14形成的時候在射極層剖面的邊緣發生射 極層分流的現象。例如，該低摻雜區110之深度D2為0.1微米時，該高摻雜區111之深度D1必須大於0.1微米。另外，理想中該高摻雜區111之深度D1可小於該低摻雜區深度D2之三倍，即具有較佳的射極層剖面。 Moreover, when the depth D1 of the highly doped region 111 is greater than the depth D2 of the low doped region 110, a deeper emitter layer profile can be formed in the vicinity of the ohmic contact region, and the alloy layer 14 can be prevented from being formed. Shooting at the edge of the emitter layer profile The phenomenon of splitting the poles. For example, when the depth D2 of the low doped region 110 is 0.1 micrometer, the depth D1 of the highly doped region 111 must be greater than 0.1 micrometer. In addition, the depth D1 of the highly doped region 111 may ideally be less than three times the depth D2 of the low doped region, that is, having a better emitter layer profile.
當該合金層14(例如矽化鎳)形成的時候在歐姆接觸區域的邊緣不會發生射極層分流(emitter shunting)的現象時，可讓非歐姆接觸區域與歐姆接觸區域都有較低的載子複合機率，確保太陽能電池具有較高的開路電壓(Voc)，並避免導致電池轉換效率降低。 When the alloy layer 14 (for example, nickel telluride) is formed, the emitter shunting phenomenon does not occur at the edge of the ohmic contact region, so that the non-ohmic contact region and the ohmic contact region have lower loads. The sub-combination rate ensures that the solar cell has a high open circuit voltage (Voc) and avoids a reduction in battery conversion efficiency.
請參考圖3，其顯示本發明之一實施例之太陽能電池製造方法，包含下列步驟： Please refer to FIG. 3, which illustrates a solar cell manufacturing method according to an embodiment of the present invention, including the following steps:
在步驟S200中，請參考圖4a，提供一基板10，具有相對應的一第一表面101及一第二表面102。該太陽能電池製造方法可更包括：將該基板10之第一表面101進行粗糙化。該基板10可為一N型或P型矽基板。 In step S200, referring to FIG. 4a, a substrate 10 having a corresponding first surface 101 and a second surface 102 is provided. The solar cell manufacturing method may further include roughening the first surface 101 of the substrate 10. The substrate 10 can be an N-type or P-type germanium substrate.
在步驟S202中，形成一第一摻雜層11於該第一表面101上，包含一低摻雜區110及一高摻雜區111，其中該高摻雜區111之深度大於該低摻雜區110之深度。當該基板10為N型時，該第一摻雜層11之低摻雜區110可為P+型材質，且該第一摻雜層11之高摻雜區111可為P++型材質。 In step S202, a first doped layer 11 is formed on the first surface 101, and includes a low doped region 110 and a highly doped region 111, wherein the high doped region 111 has a depth greater than the low doping region. The depth of zone 110. When the substrate 10 is of the N-type, the low-doped region 110 of the first doped layer 11 may be a P+ type material, and the highly doped region 111 of the first doped layer 11 may be a P++ type material.
形成該第一摻雜層11的步驟包含：請參考圖4b，利用一第一摻雜製程，形成該低摻雜區110於該第一表面101；以及，請參考圖4c，利用一第二摻雜製程，於該低摻雜區110的部分區域形成該高摻雜區111。該第一及第二摻雜製程可選自離子佈植製程、二次擴散製程及摻雜膠網印(doping paste print)製程所構成之群組的其中至少一種。舉例，該第一及第二摻雜製程皆採用離子佈植製程，先利用該離子佈植製程摻雜一段時間以形成該低摻雜區110於該第一表面101，然後再利用該離子佈植製程於該低摻雜區110的部分區域繼續摻雜另一段時間以形成該高 摻雜區111。 The step of forming the first doped layer 11 includes: referring to FIG. 4b, forming the low doped region 110 on the first surface 101 by using a first doping process; and, referring to FIG. 4c, using a second The doping process forms the highly doped region 111 in a portion of the low doped region 110. The first and second doping processes may be selected from at least one of the group consisting of an ion implantation process, a secondary diffusion process, and a doping paste print process. For example, the first and second doping processes all adopt an ion implantation process, and the ion implantation process is first doped for a period of time to form the low doped region 110 on the first surface 101, and then the ion cloth is used. The implant process continues to be doped for a further period of time in a portion of the low doped region 110 to form the high Doped region 111.
在步驟S204中，請參考圖4d，形成一第二摻雜層12於該第二表面102上，其中該第二摻雜層12與該第一摻雜層11的摻雜類型不同。利用一摻雜製程，形成一第二摻雜層12於該第二表面102上。該摻雜製程亦可選自離子佈植製程、二次擴散製程及摻雜膠網印(doping paste print)製程所構成之群組的其中至少一種。當該第一摻雜層11為P型時，該第二摻雜層12可為N+型材質。 In step S204, referring to FIG. 4d, a second doping layer 12 is formed on the second surface 102, wherein the second doping layer 12 is different in doping type from the first doping layer 11. A second doped layer 12 is formed on the second surface 102 by a doping process. The doping process may also be selected from at least one of the group consisting of an ion implantation process, a secondary diffusion process, and a doping paste print process. When the first doped layer 11 is P-type, the second doped layer 12 may be of an N+ type material.
在步驟S206中，請參考圖4e，形成一鈍化層13於該第一摻雜層11上。該鈍化層13可為氮化矽或氧化矽所製。在步驟S208中，請參考圖4f，形成一鈍化層開口130，以裸露出該高摻雜區111的至少一部分區域。 In step S206, referring to FIG. 4e, a passivation layer 13 is formed on the first doped layer 11. The passivation layer 13 can be made of tantalum nitride or hafnium oxide. In step S208, referring to FIG. 4f, a passivation layer opening 130 is formed to expose at least a portion of the region of the highly doped region 111.
在步驟S210中，請參考圖4g，形成一種子層150於該鈍化層開口130上。例如，該種子層150可為鎳所製。在步驟S212中，請參考圖4h，經由退火製程於裸露的該高摻雜區111上形成一合金層14，其中該高摻雜區111之寬度大於該合金層14之寬度。該合金層14可為一矽化鎳層。 In step S210, referring to FIG. 4g, a sub-layer 150 is formed on the passivation layer opening 130. For example, the seed layer 150 can be made of nickel. In step S212, referring to FIG. 4h, an alloy layer 14 is formed on the exposed highly doped region 111 via an annealing process, wherein the width of the highly doped region 111 is greater than the width of the alloy layer 14. The alloy layer 14 can be a nickel-deposited layer.
在步驟S214中，請參考圖4i，形成一導電層151於該種子層150上。該導電層151可為銅所製。在步驟S216中，請參考圖4j，形成一保護層152於該導電層151上。該保護層152可為錫或銀所組成。該種子層150、該導電層151及該保護層152組成一傳導層15，且該傳導層15及該合金層14之組合可稱為一正面電極。 In step S214, referring to FIG. 4i, a conductive layer 151 is formed on the seed layer 150. The conductive layer 151 can be made of copper. In step S216, referring to FIG. 4j, a protective layer 152 is formed on the conductive layer 151. The protective layer 152 can be composed of tin or silver. The seed layer 150, the conductive layer 151 and the protective layer 152 form a conductive layer 15, and the combination of the conductive layer 15 and the alloy layer 14 may be referred to as a front electrode.
另外，在步驟S206之後，該太陽能電池製造方法更選擇性地包括下列步驟：形成一鈍化層17於第二摻雜層12上，如圖1A所示。 In addition, after step S206, the solar cell manufacturing method more selectively includes the step of forming a passivation layer 17 on the second doped layer 12 as shown in FIG. 1A.
此外，在步驟S208之後，該太陽能電池製造方法更包括下列步驟：將一背面電極16形成於該第二摻雜層12上，使該背面電極16與該第二摻雜層12電性連結，如此以完成本發 明之太陽能電池1，如圖1、圖1A或圖2所示。 In addition, after the step S208, the solar cell manufacturing method further includes the following steps: forming a back surface electrode 16 on the second doping layer 12, and electrically connecting the back surface electrode 16 and the second doping layer 12, So to complete the hair The solar cell 1 of the invention is shown in Fig. 1, Fig. 1A or Fig. 2.
綜上所述，乃僅記載本發明為呈現解決問題所採用的技術手段之較佳實施方式或實施例而已，並非用來限定本發明專利實施之範圍。即凡與本發明專利申請範圍文義相符，或依本發明專利範圍所做的均等變化與修飾，皆為本發明專利範圍所涵蓋。 In summary, the present invention is only described as a preferred embodiment or embodiment of the technical means for solving the problem, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made in accordance with the scope of the patent application of the present invention or the scope of the invention are covered by the scope of the invention.
1‧‧‧太陽能電池 1‧‧‧Solar battery
10‧‧‧基板 10‧‧‧Substrate
101‧‧‧第一表面 101‧‧‧ first surface
102‧‧‧第二表面 102‧‧‧ second surface
11‧‧‧第一摻雜層 11‧‧‧First doped layer
110‧‧‧低摻雜區 110‧‧‧Low doped area
111‧‧‧高摻雜區 111‧‧‧Highly doped area
12‧‧‧第二摻雜層 12‧‧‧Second doped layer
13‧‧‧鈍化層 13‧‧‧ Passivation layer
130‧‧‧鈍化層開口 130‧‧‧passivation opening
14‧‧‧合金層 14‧‧‧ alloy layer
15‧‧‧傳導層 15‧‧‧Transmission layer
150‧‧‧種子層 150‧‧‧ seed layer
151‧‧‧導電層 151‧‧‧ Conductive layer
152‧‧‧保護層 152‧‧‧Protective layer
16‧‧‧背面電極 16‧‧‧Back electrode
W1、W2、W3、W4‧‧‧寬度 W1, W2, W3, W4‧‧‧ width
D1、D2‧‧‧深度 D1, D2‧‧ depth
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| TW201511313A (en) * | 2010-12-10 | 2015-03-16 | Teijin Ltd | Semiconductor laminate, semiconductor device and manufacturing method thereof |
| CN103515477A (en) * | 2012-06-22 | 2014-01-15 | Lg电子株式会社 | Method for manufacturing solar cell and dopant layer thereof |
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| CN106887473A (en) | 2017-06-23 |
| TW201724536A (en) | 2017-07-01 |
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