CN108987458A - A kind of two-way low pressure plane transient voltage suppressor diode and its manufacturing method - Google Patents
A kind of two-way low pressure plane transient voltage suppressor diode and its manufacturing method Download PDFInfo
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- 239000010703 silicon Substances 0.000 claims abstract description 69
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- 239000013078 crystal Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000005275 alloying Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
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- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
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- 238000001259 photo etching Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 8
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- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000025274 Lightning injury Diseases 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a kind of two-way low pressure plane transient voltage suppressor diode and its manufacturing methods, including p-type heavily doped silicon substrate；The first front doped region and the first back side doped region are respectively formed in the front and back of substrate, the second front doped region and the second back side doped region are respectively formed by adulterating window diffusing, doping in the front and back of substrate, it is respectively formed with the second front doped region oxide layer and the second back side doped region oxide layer on the second front doped region and the second back side doped region, is formed with front face hole and rear-face contact hole in the second front doped region oxide layer and the second back side doped region oxide layer；Front metal electrode and back metal electrode are respectively formed on front face hole and rear-face contact hole.The present invention increases front identical with silicon substrate doping type doped region and back side doped region, plays adjustment substrate concentration, and the PN junction both ends concentration gradient of formation increases, and mobile ion is reduced, and TVS leakage current reduces.
Description
[technical field]
The invention belongs to semiconductor components and devices technical fields, and in particular to a kind of two-way low pressure plane transient voltage inhibition two
Pole pipe chip and its manufacturing method.
[background technique]
Transient voltage suppressor diode (TVS) at present be widely used in circuit, the network port, accurate device it is quiet
The protection of electricity, surge, lightning stroke etc..Overwhelming majority producer uses pickling (OJ) or glassivation (GPP) mesa technology system both at home and abroad
Make TVS.
In comparison, using planar technology manufacture TVS without fluting, coating glass powder, process equipment is simple, processing week
Phase is short, and technology stability and consistency are more superior.But the lower TVS of voltage, especially breakdown potential are manufactured using planar technology
When pressure is less than 10V, since PN junction breakdown is between avalanche breakdown and tunnel breakdown, this results in TVS " soft breakdown " occur, leakage
Electric current is big.For two-way TVS, since its breakdown voltage compares low 0.7V or so, reverse leakage current with model unidirectional voltage
It is bigger.The big one side of low pressure TVS leakage current can bring energy waste, on the other hand can bring to protection circuit and device potential hidden
Suffer from.
[summary of the invention]
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that providing a kind of two-way low pressure
Plane transient voltage suppressor diode and its manufacturing method solve two-way low pressure plane transient voltage suppressor diode and reversely leak
The big problem of electric current.
The invention adopts the following technical scheme:
A kind of two-way low pressure plane transient voltage suppressor diode, comprising: substrate, the substrate are p-type heavily doped silicon lining
Bottom；It is respectively formed with the first front doped region and the first back side doped region in the front and back of the substrate, described first just
Face doped region and the first back side doped region are identical as the substrate doping type；Pass through doping in the front and back of the substrate
Window diffusing, doping is respectively formed the second front doped region and the second back side doped region, second front doped region and the second back
Face doped region is opposite with the substrate doping type；It is respectively formed on second front doped region and the second back side doped region
There are the second front doped region oxide layer and the second back side doped region oxide layer, the second front doped region oxide layer and the second back
Front face hole and rear-face contact hole are formed in the doped region oxide layer of face；Divide on the front face hole and rear-face contact hole
It is not formed with front metal electrode and back metal electrode.
Further, second front doped region and the second back side doped region junction depth are identical, the second front doped region oxygen
Change layer and the second back side doped region oxidated layer thickness is identical.
Further, second front doped region and the second back side doped region junction depth are 10 μm -20 μm, and the second front is mixed
Miscellaneous area's oxide layer and the second back side doped region oxidated layer thickness are greater than 0.8 μm.Further, the front metal electrode and the back side
Metal electrode is multilayer metallic electrode.
Further, the reverse leakage current of the two-way low pressure plane transient voltage suppressor diode is 10uA~20uA.
A kind of manufacturing method of two-way low pressure plane transient voltage suppressor diode, comprising the following steps:
S1, p-type heavily doped silicon substrate is provided, and P-doped zone is formed to the silicon substrate front and back diffusing, doping,
The doped region is identical as the doping type of the silicon substrate；
S2, doping window is etched in first front doped region and the first back side doped region；
S3, N-doped zone, the doping are formed in the front doped region window and back side doped region window diffusing, doping
Area is opposite with the doping type of the silicon substrate；
S4, front face hole and rear-face contact hole are etched in the front and back of the doped region oxide layer；
S5, evaporation deposition forms front metal layer and metal layer on back in the front face hole and rear-face contact hole；
S6, the etching front metal layer and metal layer on back, form front electrode and rear electrode；
S7, alloying make the front electrode and rear electrode and the silicon substrate form Ohmic contact.
Further, in step S1, the diffusing, doping is spread using two steps, and first step diffusion is pre- on the silicon substrate
Diffuse to form limited boron impurity source；Second step mixes oxychloride when spreading knot depth again, while doping forms doped region,
Layer of oxide layer is respectively formed on first front doped region and the first back side doped region.
Further, in step S1, the resistivity of the p-type heavily doped silicon substrate is 0.003~0.03 Ω m, thickness
It is 180~260 μm.
Further, the p-type heavily doped silicon substrate is 111 crystal orientation.
Further, in step S3, the diffusing, doping is spread using two steps, and first step diffusion is pre- on the silicon substrate
Limited phosphorus impurities source is diffuseed to form, second step mixes oxychloride when spreading knot depth again, while doping forms doped region,
Layer of oxide layer is respectively formed on second front doped region and the second back side doped region.
Compared with prior art, the present invention at least has the advantages that
The present invention increases front identical with silicon substrate doping type doped region and back side doped region, and it is dense to play adjustment substrate
Degree, handles the effect on surface, and after the concentration adjusts and is surface-treated, finally formed PN junction both ends concentration gradient increases,
Mobile ion is reduced, and finally formed TVS leakage current reduces, so that the leakage current of diode is smaller than conventional low voltage product leakage current
An order of magnitude overcomes the shortcomings that low voltage product leakage current reduces leakage current increase with breakdown voltage, has lower electric leakage
Stream, reduce loss in circuit, reduce the interference to circuit, while reducing potential short-circuit risks, product can
By property height.
Further, the junction depth of doped region is identical, and the thickness of oxide layer is identical, constitutes bilateral device, can be two sides
Play the role of protective action upwards, the adjustment layer at the positive back side, which plays, reduces leakage current, the multilayer gold formed using evaporation technology
Belong to electrode, good with silicon ohmic contact characteristic, the clamping voltag of product is low, and surge capacity is strong.
The invention also discloses a kind of manufacturing methods of two-way low pressure plane transient voltage suppressor diode, are different from tradition
Technique increases front and back adjustment layer, but does not need to increase reticle and photoetching number, is not necessarily to photoetching fluting and glass
Passivation, effectively save time and cost reduce the damage in subsequent scribing processing to chip, high yield rate, product parameters
Consistency is good, and yield is high.
Further, oxychloride is mixed using the diffusion of two steps, is capable of fixing mobile ion, can preferably play reduction electric leakage
Effect.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
[Detailed description of the invention]
Fig. 1 is the structural schematic diagram of section in manufacturing process of the present invention；
Fig. 2 is process flow chart of the invention；
Fig. 3 is direction leakage current distribution comparison diagram of the invention.
Wherein: 100. silicon substrates；The first front 110a. doped region；First back side 110b. doped region；The first front 120a.
Oxide layer；The first backside oxide layer of 120b.；The front 130a. doped region window；The back side 130b. doped region window；140a. second
Front doped region；Second back side 140b. doped region；The second front 150a. doped region oxide layer；Second back side 150b. doped region
Oxide layer；106a. front face hole；106b. rear-face contact hole；107a. front metal electrode；107b. back metal electrode.
[specific embodiment]
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply opposite
Importance or the quantity for implicitly indicating indicated technical characteristic.Define " first " as a result, the feature of " second " can be bright
Show or implicitly include one or more of the features.In the description of the present invention, unless otherwise indicated, " multiple " contain
Justice is two or more.
Refering to Figure 1, the invention discloses a kind of two-way low pressure plane transient voltage suppressor diode, structure packet
It includes:
P-type heavily doped silicon substrate 100 is respectively formed with the first front doped region in the front and back of the substrate 100
110a and the first back side doped region 110b, the first front doped region 110a and the first back side doped region 110b and the substrate
100 doping types are identical；Positive doping is respectively formed in the first front doped region 110a and the first back side doped region 110b
Area window 130a and back side doped region window 130b；Expand in the front doped region window 130a and back side doped region window 130b
Scattered doping is respectively formed the second front doped region 140a and the second back side doped region 140b, the second front doped region 140a and
Second back side doped region 140b is opposite with 100 doping type of substrate；It is carried on the back in the second front doped region 140a and second
The second front doped region oxide layer 150a and the second back side doped region oxide layer 150b, institute are respectively formed on the doped region 140b of face
It states and is formed with just after being etched on the second front doped region oxide layer 150a and the second back side doped region oxide layer 150b to fairlead
Face contact hole 160a and rear-face contact hole 160b；It is respectively formed on the front face hole 160a and rear-face contact hole 160b
Front metal electrode 170a and back metal electrode 170b.It is different from traditional handicraft, is increased identical as 100 doping type of silicon substrate
The first front doped region 110a and the first back side doped region 110b, play the role of adjustment substrate concentration, handle surface.By
After concentration adjustment and surface treatment, finally formed PN junction both ends concentration gradient increases, and mobile ion is reduced, finally formed
TVS leakage current reduces.
The present invention forms multilayer metallic electrode using evaporation technology, is different from traditional chemical nickel coating electrode, the multiple layer metal
Electrode is good with silicon ohmic contact characteristic, and the clamping voltag of product is low, and surge capacity is strong.
It please refers to shown in Fig. 2, the specific step of the production method of the two-way low pressure plane transient voltage suppressor diode of the present invention
Suddenly include:
S1: a silicon substrate is provided, and doped region, the doped region are formed to the silicon substrate front and back diffusing, doping
It is identical as the doping type of the silicon substrate, constitute p-type adjustment layer.
S2: doping window is etched in first front doped region and the first back side doped region.
S3: N-doped zone, the doped region and the silicon are formed in the above front and back doped region window diffusing, doping
The doping type of substrate is opposite.
S4: front face hole and rear-face contact hole are etched in silicon substrate front and back.
S5: evaporation forms front metal layer and metal layer on back in the contact hole.
S6: etching the front metal layer and metal layer on back, forms front electrode and rear electrode.
S7: alloying makes the front electrode and rear electrode and the silicon substrate form Ohmic contact.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being described and shown in usually here in attached drawing is real
The component for applying example can be arranged and be designed by a variety of different configurations.Therefore, below to the present invention provided in the accompanying drawings
The detailed description of embodiment be not intended to limit the range of claimed invention, but be merely representative of of the invention selected
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative efforts
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Below in conjunction with the manufacturing method of the two-way low pressure plane transient voltage suppressor diode of the detailed description present invention of Fig. 1.
Embodiment 1
One, a heavily doped silicon substrate 100 is provided.
In the present embodiment, the silicon substrate is P+ silicon substrate.The resistivity of the P+ silicon substrate 0.003 Ω m it
Between, 111 crystal orientation, with a thickness of 180 μm.
Two, to the front and back of silicon substrate 100, diffusing, doping forms doped region simultaneously.
The front doped region of silicon substrate 100 is referred to as the first front doped region 110a, and back side doped region is referred to as the first back
Face doped region 110b, the doping type and the silicon substrate of the first front doped region 110a and the first back side doped region 110b
100 doping types are identical.
Preferably, diffusing, doping is spread using two steps:
Prediffusion forms limited B impurity source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
Layer of oxide layer is formed in the upper surface of described doped region while doping forms doped region, is formed and described first
Oxide layer on the doped region 110a of front is referred to as the first frontside oxide layer 120a, is formed and first back side doped region 110b
On oxide layer be referred to as the first backside oxide layer 120b.The first front doped region 110a and the first back side doped region 110b
Junction depth is identical, less than 6 μm；The first frontside oxide layer 120a and the first backside oxide layer 120b thickness are identical, are greater than 0.8 μ
m。
Three, in the first back of the positive first frontside oxide layer 120a of the silicon substrate 100 and 100 back side of the silicon substrate
Photoetching on the oxide layer 120b of face etches front doped region window and back side doped region window, is referred to as front doped region
Window 130a and back side doped region window 130b.
Four, in the front doped region window 130a and back side doped region window 130b while diffusing, doping, second is formed
Front doped region and the second back side doped region are referred to as the second front doped region 140a and the second back side doped region 140b.
The doping type of the second front doped region 140a and the second back side doped region 140b and the silicon substrate 100 adulterate class
Type is opposite.
Preferable diffusing, doping is using two diffusions:
Prediffusion forms limited phosphorus impurities source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
Layer of oxide layer is formed in the upper surface of described doped region while doping forms doped region, is formed and described second
Oxide layer on the doped region 140a of front is referred to as the second frontside oxide layer 150a, is formed and second back side doped region 140b
On oxide layer be referred to as the second backside oxide layer 150b.The second front doped region 140a and the second back side doped region 140b
Junction depth is identical, with a thickness of 10 μm；The second frontside oxide layer 150a and the second backside oxide layer 150b thickness are identical, are greater than
0.8μm。
Five, the photoetching on the second frontside oxide layer 150a and the second backside oxide layer 150b, etches front respectively
Contact hole and rear-face contact hole are referred to as front face hole 160a and rear-face contact hole 160b.
Six, evaporation deposition is more on evaporation deposition multiple layer metal and rear-face contact hole 160b on the front face hole 160a
Layer metal, and metal electrode is etched to front metal and back metal photoetching respectively, finally to front metal electrode and the back side
Metal electrode vacuum alloy forms the good front electrode of Ohmic contact and rear electrode, is referred to as front metal electrode
170a and back metal electrode 170b.
Embodiment 2
One, a heavily doped silicon substrate 100 is provided.The resistivity of the P+ silicon substrate is between 0.01 Ω m, 111 crystal orientation,
With a thickness of 200 μm.
Two, to the front and back of silicon substrate 100, diffusing, doping forms the back of the first front doped region 110a and first simultaneously
Face doped region 110b, the doping type and the silicon substrate of the first front doped region 110a and the first back side doped region 110b
100 doping types are identical.
Using two step diffusing, dopings:
Prediffusion forms limited B impurity source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
The first frontside oxide layer 120a is formed on the first front doped region 110a while doping forms doped region, the
The first backside oxide layer 120b is formed on one back side doped region 110b.The first front doped region 110a and the doping of first back side
Area's 110b junction depth is identical, and respectively less than 6 μm；The first frontside oxide layer 120a and the first backside oxide layer 120b thickness are identical,
Greater than 0.8 μm.
Three, the photoetching on the first frontside oxide layer 120a and the first backside oxide layer 120b, etches front doped region window
Mouth 130a and back side doped region window 130b.
Four, in the front doped region window 130a and back side doped region window 130b while diffusing, doping, second is formed
Front doped region 140a and the second back side doped region 140b.The second front doped region 140a and the second back side doped region
The doping type of 140b and 100 doping type of silicon substrate are opposite.
Using two step diffusing, dopings:
Prediffusion forms limited phosphorus impurities source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
The second frontside oxide layer 150a is formed on the second front doped region 140a while doping forms doped region,
The second backside oxide layer 150b is formed on second back side doped region 140b.The second front doped region 140a and second back side are mixed
Miscellaneous area 140b junction depth is identical, with a thickness of 14 μm；The second frontside oxide layer 150a and the second backside oxide layer 150b thickness phase
Together, it is greater than 0.8 μm.
Five, made by lithography on the second frontside oxide layer 150a and the second backside oxide layer 150b be positive face contact hole 160a and
Rear-face contact hole 160b.
Six, the evaporation deposition multiple layer metal on front face hole 160a and rear-face contact hole 160b, and respectively to positive gold
Category and back metal photoetching, etch metal electrode, are finally formed to front metal electrode and back metal electrode vacuum alloy
Ohmic contact good front metal electrode 170a and back metal electrode 170b.
Embodiment 3
One, a heavily doped silicon substrate 100 is provided.The resistivity of the P+ silicon substrate is between 0.02 Ω m, 111 crystal orientation,
With a thickness of 240 μm.
Two, to the front and back of silicon substrate 100, diffusing, doping forms the back of the first front doped region 110a and first simultaneously
Face doped region 110b, the doping type and the silicon substrate of the first front doped region 110a and the first back side doped region 110b
100 doping types are identical.
Using two step diffusing, dopings:
Prediffusion forms limited B impurity source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
The first frontside oxide layer 120a is formed on the first front doped region 110a while doping forms doped region, the
The first backside oxide layer 120b is formed on one back side doped region 110b.The first front doped region 110a and the doping of first back side
Area's 110b junction depth is identical, and respectively less than 6 μm；The first frontside oxide layer 120a and the first backside oxide layer 120b thickness are identical,
Greater than 0.8 μm.
Three, the photoetching on the first frontside oxide layer 120a and the first backside oxide layer 120b, etches front doped region window
Mouth 130a and back side doped region window 130b.
Four, in the front doped region window 130a and back side doped region window 130b while diffusing, doping, second is formed
Front doped region 140a and the second back side doped region 140b.The second front doped region 140a and the second back side doped region
The doping type of 140b and 100 doping type of silicon substrate are opposite.
Using two diffusing, dopings:
Prediffusion forms limited phosphorus impurities source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
The second frontside oxide layer 150a is formed on the second front doped region 140a while doping forms doped region,
The second backside oxide layer 150b is formed on second back side doped region 140b.Second front doped region 140a and the second back side doped region
140b junction depth is identical, with a thickness of 18 μm；Second frontside oxide layer 150a and the second backside oxide layer 150b thickness are identical, are greater than
0.8μm。
Five, made by lithography on the second frontside oxide layer 150a and the second backside oxide layer 150b be positive face contact hole 160a and
Rear-face contact hole 160b.
Six, the evaporation deposition multiple layer metal on the front face hole 160a and rear-face contact hole 160b, and respectively to just
Face metal and back metal photoetching, etch metal electrode, finally to front metal electrode and back metal electrode vacuum alloy
Form the good front metal electrode 170a and back metal electrode 170b of Ohmic contact.
Embodiment 4
One, a heavily doped silicon substrate 100 is provided.The resistivity of the P+ silicon substrate is between 0.03 Ω m, 111 crystal orientation,
With a thickness of 260 μm.
Two, to the front and back of silicon substrate 100, diffusing, doping forms the back of the first front doped region 110a and first simultaneously
Face doped region 110b, the doping type and the silicon substrate of the first front doped region 110a and the first back side doped region 110b
100 doping types are identical.
Using two step diffusing, dopings:
Prediffusion forms limited B impurity source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
The first frontside oxide layer 120a is formed on the first front doped region 110a while doping forms doped region, the
The first backside oxide layer 120b is formed on one back side doped region 110b.The first front doped region 110a and the doping of first back side
Area's 110b junction depth is identical, and respectively less than 6 μm；The first frontside oxide layer 120a and the first backside oxide layer 120b thickness are identical,
Greater than 0.8 μm.
Three, the photoetching on the first frontside oxide layer 120a and the first backside oxide layer 120b, etches front doped region window
Mouth 130a and back side doped region window 130b.
Four, in the front doped region window 130a and back side doped region window 130b while diffusing, doping, second is formed
Front doped region 140a and the second back side doped region 140b.The second front doped region 140a and the second back side doped region
The doping type of 140b and 100 doping type of silicon substrate are opposite.
Using two diffusing, dopings:
Prediffusion forms limited phosphorus impurities source on the silicon substrate for first step diffusion；
Second step mixes oxychloride when spreading knot depth again.
The second frontside oxide layer 150a is formed on the second front doped region 140a while doping forms doped region,
The second backside oxide layer 150b is formed on second back side doped region 140b.The second front doped region 140a and second back side are mixed
Miscellaneous area 140b junction depth is identical, with a thickness of 20 μm；The second frontside oxide layer 150a and the second backside oxide layer 150b thickness phase
Together, it is greater than 0.8 μm.
Five, made by lithography on the second frontside oxide layer 150a and the second backside oxide layer 150b be positive face contact hole 160a and
Rear-face contact hole 160b.
Six, the evaporation deposition multiple layer metal on front face hole 160a and rear-face contact hole 160b, and respectively to positive gold
Category and back metal photoetching, etch metal electrode, are finally formed to front metal electrode and back metal electrode vacuum alloy
Ohmic contact good front metal electrode 170a and back metal electrode 170b.
It please refers to shown in Fig. 3, two-way low pressure plane transient voltage suppressor diode of the invention and its manufacturing method can have
The leakage current of the reduction low pressure TVS of effect.The reverse leakage current of TVS of the present invention is in 10~20uA, with the reversed leakage of model routine TVS
Electric current is between 190~270uA.
The leakage current of two-way low pressure plane transient voltage suppressor diode of the invention is smaller than conventional low voltage product leakage current
An order of magnitude overcomes the shortcomings that low voltage product leakage current reduces leakage current increase with breakdown voltage.It is provided by the invention double
To low pressure plane transient voltage suppressor diode due to reducing loss in circuit, reducing with lower leakage current
Interference to circuit, while potential short-circuit risks are reduced, therefore the high reliablity of product.
Two-way low pressure plane transient voltage suppressor diode manufacturing method provided by the invention is joined by increasing with silicon substrate
The then identical front doped region of type and back side doped region play the role of adjusting substrate surface concentration, handle substrate surface, energy
Enough leakage currents for greatly reducing TVS.Conventional chemical nickel coating electrode, electrode and silicon ohm are substituted by using multilayer metallic electrode
Contact performance is good, plays the role of reducing clamping voltag and improves surge capacity.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press
According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention
Protection scope within.
Claims (10)
1. a kind of two-way low pressure plane transient voltage suppressor diode characterized by comprising
Substrate, the substrate are p-type heavily doped silicon substrate；
It is respectively formed with the first front doped region and the first back side doped region in the front and back of the substrate, described first just
Face doped region and the first back side doped region are identical as the substrate doping type；
The second front doped region and the second back are respectively formed by adulterating window diffusing, doping in the front and back of the substrate
Face doped region, second front doped region and the second back side doped region are opposite with the substrate doping type；
The second front doped region oxide layer and are respectively formed on second front doped region and the second back side doped region
Front is formed in two back side doped region oxide layers, the second front doped region oxide layer and the second back side doped region oxide layer
Contact hole and rear-face contact hole；
Front metal electrode and back metal electrode are respectively formed on the front face hole and rear-face contact hole.
2. a kind of two-way low pressure plane transient voltage suppressor diode according to claim 1, which is characterized in that described
Two front doped regions and the second back side doped region junction depth are identical, the second front doped region oxide layer and the oxidation of the second back side doped region
Thickness degree is identical.
3. a kind of two-way low pressure plane transient voltage suppressor diode according to claim 2, which is characterized in that described
Two front doped regions and the second back side doped region junction depth are 10~20 μm, the second front doped region oxide layer and the doping of second back side
Area's oxidated layer thickness is greater than 0.8 μm.
4. a kind of two-way low pressure plane transient voltage suppressor diode according to claim 1, which is characterized in that it is described just
Face metal electrode and back metal electrode are multilayer metallic electrode.
5. a kind of two-way low pressure plane transient voltage suppressor diode according to any one of claim 1 to 4, feature
Be: the reverse leakage current of the two-way low pressure plane transient voltage suppressor diode is 10~20uA.
6. the method for two-way low pressure plane transient voltage suppressor diode described in a kind of any one of manufacturing claims 1 to 5,
It is characterized in that, comprising the following steps:
S1, p-type heavily doped silicon substrate is provided, and P-doped zone is formed to the silicon substrate front and back diffusing, doping, it is described
Doped region is identical as the doping type of silicon substrate；
S2, doping window is etched in the first front doped region and the first back side doped region；
S3, form N-doped zone in the front doped region window and back side doped region window diffusing, doping, the doped region with
The doping type of the silicon substrate is opposite；
S4, front face hole and rear-face contact hole are etched in the front and back of doped region oxide layer；
S5, evaporation deposition forms front metal layer and metal layer on back in front face hole and rear-face contact hole；
S6, etch front metal layer and metal layer on back form front electrode and rear electrode；
S7, alloying make the front electrode and rear electrode and silicon substrate form Ohmic contact.
7. a kind of manufacturing method of two-way low pressure plane transient voltage suppressor diode according to claim 6, feature
It is, in step S1, diffusing, doping is spread using two steps, and to form limited boron miscellaneous for prediffusion on the silicon substrate for first step diffusion
Matter source；Second step mixes oxychloride when spreading knot depth again, while doping forms doped region, in the first front doped region and
Layer of oxide layer is respectively formed on first back side doped region.
8. a kind of manufacturing method of two-way low pressure plane transient voltage suppressor diode according to claim 7, feature
It is, in step S1, the resistivity of the p-type heavily doped silicon substrate is 0.003~0.03 Ω cm, with a thickness of 180~260 μ
m。
9. a kind of manufacturing method of two-way low pressure plane transient voltage suppressor diode according to claim 8, feature
It is, the p-type heavily doped silicon substrate is 111 crystal orientation.
10. a kind of manufacturing method of two-way low pressure plane transient voltage suppressor diode according to claim 6, feature
Be, in step S3, the diffusing, doping using two steps spread, the first step diffusion on the silicon substrate prediffusion formed it is limited
Phosphorus impurities source, second step mix oxychloride when spreading knot depth again, while doping forms doped region, in the second front doping
Layer of oxide layer is respectively formed on area and the second back side doped region.
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| CN114038900A (en) * | 2021-09-27 | 2022-02-11 | 安徽芯旭半导体有限公司 | TVS chip and production method thereof |
| CN118412276A (en) * | 2024-06-28 | 2024-07-30 | 江西萨瑞微电子技术有限公司 | Bidirectional TVS chip and preparation method thereof |
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| CN105355654A (en) * | 2015-10-13 | 2016-02-24 | 上海瞬雷电子科技有限公司 | Low-voltage transient-suppression diode chip with low electric leakage and high reliability and production method |
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| CN118412276B (en) * | 2024-06-28 | 2024-09-06 | 江西萨瑞微电子技术有限公司 | Bidirectional TVS chip and preparation method thereof |
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