CN207068844U - Transient voltage suppressor - Google Patents
Transient voltage suppressor Download PDFInfo
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- CN207068844U CN207068844U CN201720896650.8U CN201720896650U CN207068844U CN 207068844 U CN207068844 U CN 207068844U CN 201720896650 U CN201720896650 U CN 201720896650U CN 207068844 U CN207068844 U CN 207068844U
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- epitaxial layer
- isolated island
- transient voltage
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Abstract
The utility model discloses a kind of Transient Voltage Suppressor, the Transient Voltage Suppressor includes Semiconductor substrate；Epitaxial layer on the Semiconductor substrate first surface；Isolated area, extended to from the surface of the epitaxial layer through the epitaxial layer in the Semiconductor substrate, for limiting the first isolated island and the second isolated island in the epitaxial layer；Doped region, extended to respectively in first isolated island and the second isolated island from the surface of the epitaxial layer in the epitaxial layer；First electrode, for each doped region to be electrically connected to each other；And second electrode, the part for the isolated area and the epitaxial layer to be located to second isolated island are electrically connected to each other.The Transient Voltage Suppressor by by one in two longitudinal NPN structures of parallel connection by metal electrode short circuit into PN, become the Transient Voltage Suppressor of unidirectional low clamp voltage, be advantageous to reduce chip size and reduce packaging cost.
Description
Technical field
Semiconductor devices and its manufacture method are the utility model is related to, more particularly, to a kind of Transient Voltage Suppressor.
Background technology
((Transient Voltage Suppressor, TVS) is to be used to protect integrated circuit to exempt to Transient Voltage Suppressor
The device damaged by overvoltage.Designed integrated circuit is worked in the normal range (NR) of voltage.However, static discharge
Unpredictable caused by the fortuitous event such as (Electronic Static Discharge, ESD), electric fast transient and lightning,
Uncontrollable high voltage, circuit can be caused damage.When this high voltage produces, it is necessary to TVS device protects integrated circuit,
Evade these situations that may damage integrated circuit.
Unidirectional TVS device is widely used in the integrated circuit for protecting above-mentioned application.This kind of device is limited to their work
Mode.When moment direct circulation (i.e. positive voltage peak), unidirectional TVS device reverse bias.Device is run under avalanche mode, by wink
State electric current introduces ground connection.Transient state is by the embedding clamp energy level made and provided in TVS device by TVS device, it is ensured that to the guarantor of integrated circuit
Shield.When the negative circulation (i.e. negative voltage peak) of transient state, unidirectional TVS device forward bias, electric current is along forward conduction.
When carrying out the design of unidirectional TVS device, it is typically only possible by adjusting the resistivity of substrate to control unijunction voltage,
But when wishing that voltage is further reduced to below 6V, because the breakdown of single base diode will be based on Zener breakdown, leakage current
What is become is uncontrollable, therefore conventional single base diode can not meet the application environment of below 6V low-leakage current requirements.
In order to meet the requirement under low clamp voltage to TVS device low-leakage current, those skilled in the art are inclined to use NPN
Audion, Vce is reduced by increasing β method, or use a general-purpose diode and a two-way low clamp TVS device
The method of part encapsulation in parallel, to realize low-work voltage and low clamp voltage, but the TVS devices obtained using NPN triode structures
Part is bi-directional configuration, can not meet the application environment of some unidirectional TVS devices, and uses second method, although can realize
The function of unidirectional low clamp TVS device, but due to needing the method by multi-chip assembled package to realize, packaging cost will be big
It is big to improve.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of Transient Voltage Suppressor of one-way conduction, and it can be with
Applied to the electronic device of low clamp voltage, while there is relatively low packaging cost.
In order to solve the above-mentioned technical problem, according to the utility model, there is provided a kind of Transient Voltage Suppressor, including：First
The Semiconductor substrate of doping type；The epitaxial layer of the second doping type on the Semiconductor substrate first surface, wherein
First doping type is different from the second doping type；The isolated area of first doping type, institute is passed through from the surface of the epitaxial layer
State epitaxial layer to extend in the Semiconductor substrate, for limiting the first isolated island and the second isolated island in the epitaxial layer；
The doped region of first doping type, extend respectively in first isolated island and the second isolated island from the surface of the epitaxial layer
Into the epitaxial layer；First electrode, for each doped region to be electrically connected to each other；And second electrode, for by described in
The part that isolated area and the epitaxial layer are located at second isolated island is electrically connected to each other.
Preferably, in addition to the insulating barrier on the epitaxial layer.
Preferably, in addition to the 3rd electrode, the 3rd electrode is located at the second surface of the Semiconductor substrate, and described
One surface and the second surface are relative to each other.
Preferably, second active area surrounds first active area.
Preferably, first doping type is N-type or p-type, and second doping type is another in N-type or p-type
It is individual.
After the technical solution of the utility model, following beneficial effect can be obtained：
By by parallel connection two longitudinal NPN structures in one by metal electrode short circuit into PN, become
The Transient Voltage Suppressor of unidirectional low clamp voltage, is advantageous to reduce chip size and reduces packaging cost.
Brief description of the drawings
By the description to utility model embodiment referring to the drawings, of the present utility model above-mentioned and other purposes,
Feature and advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the structure chart for the Transient Voltage Suppressor that the utility model first embodiment provides.
Fig. 2 a to 2f show each rank of manufacture method according to the Transient Voltage Suppressor of the utility model first embodiment
The sectional view of section.
Embodiment
The utility model is described below based on embodiment, but the utility model is not restricted to these implementations
Example.It is detailed to describe some specific detail sections below in the detailed description of the utility model embodiment, to this area
The description of part can also understand the utility model completely without these details for technical staff.In order to avoid obscuring this practicality
New essence, known method, process, flow do not describe in detail.
In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in accompanying drawing
Various pieces are not necessarily to scale.In addition, some known parts may be not shown in figure.Flow chart, frame in accompanying drawing
Figure illustrates possible System Framework, function and the operation of the system of embodiment of the present utility model, method, apparatus, accompanying drawing
Square frame and square frame order are used only to the process and step of preferably diagram embodiment, without should be in this, as to utility model
The limitation of itself.
The utility model is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is using similar
Reference represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Furthermore, it is possible to it is not shown
Some known parts.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.
It should be appreciated that in the structure of outlines device, it is referred to as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Other layers or region are also included between individual region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
It describe hereinafter many specific details of the present utility model, such as the structure of device, material, size, place
Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand,
The utility model can not be realized according to these specific details.
Fig. 1 shows the structure chart for the Transient Voltage Suppressor that the utility model first embodiment provides.Description below
In, the doping type by description semi-conducting material is specially one of p-type and N-type.If it is appreciated that invert each semiconductor material
The doping type of material, it is also possible to obtain the semiconductor devices of identical function.
As shown in figure 1, TVS device 100 is outer including Semiconductor substrate 101, on the first surface of Semiconductor substrate 101
Prolong layer 102, the isolated area 103 in epitaxial layer 102 and the doped region 104 in epitaxial layer 102.
Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, and epitaxial layer 102 is, for example, p-type epitaxial layer.For
Formation p-type or n type semiconductor layer or region, the dopant of respective type can be mixed in semiconductor layer or region.For example,
P-type dopant includes boron, and N type dopant includes phosphorus or arsenic or antimony.
In this embodiment, Semiconductor substrate 101 is the heavily doped N-type substrate that resistivity is not more than 0.02 Ω cm.Outside
Prolong the p-type epitaxial layer 102 that layer 102 is not less than 0.01 Ω cm for resistivity, thickness is not less than 2 μm.
Isolated area 103 is, for example, the n-type doping area of heavy doping, and isolated area 103 extends to semiconductor from the surface of epitaxial layer 102
Substrate 101, so as to limit a plurality of isolated islands in epitaxial layer 102.In the present embodiment, the second isolated island is around the first isolation
Island.Those skilled in the art can control the concentration of isolated area 103 according to device requirement, such as not less than E19cm-3。
Doped region 104 is, for example, that concentration is not less than E19cm-3Heavy doping n-type doping area 104, its respectively positioned at respectively every
In Li Island, extended to by the surface of epitaxial layer 102 in epitaxial layer 102.
Further, TVS device 100 also includes insulating barrier 105, first electrode 106, the electrode of second electrode 107 and the 3rd
108。
Insulating barrier 105 is located on epitaxial layer 102, and first electrode 106 passes through the opening in insulating barrier 105 by each doped region
104 electrical connections, second electrode 107 pass through the opening in insulating barrier 105 that part isolated area 103 and epitaxial layer 102 are located at into second
The part of isolated island is electrically connected to each other, and the 3rd electrode 108 is located on the second surface of Semiconductor substrate 101, second surface and
One surface is relative to each other.Insulating barrier 105 is for example made up of silica or silicon nitride, first electrode 106, second electrode 107 and
3rd electrode 108 is selected from the metal or alloy such as gold, silver, copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold composition.
In the TVS device 100 shown in Fig. 1, Semiconductor substrate 101, epitaxial layer 102 be located at the part of the first isolated island with
And the doped region 104 in the part forms the lamination of first NPN structure, Semiconductor substrate 101, epitaxial layer 102 are located at
The part of second isolated island and the doped region 104 in the part form the lamination of second NPN structure, first electrode
106 is in parallel by two NPN structures.Wherein, due to second electrode 107 by epitaxial layer 102 be located at the second isolated island part and every
From the short circuit of area 103, therefore the lamination practical function of second NPN structure is identical with the lamination of PN.Turned in the PN
When, as shown in phantom in fig. 1, i.e. electric current is from first electrode 106, doped region 104, epitaxial layer 102 for the flow direction of electric current
Part, second electrode 107 in the second isolated island, isolated area 103 flow to Semiconductor substrate 101.
Fig. 2 a to 2f show each rank of manufacture method according to the Transient Voltage Suppressor of the utility model first embodiment
The sectional view of section.
As shown in Figure 2 a, p-type epitaxial layer 102 is formed on the first surface of the N-type semiconductor substrate 101 of heavy doping.
In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region
Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, Semiconductor substrate 101
It is not more than 0.02 Ω cm heavily doped N-type substrate for resistivity.
Epitaxial layer 102 can use known depositing technology to be formed.For example, depositing technology can be steamed selected from electron beam
One kind in hair, chemical vapor deposition, ald, sputtering.In this embodiment, epitaxial layer 102 is not less than for resistivity
0.01 Ω cm p-type epitaxial layer, thickness are not less than 2 μm.
As shown in Figure 2 b, then, isolated area 103 is formed in epitaxial layer 102 by thermal diffusion method.
Isolated area 103 extends to Semiconductor substrate 101 from the surface of epitaxial layer 102, so as to limit plural number in epitaxial layer 102
Individual isolated island, in the present embodiment, the second isolated island surround the first isolated island.The concentration of isolated area 103 will influence rectifying device
Conducting resistance, those skilled in the art can control the concentration of isolated area 103, but the too low concentration of isolated area 103 according to device requirement
The current capacity of rectifying device is restricted by serious, therefore should be controlled not less than E19cm-3The order of magnitude.
As shown in Figure 2 c, then, the n-type doping area 104 of heavy doping is formed in the first isolated island and the second isolated island, and
Insulating barrier 105 is formed on epitaxial layer 102.
In this embodiment, doped region 104 is that the concentration that phosphorus diffusion is formed is not less than E19cm-3Heavy doping n-type doping
Area, it is extended in epitaxial layer 102 in each isolated island from the surface of epitaxial layer 102 respectively.
Insulating barrier 105 can use sputtering or thermal oxide to be formed.For example, insulating barrier 105 is the silica that thermal oxide is formed
Layer, in follow-up doping step, insulating barrier 105 is used as protective layer, and using as the interlayer insulating film 105 of resulting devices.
As shown in Figure 2 d, then, multiple openings, doped region 104, epitaxial layer are formed on insulating barrier 105 by photoetching process
102 is exposed outside via opening positioned at the part of the second isolated island and part isolated area 103, and wherein the epitaxial layer 102 is located at
The part of second isolated island and the part isolated area 103 are adjacent to each other.
As shown in Figure 2 e, first electrode 106 and second electrode 107 are formed, second electrode 107 is via on insulating barrier 105
Epitaxial layer 102 is located at opening into the part of the second isolated island and part isolated area 103 electrically connects, will be by doped region 104, extension
The lamination for the NPN structures that layer 102 is formed positioned at the part of the second isolated island and Semiconductor substrate 101 is changed into the folded of PN
Layer, first electrode 106 electrically connect each doped region 104 via the opening on insulating barrier 105, realize NPN structures and PN
Parallel connection.
As shown in figure 2f, then, by chip thinning and back face metalization, the shape on the second surface of Semiconductor substrate 101
Into the 3rd electrode 108, as earth terminal.
In this embodiment, it is used as the 3rd electrode 108 using gold.Those skilled in the art can select not according to packing forms
Same metal or metal alloy is as metal layer on back, such as gold, silver, copper, titanium silver, titanium nickel gold.
As can be seen that according to device of the present utility model, unidirectional low clamp voltage can be prepared with simple step
Transient Voltage Suppressor.By by parallel connection two longitudinal NPN structures in one by metal electrode short circuit into PN, make
It turns into the Transient Voltage Suppressor of unidirectional low clamp voltage, is advantageous to reduce chip size and reduces packaging cost.
It will be understood by those of skill in the art that the bottom of doped region 104 and Semiconductor substrate 101 first can be rationally designed
The doping concentration of spacing between spacing, doped region 104 and isolated area 103 and each doped region between surface, with control
The multiplication factor of NPN structures, obtain the Transient Voltage Suppressor of satisfactory low clamp voltage.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including the key element.
According to embodiment of the present utility model as described above, these embodiments do not have all details of detailed descriptionthe,
Also it is only described specific embodiment not limit the utility model.Obviously, as described above, many modification and change can be made
Change.This specification is chosen and specifically describes these embodiments, is to preferably explain that principle of the present utility model and reality should
With so that skilled artisan can repairing using the utility model and on the basis of the utility model well
Change use.The utility model is only limited by claims and its four corner and equivalent.
Claims (5)
- A kind of 1. Transient Voltage Suppressor, it is characterised in that including：The Semiconductor substrate of first doping type；The epitaxial layer of the second doping type on the Semiconductor substrate first surface, wherein the first doping type and second Doping type is different；The isolated area of first doping type, the Semiconductor substrate is extended to from the surface of the epitaxial layer through the epitaxial layer In, for limiting the first isolated island and the second isolated island in the epitaxial layer；The doped region of first doping type, respectively from the surface of the epitaxial layer in first isolated island and the second isolated island Extend in the epitaxial layer；First electrode, for each doped region to be electrically connected to each other；AndSecond electrode, the part for the isolated area and the epitaxial layer to be located to second isolated island are electrically connected to each other.
- 2. Transient Voltage Suppressor according to claim 1, it is characterised in that also include exhausted on the epitaxial layer Edge layer.
- 3. Transient Voltage Suppressor according to claim 1, it is characterised in that also including the 3rd electrode, the 3rd electricity Pole is located at the second surface of the Semiconductor substrate, and the first surface and the second surface are relative to each other.
- 4. Transient Voltage Suppressor according to claim 1, it is characterised in that second isolated island surrounds described first Isolated island.
- 5. Transient Voltage Suppressor according to claim 1, it is characterised in that first doping type is N-type or P Type, second doping type are another in N-type or p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720896650.8U CN207068844U (en) | 2017-07-21 | 2017-07-21 | Transient voltage suppressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720896650.8U CN207068844U (en) | 2017-07-21 | 2017-07-21 | Transient voltage suppressor |
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| Publication Number | Publication Date |
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| CN207068844U true CN207068844U (en) | 2018-03-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293533A (en) * | 2017-07-21 | 2017-10-24 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293533A (en) * | 2017-07-21 | 2017-10-24 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
| CN107293533B (en) * | 2017-07-21 | 2023-11-24 | 北京燕东微电子有限公司 | Transient voltage suppressor and method of manufacturing the same |
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