CN207834298U - Transient voltage suppressor - Google Patents
Transient voltage suppressor Download PDFInfo
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- CN207834298U CN207834298U CN201820255347.4U CN201820255347U CN207834298U CN 207834298 U CN207834298 U CN 207834298U CN 201820255347 U CN201820255347 U CN 201820255347U CN 207834298 U CN207834298 U CN 207834298U
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Abstract
The utility model discloses Transient Voltage Suppressor, Transient Voltage Suppressor includes：Semiconductor substrate；Epitaxial layer is set on the first surface of semiconductor substrate；First buried layer and the second buried layer, the first part of the first buried layer form the first transient voltage with the second buried layer and inhibit to manage, and second part and the semiconductor substrate of the first buried layer form the second transient voltage and inhibit to manage, and the first part of the first buried layer and second part do not interconnect；Multiple isolated areas are extended to from epi-layer surface in the first buried layer or the second buried layer respectively；Multiple well regions, extend to from epi-layer surface in epitaxial layer, wherein the first part of the first buried layer forms PN junction with semiconductor substrate, and the first part of the first buried layer is electrically connected with semiconductor substrate so that PN junction is short-circuited.Transient Voltage Suppressor provided by the utility model has the function of bidirectional transient voltage inhibition, capacitance is low, it is small, be made simple, and extraction electrode can be distinguished from tow sides.
Description
Technical field
The utility model is related to semiconductor microelectronic technology fields, more particularly, to a kind of Transient Voltage Suppressor.
Background technology
Transient Voltage Suppressor (Transient Voltage Suppressor, TVS) is one kind of universal practicality at present
High-effect circuit brake, shape are no different with general-purpose diode, but its special structure and technological design can inhale
Receive up to thousands of watts of surge power.The working mechanism of Transient Voltage Suppressor is：Under the conditions of applied in reverse, work as transient voltage
When suppressor bears the big pulse of a high-energy, working impedance can quickly be down to extremely low conduction value, to allow big electricity
Stream flows through, while voltage clamp in predeterminated level, and the general response time is only 10-12Second, therefore electricity can be effectively protected
The damage of precision components in sub-line road from various surge pulses.
Relative to the unidirectional Transient Voltage Suppressor for being only capable of in a single direction protecting circuit, two-way transient state electricity
Pressure suppressor meets the feature for the classical electrical I-V curve for meeting almost symmetry in positive and negative both direction, to actually answer
In, the both direction of circuit can be protected simultaneously, so application range is wider.
The market of consumer electronics develops rapidly, and is constantly carried as the electronic product performance of representative using mobile phone and mobile terminal
It rises, mobile phone or mobile terminal etc. all have higher requirements to reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is transient state electricity
The rigid index that pressure suppressor must meet.
Bidirectional transient voltage suppressor in the prior art is generally made of longitudinal NPN or positive-negative-positive structure.Fig. 1 a show existing
There are the structural schematic diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in technology, Fig. 1 b to show have in the prior art
There is the structural schematic diagram of the bidirectional transient voltage suppressor of longitudinal NPN structures.Transient voltage as illustrated in figs. 1A and ib inhibits
Although device can realize larger power and preferable voltage symmetry, and of low cost, simple for process, pair of this structure
Capacitance to Transient Voltage Suppressor is larger, cannot meet the needs of existing market is to Transient Voltage Suppressor.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series of utilization encapsulation of the prior art
Principle schematic.It, can be by two groups of separation, the duplicate unidirectional transient state of performance to realize bidirectional transient voltage suppressor
Voltage suppressor is connected according to mode shown in Fig. 2 a to realize the smaller bidirectional transient voltage suppressor of capacitance.However it is this double
Must have two groups of unidirectional Transient Voltage Suppressor Series Packages to Transient Voltage Suppressor, cost is higher, and for smaller
Packaging body, two groups of unidirectional Transient Voltage Suppressors can not encapsulate simultaneously, increase the difficulty in terms of manufacturing process.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor in two channel of the prior art.Such as
It, can be straight since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor in two channels are full symmetric shown in Fig. 2 b
It connects and draws two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor in two channels to realize the transient state electricity of bidirectional low-capacitance
Constrain system.However, under this application, since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor in two channels are necessary
It is drawn simultaneously from front, therefore chip area will increase, is not suitable for smaller packaging body；Simultaneously as in encapsulation process, two
Two tunnel ends of the unidirectional Transient Voltage Suppressor in channel each must make a call to a wires to draw two tunnel ends, this also can
Increase manufacturing cost.
Fig. 2 c show that a kind of of the prior art inhibits two poles using more independent rectifier diodes and common transient voltage
The principle schematic of the integrated bidirectional transient voltage suppressor of pipe encapsulation.As shown in Figure 2 c, since the bidirectional transient voltage inhibits
It needs to place 2 chips on Ji Dao in device, therefore is easy to cause the probability that encapsulation defect occurs and increases, to make chip patch
Cost it is higher；In encapsulation process, two tunnel ends need it is each make a call to a wires, but also cost increase；Simultaneously as
The integration packaging of multiple chips needs larger space, therefore the size of entire bidirectional transient voltage suppressor is larger, is not suitable for
Smaller packaging body.
Therefore, it is necessary to a kind of new, combining low capacitor design and the double of extraction electrode can be distinguished from tow sides
To Transient Voltage Suppressor.
Utility model content
In order to solve the above-mentioned problems of the prior art, the utility model provides a kind of Transient Voltage Suppressor, with full
Sufficient high-performance, low cost, low capacitance, bidirectional transient voltage inhibit, small size encapsulates and have and can distinguish from tow sides
The market demands such as the structure of extraction electrode.
The utility model provides a kind of Transient Voltage Suppressor, wherein including：The semiconductor of first doping type serves as a contrast
Bottom；The epitaxial layer of first doping type is set on the first surface of the semiconductor substrate；The first of second doping type
Second buried layer of buried layer and the first doping type, second doping type is with first doping type on the contrary, described first
Buried layer extends from the first surface of the semiconductor substrate into the semiconductor substrate, the first part of first buried layer with
Second buried layer forms the first transient voltage and inhibits pipe, and second part and the semiconductor substrate of first buried layer are formed
Second transient voltage inhibits pipe, and the first part of first buried layer and second part do not interconnect；Multiple isolated areas, respectively from institute
Epi-layer surface is stated to extend in first buried layer or second buried layer；Multiple well regions extend from the epi-layer surface
In to the epitaxial layer, wherein the first part of first buried layer forms PN junction, and described first with the semiconductor substrate
The first part of buried layer is electrically connected with the semiconductor substrate so that the PN junction is short-circuited, and first transient voltage inhibits pipe
Pipe is inhibited to be separately connected between the first electrode and the second electrode with second transient voltage, second transient voltage inhibits
The cathode of pipe inhibits the anode of pipe to be electrically connected through the semiconductor substrate and first transient voltage.
Preferably, the semiconductor substrate, first buried layer and second buried layer, the epitaxial layer, the multiple
Isolated area and the multiple well region form bidirectional transient voltage suppression circuit, and the bidirectional transient voltage suppression circuit includes：The
One rectifying tube and the second rectifying tube inhibit pipe and second transient voltage to inhibit pipe reversed with first transient voltage respectively
It is connected between the first electrode and the second electrode；First transient voltage inhibits pipe and second transient voltage
Inhibit pipe, second transient voltage that the cathode of pipe is inhibited to inhibit the anode of pipe to be electrically connected to draw with first transient voltage
For the second electrode, the cathode of the anode of first rectifying tube and second rectifying tube is electrically connected and leads to described the
One electrode, the PN junction are connected between the second electrode and the anode of first transient voltage inhibition pipe.
Preferably, the multiple isolated area includes：First isolated area of the second doping type, including first part and second
Part, the first part of first isolated area are connected with the first part of first buried layer to be limited in the epitaxial layer
Go out the first isolated island, the second part of first isolated area is connected with the second part of first buried layer in the extension
The second isolated island is limited in layer；Second isolated area of the first doping type, second isolated area and the second buried layer phase
Even to limit the third isolated island of the epitaxial layer in first isolated island.
Preferably, the multiple well region includes：First well region of the second doping type, be located at the third isolated island in
First rectifying tube is formed with the third isolated island；Second well region of the first doping type, the first of second well region
Part is located in second isolated island and as the cathode of second rectifying tube, the first part and institute of second well region
The first well region is stated to be electrically connected and draw as the first electrode.
Preferably, the second surface of the semiconductor substrate be equipped with metal layer using by the semiconductor substrate as described the
Two electrodes are drawn, and the first surface and second surface of the semiconductor substrate are opposite.
Preferably, second well region further includes second part, and the second part of second well region is from the epitaxial layer
Upper surface extend in the epitaxial layer, and be electrically connected with the first part of first isolated area.
Preferably, the second part of second well region and the first part of first isolated area are described outer by being located at
Prolong the electrode terminal electrical connection of the upper surface of layer.
Preferably, the Transient Voltage Suppressor further includes conductive communication means, and the communication means are through the extension
The upper surface of layer extends in the semiconductor substrate and is contacted with the first part of first isolated area.
After the technical solution of the utility model, following advantageous effect can get：By the cathode and sun of extra PN junction
Extremely it is connected so that extra PN junction is short-circuited should be able to promote Transient Voltage Suppressor；Can realize low capacitance performance and
The function of bidirectional transient voltage protection；First electrode and second electrode can be drawn respectively from tow sides；It is identical by selecting
Semiconductor substrate, sacrificial layer and the epitaxial layer of doping type, reduce the manufacture difficulty of epitaxial layer, to ensure that device is joined
The stabilization of number and performance；The collection of design and the making of core devices is mostly completed in the upper surface of epitaxial layer different from conventional single-chip
At scheme, the solid space of chip is largely utilized according to Transient Voltage Suppressor provided by the utility model, will account for
It is produced on chip interior according to the larger power device of area, only has the device of tightened up requirement to be placed on design rule some outer
Prolong a layer upper surface to complete the production, therefore chip area utilization rate higher, integrated level higher, chip size are further compressed,
Packaging cost is reduced, has industrialization advantage.
Description of the drawings
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from.
Fig. 1 a show the structural schematic diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in the prior art.
Fig. 1 b show the structural schematic diagram of the bidirectional transient voltage suppressor with longitudinal direction NPN structures in the prior art.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series of utilization encapsulation of the prior art
Principle schematic.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor in two channel of the prior art.
Fig. 2 c show that a kind of of the prior art is sealed using more independent rectifier diodes and common Transient Suppression Diode
The principle schematic of the integrated bidirectional transient voltage suppressor of dress.
Fig. 3 a show the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.
Fig. 3 b show the equivalent circuit of Transient Voltage Suppressor shown in Fig. 3 a.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3 a and Fig. 3 b.
Fig. 5 a show the part-structure schematic diagram of the Transient Voltage Suppressor of the utility model first embodiment.
Figure 5b shows that the part-structure schematic diagrams of the Transient Voltage Suppressor of the utility model second embodiment.
Fig. 6 a to 6j show that a kind of section in manufacturing method each stage of the Transient Voltage Suppressor of the utility model shows
It is intended to.
Fig. 7 and Fig. 8 shows cutting for the part stage of another manufacturing method of the Transient Voltage Suppressor of the utility model
Face schematic diagram.
Specific implementation mode
The utility model is described below based on embodiment, but the utility model is not restricted to these implementations
Example.It is detailed to describe some specific detail sections below in the datail description of the utility model embodiment, to this field
The description of part can also understand the utility model completely without these details for technical staff.In order to avoid obscuring this practicality
Novel essence, well known method, process, flow do not describe in detail.
In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in attached drawing
Various pieces are not necessarily to scale.In addition, certain well known parts may be not shown in figure.Flow chart, frame in attached drawing
Figure illustrates the system of the embodiments of the present invention, possible System Framework, the function and operation of method, apparatus, attached drawing
Box and box sequence are used only to the process and step of better diagram embodiment, without should be in this, as to utility model
The limitation of itself.
Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar
Reference numeral indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown
Certain well known parts.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
The form of presentation of face " or " A is on B and abuts therewith ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand,
The utility model can not be realized according to these specific details.
Fig. 3 a show that the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides, Fig. 3 b show Fig. 3 a
Shown in Transient Voltage Suppressor equivalent circuit.
The Transient Voltage Suppressor 100 that the utility model first embodiment provides is two-way TVS device, internal to have such as
Bidirectional transient voltage suppression circuit shown in Fig. 3, the bidirectional transient voltage suppression circuit include multiple diodes：First rectifying tube
D1, the second rectifying tube D2, diode D3, the first transient voltage inhibit pipe T1 and the second transient voltage to inhibit pipe T2.Wherein,
The anode of one rectifying tube D1 be connected with the cathode of the second rectifying tube D2 using as first electrode P1 (such as positioned at transient voltage inhibit
The encapsulation front of device 100), the second transient voltage inhibit the cathode of pipe T2 to be connected with the anode of the first transient voltage inhibition pipe T1 with
As second electrode P2 (such as positioned at encapsulation back side of Transient Voltage Suppressor 100), the second transient voltage inhibits the sun of pipe T2
Pole is connected with the anode of the second rectifying tube D2, and the anode of diode D3 inhibits the anode of pipe T1 to be connected with the first transient voltage, and two
The cathode of pole pipe D3 is connected with second electrode P2, and the first transient voltage inhibits the cathode phase of the cathode and the first rectifying tube D1 of pipe T1
Even.
Wherein, the anode and cathode of diode D3 (being formed by PN junction) is connected with each other, i.e. diode D3 is short-circuited, therefore is schemed
Bidirectional transient voltage suppression circuit 100 shown in 3a can be equivalent to equivalent circuit shown in Fig. 3 b.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3 a and Fig. 3 b.Wherein, abscissa indicates
Voltage between the first electrode and second electrode of Transient Voltage Suppressor, longitudinal axis expression inhibit from first electrode through transient voltage
Device 100 flows to the electric current of second electrode.
From fig. 4, it can be seen that when reversed between the first electrode P1 and second electrode P2 of the Transient Voltage Suppressor 100
When voltage is more than certain threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of second electrode is by pincers
Position is to predeterminated level；When the forward voltage between the first electrode P1 and second electrode P2 of Transient Voltage Suppressor 100 is more than one
When determining threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of first electrode is clamped to predetermined water
It is flat.
Specifically, in conjunction with Fig. 3 it is found that when surge occurs：If bearing to bear between first electrode P1 and second electrode P2
Voltage, then the second rectifying tube D2 conductings, the second transient voltage inhibits pipe T2 to bear backward voltage, if the numerical value of the backward voltage
Higher than the breakdown voltage that the second transient voltage inhibits pipe T2, then the second transient voltage inhibits the working impedance of pipe T2 that can drop immediately
The value very low to one is to allow high current to pass through, and at the same time by the voltage clamp of second electrode P2 to predeterminated level, to
Protection is connected to the electronic component between first electrode P1 and second electrode P2；If between first electrode P1 and second electrode P2
Positive voltage is born, then the first rectifying tube D1 conductings, the first transient voltage inhibits pipe T1 to bear backward voltage, if the backward voltage
Numerical value inhibit the breakdown voltage of pipe T1 higher than the first transient voltage, then the first transient voltage inhibits the working impedance of pipe T1 can
A very low value is dropped to immediately to allow high current to pass through, and at the same time by the voltage clamp of first electrode P1 to predeterminated level
It is connected to the electronic component between first electrode P1 and second electrode P2 with protection, is inhibited to realize two-way transient voltage
Function.
Fig. 5 a show the part-structure schematic diagram of the Transient Voltage Suppressor of the utility model first embodiment.
In the following description, it is specially one of p-type and N-type by the doping type for describing semi-conducting material.It is appreciated that
If inverting the doping type of each semi-conducting material, it is also possible to obtain the semiconductor devices of identical function.
As shown in Figure 5 a, Transient Voltage Suppressor 100 include first electrode P1, second electrode P2, semiconductor substrate 101,
Sacrificial layer (such as being realized by epitaxial growth technology, Fig. 5 a are not shown) on 101 first surface of semiconductor substrate, first are buried
The 103, second buried layer 104 of layer, the epitaxial layer 105 on sacrificial layer, the first isolated area 106, the second isolated area 107, the first trap
Area 108 and the second well region 109.
Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, in order to form p-type or n type semiconductor layer or area
Domain can mix the dopant of respective type in semiconductor layer or region.For example, P-type dopant includes boron, N type dopant
Including phosphorus or arsenic or antimony.
In this embodiment, semiconductor substrate 101 is the heavily doped N-type substrate that resistivity is less than 0.02 Ω cm, doping
Agent is arsenic (As).Second electrode P2 is for example positioned at the second surface of semiconductor substrate 101, the first surface of semiconductor substrate 101
It is relative to each other with second surface.
Sacrificial layer is the lightly doped n type epitaxial layer for being grown in 101 first surface of semiconductor substrate, and resistivity is not less than
0.1 Ω cm, and thickness is not less than 3 μm, for the sacrificial layer as 101 first surface of semiconductor substrate, the sacrificial layer is final
It by 101 back-diffusion of semiconductor substrate and will compensate totally, therefore in part description below, be omitted and sacrificial layer is retouched
It states.
First buried layer 103 is, for example, p type buried layer.By sacrificial layer to the first surface injectant from semiconductor substrate 101
Amount is not less than E14cm-2The dopant (being, for example, boron) of the order of magnitude, and anneal, to form the first buried layer 103.First buried layer 103 wraps
Include first part and second part.
Second buried layer 104 is, for example, that doping concentration is not less than E19cm-3The N-type heavily doped region of the order of magnitude.Second buried layer 104
It is formed in the first part of the first buried layer 103 and inhibits to manage to form the first transient voltage with the first part of the first buried layer 103
T1 (as best shown in figures 3 a and 3b).
Epitaxial layer 105 e.g. covers the N-type above the first surface for the semiconductor substrate 101 for being grown in N-type heavy doping
Lightly doped district, the second buried layer 104 of covering, the first buried layer 103 and sacrificial layer, and resistivity are not less than 5 Ω cm, thickness
Less than 5 μm.Wherein, the resistivity of epitaxial layer 105 and thickness will determine the electric property of the Transient Voltage Suppressor 100, in reality
When border is implemented, those skilled in the art can freely adjust according to the needs of application.
First isolated area 106 is, for example, p-type isolated area, and doping concentration is not less than E18cm-3, dopant is, for example, boron.The
One isolated area 106 is extended to from the upper surface of epitaxial layer 105 in epitaxial layer 105, and with subsequent high temperature process further to
Direction where semiconductor substrate 101 extends, and finally passes through epitaxial layer 105 to be buried with first in Transient Voltage Suppressor 100
Layer 103 is connected.First isolated area 106 includes first part and second part, and the first part of the first isolated area 106 buries with first
The first part of layer 103 is connected to limit the first isolated island in epitaxial layer 105；The second part of first isolated area 106 with
The second part of first buried layer 103 is connected to limit the second isolated island in epitaxial layer 105, wherein the first isolated island and second
Isolated island is not connected to mutually.
Second isolated area 107 is, for example, N-type isolated area, is not less than E18cm for doping concentration-3The N-type of the order of magnitude is heavily doped
Miscellaneous area, dopant are, for example, phosphorus.Second isolated area 107 is buried towards extension in the first isolated island and from the upper table of epitaxial layer with second
Layer 104 is connected, to further limit out the third isolated island of epitaxial layer in the first isolated island.Wherein, in order to form third
Isolated island, the second isolated area 107 and the medial surface of the first part of the first isolated area are least partially overlapped, i.e. the second isolated area
107 contact surface between the first part and the first isolated island of the first isolated area extends to second from the upper surface of epitaxial layer and buries
Layer is to form third isolated island.
First well region 108 is, for example, P type trap zone, is not less than E18cm for doping concentration-3The p-type heavily doped region of the order of magnitude,
Dopant is, for example, boron.First well region 108 is extended to by epitaxial layer 105 in third isolated island.
Second well region 109 is, for example, N-type well region, is not less than E14cm for implantation dosage-2N-type heavily doped region, dopant
For example, phosphorus.The first part of second well region 109 is extended to by 105 surface of epitaxial layer in the second isolated island.
In the present embodiment, as shown in Figure 5 a, the second well region 109 further includes second part, second of the second well region 109
Divide and is extended in epitaxial layer 105 and with the first part of the first isolated area 106 in the upper of epitaxial layer 105 by 105 surface of epitaxial layer
Surface electrical connection (such as the electrode terminal short circuit for passing through the upper surface of epitaxial layer).Due to the second well region 109 second part with
Epitaxial layer 105, semiconductor substrate 101 are all N-doped zones, thus the second part of the second well region 109, epitaxial layer 105 and
Semiconductor substrate 101 is connected to and is electrically connected with the first part of the first isolated area 106, thus by first of the first buried layer 103
Divide and the PN junction (i.e. diode D3 shown in Fig. 3 a and 3b) of the formation of semiconductor substrate 101 is short-circuited.
Preferably, there are at least one between the second part of the second well region 109 and the first part of the first isolated area 106
Contact area.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, insulating layer cover the upper surface of epitaxial layer 105 and
The corresponding position of the first part of first well region 108 and the first part of the second well region 109 is equipped with contact hole, is set in contact hole
It is equipped with electrode terminal so that first electrode P1 can utilize the electrode terminal in contact conductor and contact hole by the first well region 108
It is electrically connected and draws with the second well region 109.Insulating layer also is provided with contacting in the corresponding position of the second part of the second well region 109
Hole is also equipped with electrode terminal in contact hole so that first of the second part of the second well region 109 and the first isolated area 106
Dividing directly to be electrically connected by the electrode terminal in contact hole in the upper surface of epitaxial layer.
Insulation layers are such as made of silicon oxide or silicon nitride, electrode terminal and contact conductor for example by be selected from gold, silver, copper,
The metal or alloy such as aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
Figure 5b shows that the part-structure schematic diagrams of the Transient Voltage Suppressor of the utility model second embodiment.
As shown in Figure 5 b, the structure of the Transient Voltage Suppressor of the utility model second embodiment and above-mentioned the utility model
The structure of the Transient Voltage Suppressor of first embodiment is almost the same, and something in common repeats no more, the difference is that：In this reality
In Transient Voltage Suppressor with novel second embodiment, the second well region 109 only include first part without including second part,
Also, the Transient Voltage Suppressor of the utility model second embodiment further includes the communication means 110 of at least one conduction, the company
Logical upper surface of the component 110 through epitaxial layer 105 extend in semiconductor substrate 101 and with the first part of the first isolated area 106
The first part of first isolated area 106 is electrically connected by contact, communication means 110 with semiconductor substrate 101, to be buried by first
The anode and cathode short circuit of the PN junction (i.e. diode D3) formed between the first part and semiconductor substrate 101 of layer 103.
In the particular embodiment, communication means 110 by epitaxial layer 105 to the contact hole between semiconductor substrate 101 with
And the conductor material being filled in contact hole is realized.
Corresponding to Fig. 3 a, in the Transient Voltage Suppressor 100 shown in Fig. 5 a and Fig. 5 b, semiconductor substrate 101 is used as two
The cathode of pole pipe D3 is connected with second electrode P2, the anode of the first part of the first buried layer 103 as diode D3, diode D3
Anode and cathode be electrically connected, the first part of the first buried layer 103 anode as the first transient voltage inhibition pipe T1 simultaneously, the
Two buried layers 104 inhibit the cathode of pipe T1 as the first transient voltage.The second part of first buried layer 103 is as the second transient voltage
The anode of pipe T2, semiconductor substrate 101 is inhibited to inhibit the cathode of pipe T2 as the second transient voltage simultaneously.
First well region 108 is extended in third isolated island by epitaxial layer 105 using the anode as the first rectifying tube D1, third
Isolated island is connected by the second isolated area 107 with the second buried layer 104 as the cathode of the first rectifying tube D1.
The second part of the second part of first isolated area 106 and the first buried layer 103 is collectively formed the second rectifying tube D2's
Anode, the first part of the second well region 109 are extended in the second isolated island by 105 surface of epitaxial layer using as the second rectifying tube D2
Cathode.
The first part of second well region 109 and the first well region 108 are electrically connected and are drawn by first electrode P1, to realize the
Connection between the anode of one rectifying tube D1 and the cathode of the second rectifying tube D2.
Fig. 6 a to 6j show a kind of section signal in manufacturing method each stage of the utility model Transient Voltage Suppressor
Figure.
As shown in Figure 6 a, the sacrificial layer of N-type is formed in the first surface of the semiconductor substrate of N-type 101.
In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region
Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, semiconductor substrate 101
It is less than the heavily doped N-type substrate of 0.02 Ω cm for resistivity, dopant is arsenic (As).
The thickness of sacrificial layer is not less than 3 μm, and resistivity is not less than 0.1 Ω cm, and final sacrificial layer will be by semiconductor substrate
101 back-diffusion simultaneously compensate totally.
Sacrificial layer may be used known depositing technology and be formed.For example, depositing technology can be selected from electron beam evaporation, change
Learn one kind in vapor deposition, atomic layer deposition, sputtering.
As shown in Figure 6 b, the first buried layer of p-type is formed in semiconductor substrate 101 through sacrificial layer.First buried layer at least wraps
Include first part 103a and second part 103b.
For example, being not less than E14cm to from the first surface implantation dosage of semiconductor substrate 101 by sacrificial layer-2The order of magnitude
Dopant (be, for example, boron), and anneal, to form the first buried layer in semiconductor substrate 101.In actual implementation, this field
Technical staff can freely adjust the doping concentration and junction depth of the first buried layer according to the needs of application.
As fig. 6 c, the second buried layer 104 of N-type is formed.Second buried layer is, for example, that doping concentration is not less than E19cm-3Number
The N-type heavily doped region of magnitude.Second buried layer 104 is formed in the first part 103a of the first buried layer with first with the first buried layer
Part 103a forms the first transient voltage and inhibits pipe T1 (as best shown in figures 3 a and 3b).
As shown in fig 6d, the epitaxial layer 105 for forming N-type, to cover sacrificial layer, the first buried layer and the second buried layer.Extension
Layer 105 is, for example, N-type lightly doped district, and resistivity is not less than 5 Ω cm, and thickness is not less than 5 μm.Wherein, the electricity of epitaxial layer 105
Resistance rate and thickness will determine the operating voltage and electric property of the Transient Voltage Suppressor 100, in actual implementation, this field skill
Art personnel can freely adjust according to the needs of application.
Epitaxial layer 105 may be used known depositing technology and be formed.For example, depositing technology can be steamed selected from electron beam
One kind in hair, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in fig 6e, the first isolated area for forming p-type extends to epitaxial layer 105 from the upper surface of epitaxial layer 105
In, and as subsequent high temperature process further extends to the direction where semiconductor substrate 101, eventually pass through epitaxial layer 105
To be connected with the first buried layer.
The doping concentration of first isolated area is for example not less than E18cm-3The order of magnitude, dopant are, for example, boron.
First isolated area includes first part 106a and second part 106b, wherein the first part of the first isolated area
106a is connected with the first part 103a of the first buried layer to limit the first isolated island 105a, the first isolation in epitaxial layer 105
The second part 106b in area is connected with the second part 103b of the first buried layer to limit the second isolated island in epitaxial layer 105
105b, the first isolated island 105a and the second isolated island 105b are not connected to mutually.
As shown in Figure 6 f, the second isolated area 107 of N-type is formed.Second isolated area 107 is, for example, that doping concentration is not less than
E18cm-3The N-type heavily doped region of the order of magnitude, dopant are, for example, phosphorus.
Second isolated area 107 from the upper table of epitaxial layer 105 towards extend in the first isolated island 105a and with the second buried layer 104
It is connected, to further limit out the third isolated island 105c of epitaxial layer 105, the third isolated island in the second isolated island 105b
105c is electrically connected with the second buried layer 104.Wherein, in order to form third isolated island 105c, the second isolated area 107 and the first isolated area
First part 106a medial surface it is least partially overlapped, i.e. first part 106a of the second isolated area 107 along the first isolated area
Contact surface between the first isolated island 105a from the upper surface of epitaxial layer 105 extend to the second buried layer 104 with formed third every
Li Island 105c.
As shown in figure 6g, the first well region 108 of p-type is formed.First well region is, for example, that doping concentration is not less than E18cm-3Number
The p-type heavily doped region of magnitude, dopant are, for example, boron.
First well region 108 is extended to by the upper surface of epitaxial layer 105 in third isolated island 105c.
As shown in figure 6h, the second well region of N-type is formed.Second well region is, for example, that implantation dosage is not less than E14cm-2The order of magnitude
N-type heavily doped region, dopant is, for example, phosphorus.The first part 109a of second well region is extended to by the upper surface of epitaxial layer 105
In second isolated island 105b.
In the present embodiment, as shown in figure 6h, the second well region further includes second part 109b, the second part of the second well region
109b is extended in epitaxial layer 105 and with the first part 106a of the first isolated area by 105 surface of epitaxial layer in epitaxial layer 105
Upper surface short circuit (such as the electrode terminal short circuit for passing through the upper surface of epitaxial layer).Due to the second well region second part 109b with
Epitaxial layer 105, semiconductor substrate 101 are connected to and are electrically connected with the first part 106a of the first isolated area, to by the first buried layer
First part 103a and semiconductor substrate 101 formed PN junction (i.e. diode D3 shown in Fig. 3 a and 3b) be shorted.
Preferably, have at least one between the second part 109b of the second well region and the first part 106a of the first isolated area
A contact area.
As shown in Fig. 6 i, the first part 109a of the second well region and the first well region 108 are electrically connected to draw with contact conductor
Go out the first electrode P1 of Transient Voltage Suppressor 100.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, insulating layer cover the upper surface of epitaxial layer 105 and
The corresponding position of the first part 109a of first well region 108 and the second well region is equipped with contact hole, and electrode is provided in contact hole
Terminal so that first electrode P1 can utilize the electrode terminal in contact conductor and contact hole by the first part of the second well region
109a and the first well region 108 are electrically connected and lead to first electrode P1.Meanwhile insulating layer is in the second part 109b of the second well region
Corresponding position also be provided with contact hole, be also provided with electrode terminal in contact hole so that the second part 109b of the second well region with
The first part 106a of first isolated area can directly by the electrode terminal in contact hole epitaxial layer 105 upper surface electricity phase
Even.
Insulation layers are such as made of silicon oxide or silicon nitride, contact conductor and electrode terminal for example by be selected from gold, silver, copper,
The metal or alloy such as aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
As shown in Fig. 6 j, the second surface of semiconductor substrate 101 formed metal layer using by semiconductor substrate 101 as the
Two electrode P2 are drawn, and the first surface of semiconductor substrate 101 is opposite with the second surface of semiconductor substrate 101.
Preferably, before the second surface of semiconductor substrate 101 forms metal layer, first from the of semiconductor substrate 101
Two surfaces are to the thickness that semiconductor substrate 101 is thinned inside semiconductor substrate 101, to reduce the envelope of Transient Voltage Suppressor 100
Fill volume.
Fig. 7 and Fig. 8 shows cutting for the part stage of another manufacturing method of the Transient Voltage Suppressor of the utility model
Face schematic diagram.
This manufacturing method and above-mentioned manufacturing method are almost the same, and something in common repeats no more, below only to difference into
Row description.
As shown in Figure 7 and Figure 8, it is different from above-mentioned Fig. 6 h to 6j, in this manufacturing method, the second well region only includes first
Divide 109a without including second part.
As shown in fig. 7, this manufacturing method further includes：Form the communication means 110 of at least one conduction.The communication means
110 upper surfaces through epitaxial layer 105 extend in semiconductor substrate 101 and are contacted with the first part 106a of the first isolated area,
So that semiconductor substrate 101 is electrically connected by communication means 110 with the first part 106a of the first isolated area, thus will be by first
The anode and cathode short circuit of the PN junction (i.e. diode D3) formed between the first part 103a and semiconductor substrate 101 of buried layer.
In the particular embodiment, the step of forming conductive communication means 110 include：From the upper surface of epitaxial layer 105
Contact hole is made into semiconductor substrate 101 so that the first part of the first isolated area is at least partly exposed, then, is contacting
Conductive material is filled in hole to form communication means 110.Conductive material for example by be selected from gold, silver, copper, aluminium, aluminium silicon, aluminium copper silicon,
The metal or alloy such as titanium silver, titanium nickel gold form.
As shown in figure 8, in this manufacturing method, further with contact conductor by the of the second well region 109a and the first well region
A part of 108a is electrically connected to draw the first electrode P1 of Transient Voltage Suppressor 100, and in the second table of semiconductor substrate 101
Face forms metal layer to draw semiconductor substrate 101 as second electrode P2.The first surface of semiconductor substrate 101 with partly lead
The second surface of body substrate 101 is opposite.
As can be seen that can be prepared by easy steps according to the Transient Voltage Suppressor that the utility model embodiment provides
It obtains, can realize the function of the performance and bidirectional transient voltage protection of low capacitance, first can be drawn respectively from tow sides
Electrode and second electrode, and can be by the cathode of extra PN junction and anode short circuit to improve the property of Transient Voltage Suppressor
Energy.By semiconductor substrate, sacrificial layer and the epitaxial layer of the identical doping type of selection, the manufacture difficulty of epitaxial layer is reduced,
To ensure that the stabilization of device parameters and performance.And mostly core device is completed in the upper surface of epitaxial layer different from conventional single-chip
Core is largely utilized according to Transient Voltage Suppressor provided by the utility model in the Integrated Solution of design and the making of part
The larger power device of footprint area is produced on chip interior by the solid space of piece, is only had some to design rule tighter
The device that lattice require is placed on epitaxial layer upper surface and completes the production, chip area utilization rate higher, integrated level higher, and chip size obtains
To further compression, packaging cost is reduced, has industrialization advantage.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiments of the present invention, these embodiments there is no all details of detailed descriptionthe,
The specific embodiment that the utility model is only described is not limited yet.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With to enable skilled artisan to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (8)
1. a kind of Transient Voltage Suppressor, wherein including：
The semiconductor substrate of first doping type；
The epitaxial layer of first doping type is set on the first surface of the semiconductor substrate；
First buried layer of the second doping type and the second buried layer of the first doping type, second doping type and described first
Doping type is on the contrary, first buried layer extends from the first surface of the semiconductor substrate into the semiconductor substrate, institute
It states the first part of the first buried layer and second buried layer forms the first transient voltage and inhibits to manage, second of first buried layer
Divide and form the second transient voltage inhibition pipe with the semiconductor substrate, the first part of first buried layer and second part be not mutual
Even；
Multiple isolated areas are extended to from the epi-layer surface in first buried layer or second buried layer respectively；
Multiple well regions are extended to from the epi-layer surface in the epitaxial layer,
Wherein, the first part of first buried layer forms PN junction, and the first of first buried layer with the semiconductor substrate
Part is electrically connected with the semiconductor substrate so that the PN junction is short-circuited, and first transient voltage inhibits pipe and described second
Transient voltage inhibits pipe to be separately connected between the first electrode and the second electrode, and second transient voltage inhibits the cathode warp of pipe
The semiconductor substrate inhibits the anode of pipe to be electrically connected with first transient voltage.
2. Transient Voltage Suppressor according to claim 1, wherein
The semiconductor substrate, first buried layer and second buried layer, the epitaxial layer, the multiple isolated area and described
Multiple well regions form bidirectional transient voltage suppression circuit,
The bidirectional transient voltage suppression circuit includes：
First rectifying tube and the second rectifying tube inhibit pipe and second transient voltage to inhibit with first transient voltage respectively
Pipe differential concatenation is between the first electrode and the second electrode；
First transient voltage inhibits pipe and second transient voltage inhibits pipe, second transient voltage to inhibit the moon of pipe
Pole inhibits the anode of pipe to be electrically connected to lead to the second electrode, the sun of first rectifying tube with first transient voltage
The cathode of pole and second rectifying tube is electrically connected and leads to the first electrode,
The PN junction is connected between the second electrode and the anode of first transient voltage inhibition pipe.
3. Transient Voltage Suppressor according to claim 2, wherein the multiple isolated area includes：
First isolated area of the second doping type, including first part and second part, the first part of first isolated area
It is connected with the first part of first buried layer to limit the first isolated island in the epitaxial layer, first isolated area
Second part is connected with the second part of first buried layer to limit the second isolated island in the epitaxial layer；
Second isolated area of the first doping type, second isolated area are connected with second buried layer to be isolated described first
The third isolated island of the epitaxial layer is limited in island.
4. Transient Voltage Suppressor according to claim 3, wherein the multiple well region includes：
First well region of the second doping type, to form described first with the third isolated island in the third isolated island
Rectifying tube；
The first part of second well region of the first doping type, second well region is located in second isolated island and as institute
The cathode of the second rectifying tube is stated, the first part of second well region is electrically connected with first well region and as first electricity
It draws pole.
5. Transient Voltage Suppressor according to claim 1, wherein
The second surface of the semiconductor substrate be equipped with metal layer the semiconductor substrate to be drawn as the second electrode,
The first surface and second surface of the semiconductor substrate are opposite.
6. Transient Voltage Suppressor according to claim 4, wherein second well region further includes second part,
The second part of second well region is extended to from the upper surface of the epitaxial layer in the epitaxial layer, and with described first
The first part of isolated area is electrically connected.
7. Transient Voltage Suppressor according to claim 6, wherein the second part of second well region and described first
The first part of isolated area passes through the electrode terminal electrical connection positioned at the upper surface of the epitaxial layer.
8. Transient Voltage Suppressor according to claim 4, wherein the Transient Voltage Suppressor further includes the company of conduction
Logical component, upper surface of the communication means through the epitaxial layer extends in the semiconductor substrate and is isolated with described first
The first part in area contacts.
Priority Applications (1)
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|---|---|---|---|
| CN201820255347.4U CN207834298U (en) | 2018-02-12 | 2018-02-12 | Transient voltage suppressor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820255347.4U CN207834298U (en) | 2018-02-12 | 2018-02-12 | Transient voltage suppressor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108198811A (en) * | 2018-02-12 | 2018-06-22 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacturing method |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108198811A (en) * | 2018-02-12 | 2018-06-22 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacturing method |
| CN108198811B (en) * | 2018-02-12 | 2023-09-19 | 北京燕东微电子股份有限公司 | Transient voltage suppressor and method of manufacturing the same |
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