CN108198811A - Transient Voltage Suppressor and its manufacturing method - Google Patents
Transient Voltage Suppressor and its manufacturing method Download PDFInfo
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- CN108198811A CN108198811A CN201810146592.6A CN201810146592A CN108198811A CN 108198811 A CN108198811 A CN 108198811A CN 201810146592 A CN201810146592 A CN 201810146592A CN 108198811 A CN108198811 A CN 108198811A
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- transient voltage
- semiconductor substrate
- buried layer
- layer
- well region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The invention discloses Transient Voltage Suppressor and its manufacturing method, Transient Voltage Suppressor includes：Semiconductor substrate；Epitaxial layer is set on the first surface of Semiconductor substrate；First buried layer and the second buried layer, the first part of the first buried layer form the first transient voltage with the second buried layer and inhibit to manage, and second part and the Semiconductor substrate of the first buried layer form the second transient voltage and inhibit to manage, and the first part of the first buried layer and second part do not interconnect；Multiple isolated areas are extended to from epi-layer surface in the first buried layer or the second buried layer respectively；Multiple well regions, extend to from epi-layer surface in epitaxial layer, wherein, first part and the Semiconductor substrate of the first buried layer form PN junction, and the first part of the first buried layer is electrically connected with Semiconductor substrate so that PN junction is short-circuited.Transient Voltage Suppressor provided by the invention has the function of bidirectional transient voltage inhibition, capacitance is low, it is small, be made simple, and extraction electrode can be distinguished from tow sides.
Description
Technical field
The present invention relates to semiconductor microelectronic technology field, more particularly, to a kind of Transient Voltage Suppressor and its system
Make method.
Background technology
Transient Voltage Suppressor (Transient Voltage Suppressor, TVS) is one kind of universal practicality at present
High-effect circuit brake, shape are no different with general-purpose diode, but its special structure and technological design can inhale
Receive up to thousands of watts of surge power.The working mechanism of Transient Voltage Suppressor is：Under the conditions of applied in reverse, work as transient voltage
When suppressor bears the big pulse of high-energy, working impedance can quickly be down to extremely low conduction value, so as to allow big electricity
Stream flows through, while voltage clamp in predeterminated level, and the general response time is only 10-12Second, therefore can effectively protect electricity
Precision components in sub-line road are from the damage of various surge pulses.
Relative to the unidirectional Transient Voltage Suppressor for being only capable of in a single direction protecting circuit, two-way transient state electricity
Pressure suppressor meets the feature for the classical electrical I-V curve for meeting almost symmetry in positive and negative both direction, so as to actually should
In, the both direction of circuit can be protected simultaneously, so application range is wider.
The market rapid development of consumer electronics, the electronic product performance using mobile phone and mobile terminal as representative constantly carry
It rises, mobile phone or mobile terminal etc. all have higher requirements to reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is transient state electricity
The rigid index that pressure suppressor must meet.
Bidirectional transient voltage suppressor of the prior art is generally made of the NPN or positive-negative-positive structure of longitudinal direction.Fig. 1 a show existing
There is the structure diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in technology, Fig. 1 b show have in the prior art
There is the structure diagram of the bidirectional transient voltage suppressor of longitudinal NPN structures.Transient voltage as illustrated in figs. 1A and ib inhibits
Although device can realize larger power and preferable voltage symmetry, and of low cost, simple for process, pair of this structure
It is larger to the capacitance of Transient Voltage Suppressor, it is impossible to meet the needs of existing market is to Transient Voltage Suppressor.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series encapsulation of utilization of the prior art
Principle schematic.It, can be by two groups of separation, the duplicate unidirectional transient state of performance to realize bidirectional transient voltage suppressor
Voltage suppressor connects to realize the smaller bidirectional transient voltage suppressor of capacitance in the way of shown in Fig. 2 a.It is however this double
Must have two groups of unidirectional Transient Voltage Suppressor Series Packages to Transient Voltage Suppressor, cost is higher, and for smaller
Packaging body, two groups of unidirectional Transient Voltage Suppressors can not encapsulate simultaneously, increase the difficulty in terms of manufacturing process.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor of two channel of the prior art.Such as
It, can be straight since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor of two channels are full symmetric shown in Fig. 2 b
Connect the transient state electricity two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor of two channels drawn to realize bidirectional low-capacitance
Constrain system.However, under this application, since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor of two channels are necessary
It is drawn simultaneously from front, therefore chip area can increase, is not suitable for smaller packaging body；Simultaneously as in encapsulation process, two
Two tunnel ends of the unidirectional Transient Voltage Suppressor of channel each must make a call to a wires to draw two tunnel ends, this also can
Increase manufacture cost.
Fig. 2 c show that a kind of of the prior art inhibits two poles using more independent rectifier diodes and common transient voltage
The principle schematic of the integrated bidirectional transient voltage suppressor of pipe encapsulation.As shown in Figure 2 c, since the bidirectional transient voltage inhibits
It needs to place 2 chips on Ji Dao in device, therefore is easy to cause the probability increase that encapsulation defect occurs, so as to make chip patch
Cost it is higher；In encapsulation process, two tunnel ends need it is each make a call to a wires, but also cost increase；Simultaneously as
The integration packaging of multiple chips needs larger space, therefore the size of entire bidirectional transient voltage suppressor is larger, is not suitable for
Smaller packaging body.
Therefore, it is necessary to a kind of new, combining low capacitor design and the double of extraction electrode can be distinguished from tow sides
To Transient Voltage Suppressor.
Invention content
In order to solve the above-mentioned problems of the prior art, the present invention provides a kind of Transient Voltage Suppressor and its manufacturer
Method, to meet, high-performance, low cost, low capacitance, bidirectional transient voltage inhibit, small size encapsulates and with can be from positive and negative two
The market demands such as the structure of face difference extraction electrode.
According to an aspect of the present invention, a kind of Transient Voltage Suppressor is provided, wherein, including：First doping type
Semiconductor substrate；The epitaxial layer of first doping type is set on the first surface of the Semiconductor substrate；Second doping class
First buried layer of type and the second buried layer of the first doping type, second doping type and first doping type on the contrary,
First buried layer extends from the first surface of the Semiconductor substrate into the Semiconductor substrate, and the of first buried layer
It is a part of to form the first transient voltage inhibition pipe, second part and the semiconductor of first buried layer with second buried layer
Substrate forms the second transient voltage and inhibits pipe, and the first part of first buried layer and second part do not interconnect；Multiple isolated areas,
It is extended in first buried layer or second buried layer from the epi-layer surface respectively；Multiple well regions, from the epitaxial layer
Surface is extended in the epitaxial layer, wherein, first part and the Semiconductor substrate of first buried layer form PN junction, and
The first part of first buried layer is electrically connected with the Semiconductor substrate so that the PN junction is short-circuited, and first transient state is electric
Constrain tubulation and second transient voltage inhibits pipe to be connected between first electrode and second electrode, second transient state
Voltage inhibits the cathode of pipe the anode of pipe to be inhibited to be electrically connected through the Semiconductor substrate and first transient voltage.
Preferably, the Semiconductor substrate, first buried layer and second buried layer, the epitaxial layer, the multiple
Isolated area and the multiple well region form bidirectional transient voltage suppression circuit, and the bidirectional transient voltage suppression circuit includes：The
One rectifying tube and the second rectifying tube inhibit pipe and second transient voltage to inhibit pipe reversed with first transient voltage respectively
It is connected between the first electrode and the second electrode；First transient voltage inhibits pipe and second transient voltage
Inhibit pipe, second transient voltage inhibits the cathode of pipe and first transient voltage anode of pipe to be inhibited to be electrically connected to draw
For the second electrode, the cathode of the anode of first rectifying tube and second rectifying tube is electrically connected and leads to described the
One electrode, the PN junction are connected between the anode of the second electrode and first transient voltage inhibition pipe.
Preferably, the multiple isolated area includes：First isolated area of the second doping type, including first part and second
Part, the first part of first isolated area are connected to limit in the epitaxial layer with the first part of first buried layer
Go out the first isolated island, the second part of first isolated area is connected with the second part of first buried layer in the extension
The second isolated island is limited in layer；Second isolated area of the first doping type, second isolated area and the second buried layer phase
Connect the third isolated island to limit the epitaxial layer in first isolated island.
Preferably, the multiple well region includes：First well region of the second doping type, in the third isolated island with
First rectifying tube is formed with the third isolated island；Second well region of the first doping type, the first of second well region
Part is located in second isolated island and as the cathode of second rectifying tube, the first part and institute of second well region
The first well region is stated to be electrically connected and the first electrode is used as to draw.
Preferably, the second surface of the Semiconductor substrate be equipped with metal layer using by the Semiconductor substrate as described the
Two electrodes are drawn, and the first surface and second surface of the Semiconductor substrate are opposite.
Preferably, second well region further includes second part, and the second part of second well region is from the epitaxial layer
Upper surface extend in the epitaxial layer, and be electrically connected with the first part of first isolated area.
Preferably, the second part of second well region and the first part of first isolated area are described outer by being located at
Prolong the electrode terminal electrical connection of the upper surface of layer.
Preferably, the Transient Voltage Suppressor further includes conductive communication means, and the communication means are through the extension
The upper surface of layer extends in the Semiconductor substrate and is contacted with the first part of first isolated area.
According to another aspect of the present invention, a kind of manufacturing method of Transient Voltage Suppressor is additionally provided, wherein, including：
The Semiconductor substrate of first doping type is provided；It forms the first buried layer of the second doping type and the second of the first doping type is buried
Layer, second doping type and first doping type on the contrary, first buried layer from the first of the Semiconductor substrate
Surface extends into the Semiconductor substrate, and first part and the Semiconductor substrate of first buried layer form PN junction, institute
It states the first part of the first buried layer and second buried layer forms the first transient voltage and inhibits to manage, second of first buried layer
Divide and form the second transient voltage inhibition pipe with the Semiconductor substrate, the first part of first buried layer and second part be not mutual
Even；The epitaxial layer of the first doping type is formed on the first surface of the Semiconductor substrate of the first doping type；It is formed multiple
Isolated area, the multiple isolated area are extended to from the epi-layer surface in first buried layer or second buried layer respectively；
Multiple well regions are formed, the multiple well region is extended to from the epi-layer surface in the epitaxial layer；And described first is buried
The first part of layer is electrically connected with the Semiconductor substrate so that the PN junction is short-circuited, first transient voltage inhibit pipe with
Second transient voltage inhibits pipe to be connected between first electrode and second electrode, and second transient voltage inhibits pipe
Cathode the anode of pipe is inhibited to be electrically connected through the Semiconductor substrate and first transient voltage.
Preferably, the step of forming the multiple isolated area includes：The first isolated area of the second doping type is formed, it is described
First isolated area includes first part and second part, the first part of first isolated area and the first of first buried layer
Part is connected to limit the first isolated island in the epitaxial layer, and the second part of second isolated area is buried with described first
The second part of layer is connected to limit the second isolated island in the epitaxial layer；Form the second isolation of the first doping type
Area, second isolated area are connected with second buried layer with the third that the epitaxial layer is limited in first isolated island
Isolated island.
Preferably, the step of forming the multiple well region includes：The second doping type is formed in the third isolated island
The first well region；Form the second well region of the first doping type, the first part of second well region be formed in described second every
In Li Island, the first part of second well region is electrically connected with first well region and the first electrode is used as to draw.
Preferably, the manufacturing method further includes：Metal layer is formed with by institute in the second surface of the Semiconductor substrate
It states Semiconductor substrate to draw as the second electrode, the first surface and second surface of the Semiconductor substrate are opposite.
Preferably, the first part of first buried layer is electrically connected with the Semiconductor substrate so that the PN junction is short
The step of road, includes：Form the second part of second well region, the second part of second well region is from the epitaxial layer
Upper surface extends in the epitaxial layer and is electrically connected with the first part of first isolated area.
Preferably, the second part of second well region and the first part of first isolated area are described outer by being located at
Prolong the electrode terminal electrical connection of the upper surface of layer.
Preferably, the first part of first buried layer is electrically connected with the Semiconductor substrate so that the PN junction is short
The step of road, includes：Conductive communication means are formed, upper surface of the communication means through the epitaxial layer extends to described half
It is contacted in conductor substrate and with the first part of first isolated area.
Preferably, the step of forming conductive communication means includes：From the upper table of the epitaxial layer towards the semiconductor
Contact hole is made in substrate so that the first part of first isolated area is at least partly exposed；It fills in the contact hole
Conductive material is to form the communication means.
Preferably, the step of providing the Semiconductor substrate includes：In the pre- Mr. of the first surface of the Semiconductor substrate
The sacrificial layer of long first doping type, the doping concentration of the epitaxial layer are less than the doping concentration of the sacrificial layer.
After technical solution using the present invention, following advantageous effect can be obtained：By the cathode of extra PN junction and anode phase
Even so that extra PN junction is short-circuited should be able to promote Transient Voltage Suppressor；It can realize the performance of low capacitance and two-way
The function of transient voltage protection；First electrode and second electrode can be drawn respectively from tow sides；By selecting identical doping
Semiconductor substrate, sacrificial layer and the epitaxial layer of type reduce the manufacture difficulty of epitaxial layer, so as to ensure that device parameters and
The stabilization of performance；The integrated side of design and the making of core devices is mostly completed in the upper surface of epitaxial layer different from conventional single-chip
The solid space of chip is largely utilized according to Transient Voltage Suppressor provided by the invention for case, by footprint area compared with
Big power device is produced on chip interior, some devices for having tightened up requirement to design rule only are placed on epitaxial layer upper table
Face completes the production, therefore chip area utilization rate higher, integrated level higher, chip size are further compressed, and reduce envelope
This is dressed up, has industrialization advantage.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 a show the structure diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in the prior art.
Fig. 1 b show the structure diagram of the bidirectional transient voltage suppressor with longitudinal direction NPN structures in the prior art.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series encapsulation of utilization of the prior art
Principle schematic.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor of two channel of the prior art.
Fig. 2 c show that a kind of of the prior art is sealed using more independent rectifier diodes and common Transient Suppression Diode
The principle schematic of the integrated bidirectional transient voltage suppressor of dress.
Fig. 3 a show the circuit diagram for the Transient Voltage Suppressor that first embodiment of the invention provides.
Fig. 3 b show the equivalent circuit of the Transient Voltage Suppressor shown in Fig. 3 a.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3 a and Fig. 3 b.
Fig. 5 a show the part-structure schematic diagram of the Transient Voltage Suppressor of first embodiment of the invention.
Figure 5b shows that the part-structure schematic diagrams of the Transient Voltage Suppressor of second embodiment of the invention.
Fig. 6 a to 6j show the section in the manufacturing method of the Transient Voltage Suppressor of third embodiment of the invention each stage
Schematic diagram.
Fig. 7 and Fig. 8 shows cutting for the part stage of the manufacturing method of the Transient Voltage Suppressor of fourth embodiment of the invention
Face schematic diagram.
Specific embodiment
Below based on embodiment, present invention is described, but the present invention is not restricted to these embodiments.Under
Text is detailed to describe some specific detail sections in the datail description of the embodiment of the present invention, and those skilled in the art are come
The present invention can also be understood completely by saying the description of part without these details.It is well known in order to avoid obscuring the essence of the present invention
Method, process, flow do not describe in detail.
In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in attached drawing
Various pieces are not necessarily to scale.In addition, certain well known parts may be not shown in figure.Flow chart, frame in attached drawing
Figure illustrates possible System Framework, function and the operation of the system of the embodiment of the present invention, method, apparatus, the box of attached drawing
And box sequence is used only to the process and step of better diagram embodiment, without should be in this, as the limit to invention itself
System.
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown certain
Well known part.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, it is known as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
It if, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted directly against rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the present invention, such as the structure of device, material, size, processing work is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Fig. 3 a show the circuit diagram for the Transient Voltage Suppressor that first embodiment of the invention provides, and Fig. 3 b are shown shown in Fig. 3 a
Transient Voltage Suppressor equivalent circuit.
The Transient Voltage Suppressor 100 that first embodiment of the invention provides is two-way TVS device, internal to have such as Fig. 3
Shown bidirectional transient voltage suppression circuit, the bidirectional transient voltage suppression circuit include multiple diodes：First rectifying tube D1,
Second rectifying tube D2, diode D3, the first transient voltage inhibit pipe T1 and the second transient voltage to inhibit pipe T2.Wherein, first
The anode of rectifying tube D1 be connected with the cathode of the second rectifying tube D2 using as first electrode P1 (such as positioned at Transient Voltage Suppressor
100 encapsulation front), the second transient voltage inhibits the cathode of pipe T2 and the first transient voltage the anode of pipe T1 to be inhibited to be connected to make
For second electrode P2 (such as positioned at encapsulation back side of Transient Voltage Suppressor 100), the second transient voltage inhibits the anode of pipe T2
It is connected with the anode of the second rectifying tube D2, the anode of diode D3 inhibits the anode of pipe T1 to be connected with the first transient voltage, two poles
The cathode of pipe D3 is connected with second electrode P2, and the first transient voltage inhibits the cathode phase of the cathode and the first rectifying tube D1 of pipe T1
Even.
Wherein, the anode of diode D3 (being formed by PN junction) and cathode are connected with each other, i.e. diode D3 is short-circuited, therefore are schemed
Bidirectional transient voltage suppression circuit 100 shown in 3a can be equivalent to the equivalent circuit shown in Fig. 3 b.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3 a and Fig. 3 b.Wherein, abscissa represents
Voltage between the first electrode and second electrode of Transient Voltage Suppressor, longitudinal axis expression inhibit from first electrode through transient voltage
Device 100 flows to the electric current of second electrode.
From fig. 4, it can be seen that when reversed between the first electrode P1 of the Transient Voltage Suppressor 100 and second electrode P2
When voltage is more than certain threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of second electrode is by pincers
Position is to predeterminated level；When the forward voltage between the first electrode P1 of Transient Voltage Suppressor 100 and second electrode P2 is more than one
When determining threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of first electrode is clamped to predetermined water
It is flat.
Specifically, with reference to Fig. 3 it is found that when surge occurs：If it bears to bear between first electrode P1 and second electrode P2
Voltage, then the second rectifying tube D2 conductings, the second transient voltage inhibits pipe T2 to bear backward voltage, if the numerical value of the backward voltage
Higher than the breakdown voltage that the second transient voltage inhibits pipe T2, then the second transient voltage inhibits the working impedance of pipe T2 that can drop immediately
The value very low to one is to allow high current to pass through, and at the same time by the voltage clamp of second electrode P2 to predeterminated level, so as to
Protection is connected to the electronic component between first electrode P1 and second electrode P2；If between first electrode P1 and second electrode P2
Positive voltage is born, then the first rectifying tube D1 is connected, and the first transient voltage inhibits pipe T1 to bear backward voltage, if the backward voltage
Numerical value inhibit the breakdown voltage of pipe T1 higher than the first transient voltage, then the first transient voltage inhibits the working impedance of pipe T1 can
A very low value is dropped to immediately so that high current to be allowed to pass through, and at the same time by the voltage clamp of first electrode P1 to predeterminated level
Electronic component between first electrode P1 and second electrode P2 is connected to protection, it is achieved thereby that two-way transient voltage inhibits
Function.
Fig. 5 a show the part-structure schematic diagram of the Transient Voltage Suppressor of first embodiment of the invention.
In the following description, it is specially one of p-type and N-type by the doping type for describing semi-conducting material.It is appreciated that
If invert the doping type of each semi-conducting material, it is also possible to obtain the semiconductor devices of identical function.
As shown in Figure 5 a, Transient Voltage Suppressor 100 include first electrode P1, second electrode P2, Semiconductor substrate 101,
Sacrificial layer (such as being realized by epitaxial growth technology, Fig. 5 a are not shown) on 101 first surface of Semiconductor substrate, first are buried
The 103, second buried layer 104 of layer, the epitaxial layer 105 on sacrificial layer, the first isolated area 106, the second isolated area 107, the first trap
108 and second well region 109 of area.
Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, in order to form p-type or n type semiconductor layer or area
Domain can mix the dopant of respective type in semiconductor layer or region.For example, P-type dopant includes boron, N type dopant
Including phosphorus or arsenic or antimony.
In this embodiment, Semiconductor substrate 101 is less than the heavily doped N-type substrate of 0.02 Ω cm, doping for resistivity
Agent is arsenic (As).Second electrode P2 is for example positioned at the second surface of Semiconductor substrate 101, the first surface of Semiconductor substrate 101
It is relative to each other with second surface.
Sacrificial layer is the lightly doped n type epitaxial layer for being grown in 101 first surface of Semiconductor substrate, and resistivity is not less than
0.1 Ω cm, and thickness, not less than 3 μm, for the sacrificial layer as 101 first surface of Semiconductor substrate, the sacrificial layer is final
It by 101 back-diffusion of Semiconductor substrate and will compensate totally, therefore in part description below, be omitted and sacrificial layer is retouched
It states.
First buried layer 103 is, for example, p type buried layer.By sacrificial layer to the first surface injectant from Semiconductor substrate 101
Amount is not less than E14cm-2The dopant (being, for example, boron) of the order of magnitude, and anneal, to form the first buried layer 103.First buried layer 103 wraps
Include first part and second part.
Second buried layer 104 is, for example, that doping concentration is not less than E19cm-3The N-type heavily doped region of the order of magnitude.Second buried layer 104
It is formed in the first part of the first buried layer 103 and inhibits to manage to form the first transient voltage with the first part of the first buried layer 103
T1 (as best shown in figures 3 a and 3b).
Epitaxial layer 105 e.g. covers the N-type above the first surface of Semiconductor substrate 101 for being grown in N-type heavy doping
Lightly doped district, the second buried layer 104 of covering, the first buried layer 103 and sacrificial layer, and resistivity are not less than 5 Ω cm, thickness not
Less than 5 μm.Wherein, the electric property that the resistivity of epitaxial layer 105 and thickness will determine the Transient Voltage Suppressor 100, in reality
When border is implemented, those skilled in the art can freely adjust according to the needs of application.
First isolated area 106 is, for example, p-type isolated area, and doping concentration is not less than E18cm-3, dopant is, for example, boron.The
One isolated area 106 is extended to from the upper surface of epitaxial layer 105 in epitaxial layer 105, and with subsequent high temperature process further to
Direction extension where Semiconductor substrate 101, finally passes through epitaxial layer 105 to be buried with first in Transient Voltage Suppressor 100
Layer 103 is connected.First isolated area 106 includes first part and second part, and the first part of the first isolated area 106 buries with first
The first part of layer 103 is connected to limit the first isolated island in epitaxial layer 105；The second part of first isolated area 106 with
The second part of first buried layer 103 is connected to limit the second isolated island in epitaxial layer 105, wherein the first isolated island and second
Isolated island does not connect mutually.
Second isolated area 107 is, for example, N-type isolated area, is not less than E18cm for doping concentration-3The N-type of the order of magnitude is heavily doped
Miscellaneous area, dopant are, for example, phosphorus.Second isolated area 107 from the upper table of epitaxial layer towards the first isolated island in extend and buried with second
Layer 104 is connected, so as to further limit the third isolated island of epitaxial layer in the first isolated island.Wherein, in order to form third
Isolated island, the second isolated area 107 and the medial surface of the first part of the first isolated area are least partially overlapped, i.e. the second isolated area
107 extend to second along the contact surface between the first part of the first isolated area and the first isolated island from the upper surface of epitaxial layer buries
Layer is to form third isolated island.
First well region 108 is, for example, P type trap zone, is not less than E18cm for doping concentration-3The p-type heavily doped region of the order of magnitude,
Dopant is, for example, boron.First well region 108 is extended to by epitaxial layer 105 in third isolated island.
Second well region 109 is, for example, N-type well region, is not less than E14cm for implantation dosage-2N-type heavily doped region, dopant
For example, phosphorus.The first part of second well region 109 is extended to by 105 surface of epitaxial layer in the second isolated island.
In the present embodiment, as shown in Figure 5 a, the second well region 109 further includes second part, second of the second well region 109
It point is extended in epitaxial layer 105 by 105 surface of epitaxial layer and with the first part of the first isolated area 106 in the upper of epitaxial layer 105
Surface is electrically connected (such as the electrode terminal short circuit for the upper surface for passing through epitaxial layer).Due to the second well region 109 second part with
Epitaxial layer 105, Semiconductor substrate 101 are all N-doped zones, thus the second part of the second well region 109, epitaxial layer 105 and
Semiconductor substrate 101 is connected and is electrically connected with the first part of the first isolated area 106, thus first by the first buried layer 103
Divide and the PN junction (the diode D3 i.e. shown in Fig. 3 a and 3b) of the formation of Semiconductor substrate 101 is short-circuited.
Preferably, there are at least one between the first part of the second part of the second well region 109 and the first isolated area 106
Contact area.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, the upper surface of insulating layer covering epitaxial layer 105 and
The corresponding position of the first part of first well region 108 and the first part of the second well region 109 is equipped with contact hole, is set in contact hole
It is equipped with electrode terminal so that first electrode P1 can utilize the electrode terminal in contact conductor and contact hole by the first well region 108
It is electrically connected and draws with the second well region 109.Insulating layer also is provided with contacting in the corresponding position of the second part of the second well region 109
Hole is also equipped with electrode terminal in contact hole so that first of the second part of the second well region 109 and the first isolated area 106
Divide directly to be electrically connected by the electrode terminal in contact hole in the upper surface of epitaxial layer.
Insulation layers are such as made of silica or silicon nitride, electrode terminal and contact conductor for example by be selected from gold, silver, copper,
The metal or alloy such as aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
Figure 5b shows that the part-structure schematic diagrams of the Transient Voltage Suppressor of second embodiment of the invention.
As shown in Figure 5 b, the structure of the Transient Voltage Suppressor of second embodiment of the invention is implemented with the invention described above first
The structure of the Transient Voltage Suppressor of example is basically identical, and something in common repeats no more, the difference lies in：It is real in the present invention second
In the Transient Voltage Suppressor for applying example, the second well region 109 only includes first part without including second part, also, the present invention
The Transient Voltage Suppressor of second embodiment further includes the communication means 110 of at least one conduction, and the communication means 110 are through extension
The upper surface of layer 105 extends in Semiconductor substrate 101 and is contacted with the first part of the first isolated area 106, communication means 110
The first part of first isolated area 106 is electrically connected with Semiconductor substrate 101, thus will be by the first part of the first buried layer 103
Anode and the cathode short circuit of the PN junction (i.e. diode D3) formed between Semiconductor substrate 101.
In the particular embodiment, communication means 110 by epitaxial layer 105 to the contact hole between Semiconductor substrate 101 with
And the conductor material being filled in contact hole is realized.
Corresponding to Fig. 3 a, in the Transient Voltage Suppressor 100 shown in Fig. 5 a and Fig. 5 b, Semiconductor substrate 101 is used as two
The cathode of pole pipe D3 is connected with second electrode P2, the anode of the first part of the first buried layer 103 as diode D3, diode D3
Anode and cathode be electrically connected, the first part of the first buried layer 103 anode as the first transient voltage inhibition pipe T1 simultaneously, the
Two buried layers 104 inhibit the cathode of pipe T1 as the first transient voltage.The second part of first buried layer 103 is as the second transient voltage
Inhibit the anode of pipe T2, Semiconductor substrate 101 inhibits the cathode of pipe T2 as the second transient voltage simultaneously.
First well region 108 is extended in third isolated island by epitaxial layer 105 using the anode as the first rectifying tube D1, third
Isolated island is connected as the cathode of the first rectifying tube D1 by the second isolated area 107 with the second buried layer 104.
The second part of the second part of first isolated area 106 and the first buried layer 103 is collectively formed the second rectifying tube D2's
Anode, the first part of the second well region 109 are extended in the second isolated island by 105 surface of epitaxial layer using as the second rectifying tube D2
Cathode.
The first part of second well region 109 and the first well region 108 are electrically connected and drawn by first electrode P1, so as to fulfill
Connection between the cathode of the anode of one rectifying tube D1 and the second rectifying tube D2.
Fig. 6 a to 6j show the section in the manufacturing method of the Transient Voltage Suppressor of third embodiment of the invention each stage
Schematic diagram.
As shown in Figure 6 a, the sacrificial layer of N-type is formed in the first surface of the Semiconductor substrate of N-type 101.
In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region
Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, Semiconductor substrate 101
It is less than the heavily doped N-type substrate of 0.02 Ω cm for resistivity, dopant is arsenic (As).
The thickness of sacrificial layer is not less than 3 μm, and resistivity is not less than 0.1 Ω cm, and final sacrificial layer will be by Semiconductor substrate
101 back-diffusion simultaneously compensate totally.
Sacrificial layer may be used known depositing technology and be formed.For example, depositing technology can be selected from electron beam evaporation, change
Learn one kind in vapor deposition, atomic layer deposition, sputtering.
As shown in Figure 6 b, the first buried layer of p-type is formed in Semiconductor substrate 101 through sacrificial layer.First buried layer at least wraps
Include first part 103a and second part 103b.
For example, E14cm is not less than to the first surface implantation dosage from Semiconductor substrate 101 by sacrificial layer-2The order of magnitude
Dopant (be, for example, boron), and anneal, to form the first buried layer in Semiconductor substrate 101.In actual implementation, this field
Technical staff can freely adjust the doping concentration and junction depth of the first buried layer according to the needs of application.
As fig. 6 c, the second buried layer 104 of N-type is formed.Second buried layer is, for example, that doping concentration is not less than E19cm-3Number
The N-type heavily doped region of magnitude.Second buried layer 104 is formed in the first part 103a of the first buried layer with first with the first buried layer
Part 103a forms the first transient voltage and inhibits pipe T1 (as best shown in figures 3 a and 3b).
As shown in fig 6d, the epitaxial layer 105 of N-type is formed, to cover sacrificial layer, the first buried layer and the second buried layer.Extension
Layer 105 is, for example, N-type lightly doped district, and resistivity is not less than 5 Ω cm, and thickness is not less than 5 μm.Wherein, the electricity of epitaxial layer 105
The operating voltage and electric property that resistance rate and thickness will determine the Transient Voltage Suppressor 100, in actual implementation, this field skill
Art personnel can freely adjust according to the needs of application.
Epitaxial layer 105 may be used known depositing technology and be formed.For example, depositing technology can be steamed selected from electron beam
One kind in hair, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in fig 6e, the first isolated area of p-type is formed, epitaxial layer 105 is extended to from the upper surface of epitaxial layer 105
In, and as subsequent high temperature process further extends to the direction where Semiconductor substrate 101, eventually pass through epitaxial layer 105
To be connected with the first buried layer.
The doping concentration of first isolated area is for example not less than E18cm-3The order of magnitude, dopant are, for example, boron.
First isolated area includes first part 106a and second part 106b, wherein, the first part of the first isolated area
106a is connected to limit the first isolated island 105a, the first isolation in epitaxial layer 105 with the first part 103a of the first buried layer
The second part 106b in area is connected to limit the second isolated island in epitaxial layer 105 with the second part 103b of the first buried layer
105b, the first isolated island 105a and the second isolated island 105b are not connected mutually.
As shown in Figure 6 f, the second isolated area 107 of N-type is formed.Second isolated area 107 is, for example, that doping concentration is not less than
E18cm-3The N-type heavily doped region of the order of magnitude, dopant are, for example, phosphorus.
Second isolated area 107 from the upper table of epitaxial layer 105 towards the first isolated island 105a in extension and with the second buried layer 104
It is connected, so as to further limit the third isolated island 105c of epitaxial layer 105, the third isolated island in the second isolated island 105b
105c is electrically connected with the second buried layer 104.Wherein, in order to form third isolated island 105c, the second isolated area 107 and the first isolated area
First part 106a medial surface it is least partially overlapped, i.e. first part 106a of the second isolated area 107 along the first isolated area
Contact surface between the first isolated island 105a from the upper surface of epitaxial layer 105 extend to the second buried layer 104 with formed third every
Li Island 105c.
As shown in figure 6g, the first well region 108 of p-type is formed.First well region is, for example, that doping concentration is not less than E18cm-3Number
The p-type heavily doped region of magnitude, dopant are, for example, boron.
First well region 108 is extended to by the upper surface of epitaxial layer 105 in third isolated island 105c.
As shown in figure 6h, the second well region of N-type is formed.Second well region is, for example, that implantation dosage is not less than E14cm-2The order of magnitude
N-type heavily doped region, dopant is, for example, phosphorus.The first part 109a of second well region is extended to by the upper surface of epitaxial layer 105
In second isolated island 105b.
In the present embodiment, as shown in figure 6h, the second well region further includes second part 109b, the second part of the second well region
109b is extended in epitaxial layer 105 by 105 surface of epitaxial layer and with the first part 106a of the first isolated area in epitaxial layer 105
Upper surface short circuit (such as the electrode terminal short circuit for the upper surface for passing through epitaxial layer).Due to the second well region second part 109b with
Epitaxial layer 105, Semiconductor substrate 101 are connected and are electrically connected with the first part 106a of the first isolated area, so as to by the first buried layer
First part 103a and Semiconductor substrate 101 formed PN junction (the diode D3 i.e. shown in Fig. 3 a and 3b) be shorted.
Preferably, have at least one between the second part 109b of the second well region and the first part 106a of the first isolated area
A contact area.
As shown in Fig. 6 i, the first part 109a of the second well region and the first well region 108 are electrically connected to draw with contact conductor
Go out the first electrode P1 of Transient Voltage Suppressor 100.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, the upper surface of insulating layer covering epitaxial layer 105 and
The corresponding position of the first part 109a of first well region 108 and the second well region is equipped with contact hole, and electrode is provided in contact hole
Terminal so that first electrode P1 can utilize the electrode terminal in contact conductor and contact hole by the first part of the second well region
109a and the first well region 108 are electrically connected and lead to first electrode P1.Meanwhile insulating layer is in the second part 109b of the second well region
Corresponding position also be provided with contact hole, be also provided with electrode terminal in contact hole so that the second part 109b of the second well region with
The first part 106a of first isolated area can directly by the electrode terminal in contact hole epitaxial layer 105 upper surface electricity phase
Even.
Insulation layers are such as made of silica or silicon nitride, contact conductor and electrode terminal for example by be selected from gold, silver, copper,
The metal or alloy such as aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
As shown in Fig. 6 j, the second surface of Semiconductor substrate 101 formed metal layer using by Semiconductor substrate 101 as the
Two electrode P2 are drawn, and the first surface of Semiconductor substrate 101 is opposite with the second surface of Semiconductor substrate 101.
Preferably, before the second surface of Semiconductor substrate 101 forms metal layer, first from the of Semiconductor substrate 101
The thickness of Semiconductor substrate 101 is thinned to the inside of Semiconductor substrate 101 for two surfaces, to reduce the envelope of Transient Voltage Suppressor 100
Fill volume.
Fig. 7 and Fig. 8 shows cutting for the part stage of the manufacturing method of the Transient Voltage Suppressor of fourth embodiment of the invention
Face schematic diagram.
The manufacturing method of the Transient Voltage Suppressor of fourth embodiment of the invention and the wink of the invention described above 3rd embodiment
The manufacturing method of state voltage suppressor is basically identical, and something in common repeats no more, and only difference is described below.
As shown in Figure 7 and Figure 8, different from above-mentioned Fig. 6 h to 6j, in the Transient Voltage Suppressor of fourth embodiment of the invention
Manufacturing method in, the second well region only include first part 109a without including second part.
As shown in fig. 7, the manufacturing method of the Transient Voltage Suppressor of fourth embodiment of the invention further includes：Form at least one
The communication means 110 of a conduction.The upper surface of the communication means 110 through epitaxial layer 105 extend in Semiconductor substrate 101 and with
The first part 106a contacts of first isolated area so that Semiconductor substrate 101 pass through 110 and first isolated area of communication means the
A part of 106a electrical connections, thus by the PN junction by being formed between the first part 103a of the first buried layer and Semiconductor substrate 101
Anode and the cathode short circuit of (i.e. diode D3).
In the particular embodiment, the step of forming conductive communication means 110 includes：From the upper surface of epitaxial layer 105
Contact hole is made into Semiconductor substrate 101 so that the first part of the first isolated area is at least partly exposed, then, is contacting
Conductive material is filled in hole to form communication means 110.Conductive material for example by be selected from gold, silver, copper, aluminium, aluminium silicon, aluminium copper silicon,
The metal or alloy such as titanium silver, titanium nickel gold form.
As shown in figure 8, in the manufacturing method of the Transient Voltage Suppressor of fourth embodiment of the invention, electrode is further used
Lead the first part 108a of the second well region 109a and the first well region are electrically connected with draw Transient Voltage Suppressor 100 first
Electrode P1, and metal layer is formed so that Semiconductor substrate 101 to be drawn as second electrode P2 in the second surface of Semiconductor substrate 101
Go out.The first surface of Semiconductor substrate 101 is opposite with the second surface of Semiconductor substrate 101.
As can be seen that the Transient Voltage Suppressor provided according to embodiments of the present invention can be prepared by easy steps
It arrives, can realize the performance of low capacitance and the function of bidirectional transient voltage protection, the first electricity can be drawn respectively from tow sides
Pole and second electrode, and the cathode of extra PN junction and anode short circuit can be improved the performance of Transient Voltage Suppressor.
By selecting Semiconductor substrate, sacrificial layer and the epitaxial layer of identical doping type, the manufacture difficulty of epitaxial layer is reduced, so as to
It ensure that the stabilization of device parameters and performance.And mostly core devices are completed in the upper surface of epitaxial layer different from conventional single-chip
The solid of chip is largely utilized according to Transient Voltage Suppressor provided by the invention for design and the Integrated Solution made
The larger power device of footprint area is produced on chip interior by space, some only have design rule tightened up requirement
Device is placed on epitaxial layer upper surface and completes the production, chip area utilization rate higher, integrated level higher, and chip size obtains further
Compression, reduces packaging cost, has industrialization advantage.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any this practical relationship or sequence.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed or further include as this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
Also there are other identical elements in process, method, article or equipment including the element.
According to the embodiment of the present invention as described above, these embodiments are there is no all details of detailed descriptionthe, also not
It is only the specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle of the present invention and practical application, belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its four corner and equivalent.
Claims (17)
1. a kind of Transient Voltage Suppressor, wherein, including：
The Semiconductor substrate of first doping type；
The epitaxial layer of first doping type is set on the first surface of the Semiconductor substrate；
First buried layer of the second doping type and the second buried layer of the first doping type, second doping type and described first
Doping type is on the contrary, first buried layer extends from the first surface of the Semiconductor substrate into the Semiconductor substrate, institute
It states the first part of the first buried layer and second buried layer forms the first transient voltage and inhibits to manage, second of first buried layer
Divide and form the second transient voltage inhibition pipe with the Semiconductor substrate, the first part of first buried layer and second part be not mutual
Even；
Multiple isolated areas are extended to from the epi-layer surface in first buried layer or second buried layer respectively；
Multiple well regions are extended to from the epi-layer surface in the epitaxial layer,
Wherein, the first part of first buried layer forms PN junction, and the first of first buried layer with the Semiconductor substrate
Part is electrically connected with the Semiconductor substrate so that the PN junction is short-circuited, and first transient voltage inhibits pipe and described second
Transient voltage inhibits pipe to be connected between first electrode and second electrode, and second transient voltage inhibits the cathode warp of pipe
The Semiconductor substrate inhibits the anode of pipe to be electrically connected with first transient voltage.
2. Transient Voltage Suppressor according to claim 1, wherein,
The Semiconductor substrate, first buried layer and second buried layer, the epitaxial layer, the multiple isolated area and described
Multiple well regions form bidirectional transient voltage suppression circuit,
The bidirectional transient voltage suppression circuit includes：
First rectifying tube and the second rectifying tube inhibit pipe and second transient voltage to inhibit with first transient voltage respectively
Pipe differential concatenation is between the first electrode and the second electrode；
First transient voltage inhibits pipe and second transient voltage inhibits pipe, and second transient voltage inhibits the moon of pipe
Pole inhibits the anode of pipe to be electrically connected to lead to the second electrode, the sun of first rectifying tube with first transient voltage
The cathode of pole and second rectifying tube is electrically connected and leads to the first electrode,
The PN junction is connected between the anode of the second electrode and first transient voltage inhibition pipe.
3. Transient Voltage Suppressor according to claim 2, wherein, the multiple isolated area includes：
First isolated area of the second doping type, including first part and second part, the first part of first isolated area
It is connected with the first part of first buried layer to limit the first isolated island in the epitaxial layer, first isolated area
Second part is connected to limit the second isolated island in the epitaxial layer with the second part of first buried layer；
Second isolated area of the first doping type, second isolated area are connected to be isolated described first with second buried layer
The third isolated island of the epitaxial layer is limited in island.
4. Transient Voltage Suppressor according to claim 3, wherein, the multiple well region includes：
First well region of the second doping type, to form described first with the third isolated island in the third isolated island
Rectifying tube；
Second well region of the first doping type, the first part of second well region are located in second isolated island and as institute
State the cathode of the second rectifying tube, the first part of second well region is electrically connected with first well region and be used as described first electric
It draws pole.
5. Transient Voltage Suppressor according to claim 1, wherein,
The second surface of the Semiconductor substrate is equipped with metal layer so that the Semiconductor substrate to be drawn as the second electrode,
The first surface and second surface of the Semiconductor substrate are opposite.
6. Transient Voltage Suppressor according to claim 4, wherein, second well region further includes second part,
The second part of second well region is extended to from the upper surface of the epitaxial layer in the epitaxial layer, and with described first
First part's electrical connection of isolated area.
7. Transient Voltage Suppressor according to claim 6, wherein, the second part of second well region and described first
The first part of isolated area is electrically connected by being located at the electrode terminal of the upper surface of the epitaxial layer.
8. Transient Voltage Suppressor according to claim 4, wherein, the Transient Voltage Suppressor further includes conductive company
Logical component, upper surface of the communication means through the epitaxial layer extends in the Semiconductor substrate and is isolated with described first
First part's contact in area.
9. a kind of manufacturing method of Transient Voltage Suppressor, wherein, including：
The Semiconductor substrate of first doping type is provided；
Form the first buried layer of the second doping type and the second buried layer of the first doping type, second doping type with it is described
First doping type is on the contrary, first buried layer prolongs from the first surface of the Semiconductor substrate into the Semiconductor substrate
It stretches, first part and the Semiconductor substrate of first buried layer form PN junction, the first part and institute of first buried layer
It states the second buried layer and forms the first transient voltage and inhibit pipe, the second part of first buried layer and the Semiconductor substrate form the
Two transient voltages inhibit pipe, and the first part of first buried layer and second part do not interconnect；
The epitaxial layer of the first doping type is formed on the first surface of the Semiconductor substrate of the first doping type；
Form multiple isolated areas, the multiple isolated area extends to first buried layer or described from the epi-layer surface respectively
In second buried layer；
Multiple well regions are formed, the multiple well region is extended to from the epi-layer surface in the epitaxial layer；And
The first part of first buried layer is electrically connected with the Semiconductor substrate so that the PN junction is short-circuited, described first
Transient voltage inhibits pipe and second transient voltage that pipe is inhibited to be connected between first electrode and second electrode, and described the
Two transient voltages inhibit the cathode of pipe the anode of pipe to be inhibited to be electrically connected through the Semiconductor substrate and first transient voltage.
10. the manufacturing method of Transient Voltage Suppressor according to claim 9, wherein, form the multiple isolated area
Step includes：
Forming the first isolated area of the second doping type, first isolated area includes first part and second part, and described the
The first part of one isolated area is connected with the first part of first buried layer and is isolated with limiting first in the epitaxial layer
Island, the second part of second isolated area are connected to limit in the epitaxial layer with the second part of first buried layer
Second isolated island；
The second isolated area of the first doping type is formed, second isolated area is connected with second buried layer with described first
The third isolated island of the epitaxial layer is limited in isolated island.
11. the manufacturing method of Transient Voltage Suppressor according to claim 10, wherein, form the step of the multiple well region
Suddenly include：
The first well region of the second doping type is formed in the third isolated island；
The second well region of the first doping type is formed, the first part of second well region is formed in second isolated island,
The first part of second well region is electrically connected with first well region and the first electrode is used as to draw.
12. the manufacturing method of Transient Voltage Suppressor according to claim 11, wherein, the manufacturing method further includes：
Metal layer is formed so that the Semiconductor substrate to be drawn as the second electrode in the second surface of the Semiconductor substrate
Go out, the first surface and second surface of the Semiconductor substrate are opposite.
13. Transient Voltage Suppressor according to claim 11, wherein, by the first part of first buried layer with it is described
Semiconductor substrate is electrically connected so that the PN junction includes the step of being short-circuited：
The second part of second well region is formed, the second part of second well region extends from the upper surface of the epitaxial layer
It is electrically connected into the epitaxial layer and with the first part of first isolated area.
14. the manufacturing method of Transient Voltage Suppressor according to claim 13, wherein, second of second well region
Divide and be electrically connected with the first part of first isolated area by being located at the electrode terminal of the upper surface of the epitaxial layer.
15. the manufacturing method of Transient Voltage Suppressor according to claim 13, wherein, by the first of first buried layer
Part is electrically connected with the Semiconductor substrate so that the PN junction includes the step of being short-circuited：
Conductive communication means are formed, upper surface of the communication means through the epitaxial layer is extended in the Semiconductor substrate
And it is contacted with the first part of first isolated area.
16. the production method of Transient Voltage Suppressor according to claim 15, wherein, form conductive communication means
Step includes：
Contact hole is made in from the upper table of the epitaxial layer towards the Semiconductor substrate so that the first of first isolated area
Part is at least partly exposed；
Conductive material is filled in the contact hole to form the communication means.
17. the manufacturing method of Transient Voltage Suppressor according to claim 9, wherein, the Semiconductor substrate is provided
Step includes：
In the sacrificial layer of advance one doping type of growth regulation of the first surface of the Semiconductor substrate, the doping of the epitaxial layer is dense
Degree is less than the doping concentration of the sacrificial layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034108A (en) * | 2018-09-06 | 2019-07-19 | 晶焱科技股份有限公司 | Transient Voltage Suppressor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080217749A1 (en) * | 2005-07-27 | 2008-09-11 | Fred Matteson | Low Capacitance Transient Voltage Suppressor |
| CN102593155A (en) * | 2012-03-01 | 2012-07-18 | 浙江大学 | Multi-porous channel current equalizing-based transient voltage suppressor |
| CN105261616A (en) * | 2015-09-22 | 2016-01-20 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method thereof |
| CN205595334U (en) * | 2016-05-10 | 2016-09-21 | 北京燕东微电子有限公司 | Multichannel transient voltage inhibitor |
| US20170170167A1 (en) * | 2015-12-15 | 2017-06-15 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device capable of adjusting holding voltage |
| US20180082993A1 (en) * | 2006-11-16 | 2018-03-22 | Alpha And Omega Semiconductor Incorporated | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| CN207834298U (en) * | 2018-02-12 | 2018-09-07 | 北京燕东微电子有限公司 | Transient voltage suppressor |
-
2018
- 2018-02-12 CN CN201810146592.6A patent/CN108198811B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080217749A1 (en) * | 2005-07-27 | 2008-09-11 | Fred Matteson | Low Capacitance Transient Voltage Suppressor |
| US20180082993A1 (en) * | 2006-11-16 | 2018-03-22 | Alpha And Omega Semiconductor Incorporated | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| CN102593155A (en) * | 2012-03-01 | 2012-07-18 | 浙江大学 | Multi-porous channel current equalizing-based transient voltage suppressor |
| CN105261616A (en) * | 2015-09-22 | 2016-01-20 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method thereof |
| US20170170167A1 (en) * | 2015-12-15 | 2017-06-15 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device capable of adjusting holding voltage |
| CN205595334U (en) * | 2016-05-10 | 2016-09-21 | 北京燕东微电子有限公司 | Multichannel transient voltage inhibitor |
| CN207834298U (en) * | 2018-02-12 | 2018-09-07 | 北京燕东微电子有限公司 | Transient voltage suppressor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034108A (en) * | 2018-09-06 | 2019-07-19 | 晶焱科技股份有限公司 | Transient Voltage Suppressor |
| TWI714214B (en) * | 2018-09-06 | 2020-12-21 | 晶焱科技股份有限公司 | Transient voltage suppressor |
| US10930637B2 (en) | 2018-09-06 | 2021-02-23 | Amazing Microelectronic Corp. | Transient voltage suppressor |
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