CN207834297U - Transient voltage suppressor - Google Patents
Transient voltage suppressor Download PDFInfo
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- CN207834297U CN207834297U CN201820255346.XU CN201820255346U CN207834297U CN 207834297 U CN207834297 U CN 207834297U CN 201820255346 U CN201820255346 U CN 201820255346U CN 207834297 U CN207834297 U CN 207834297U
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- transient voltage
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- voltage suppressor
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Abstract
The utility model discloses Transient Voltage Suppressor, Transient Voltage Suppressor includes：The second epitaxial layer in semiconductor substrate and its first surface；First buried layer, extends into semiconductor substrate；Second buried layer, first part extends into semiconductor substrate, second part extends into the first buried layer；First isolated area extends into the second epitaxial layer to limit the first isolated island and the second isolated island；Second isolated area extends into the second epitaxial layer, and first part limits third isolated island in the first isolated island, and second part is connected with the first part of the second buried layer；First well region, a part extends into third isolated island, another part is connected by the first isolated area with the first buried layer；The second well region in the second isolated island is extended to, is electrically connected with the first part of the first well region.Transient Voltage Suppressor provided by the utility model has the function of bidirectional transient voltage inhibition, capacitance is low, it is small, be made simple, and extraction electrode can be distinguished from tow sides.
Description
Technical field
The utility model is related to semiconductor microelectronic technology fields, more particularly, to a kind of Transient Voltage Suppressor.
Background technology
Transient Voltage Suppressor (Transient Voltage Suppressor, TVS) is one kind of universal practicality at present
High-effect circuit brake, shape are no different with general-purpose diode, but its special structure and technological design can inhale
Receive up to thousands of watts of surge power.The working mechanism of Transient Voltage Suppressor is：Under the conditions of applied in reverse, work as transient voltage
When suppressor bears the big pulse of a high-energy, working impedance can quickly be down to extremely low conduction value, to allow big electricity
Stream flows through, while voltage clamp in predeterminated level, and the general response time is only 10-12Second, therefore electricity can be effectively protected
The damage of precision components in sub-line road from various surge pulses.
Relative to the unidirectional Transient Voltage Suppressor for being only capable of in a single direction protecting circuit, two-way transient state electricity
Pressure suppressor meets the feature for the classical electrical I-V curve for meeting almost symmetry in positive and negative both direction, to actually answer
In, the both direction of circuit can be protected simultaneously, so application range is wider.
The market of consumer electronics develops rapidly, and is constantly carried as the electronic product performance of representative using mobile phone and mobile terminal
It rises, mobile phone or mobile terminal etc. all have higher requirements to reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is transient state electricity
The rigid index that pressure suppressor must meet.
Bidirectional transient voltage suppressor in the prior art is generally made of longitudinal NPN or positive-negative-positive structure.Fig. 1 a show existing
There are the structural schematic diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in technology, Fig. 1 b to show have in the prior art
There is the structural schematic diagram of the bidirectional transient voltage suppressor of longitudinal NPN structures.Transient voltage as illustrated in figs. 1A and ib inhibits
Although device can realize larger power and preferable voltage symmetry, and of low cost, simple for process, pair of this structure
Capacitance to Transient Voltage Suppressor is larger, cannot meet the needs of existing market is to Transient Voltage Suppressor.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series of utilization encapsulation of the prior art
Principle schematic.It, can be by two groups of separation, the duplicate unidirectional transient state of performance to realize bidirectional transient voltage suppressor
Voltage suppressor is connected according to mode shown in Fig. 3 to realize the smaller bidirectional transient voltage suppressor of capacitance.However it is this double
Must have two groups of unidirectional Transient Voltage Suppressor Series Packages to Transient Voltage Suppressor, cost is higher, and for smaller
Packaging body, two groups of unidirectional Transient Voltage Suppressors can not encapsulate simultaneously, increase the difficulty in terms of manufacturing process.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor in two channel of the prior art.Such as
It, can be straight since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor in two channels are full symmetric shown in Fig. 2 b
It connects and draws two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor in two channels to realize the transient state electricity of bidirectional low-capacitance
Constrain system.However, under this application, since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor in two channels are necessary
It is drawn simultaneously from front, therefore chip area will increase, is not suitable for smaller packaging body；Simultaneously as in encapsulation process, two
Two tunnel ends of the unidirectional Transient Voltage Suppressor in channel each must make a call to a wires to draw two tunnel ends, this also can
Increase manufacturing cost.
Fig. 2 c show that a kind of of the prior art inhibits two poles using more independent rectifier diodes and common transient voltage
The principle schematic of the integrated bidirectional transient voltage suppressor of pipe encapsulation.As shown in Figure 2 c, since the bidirectional transient voltage inhibits
It needs to place 2 chips on Ji Dao in device, therefore is easy to cause the probability that encapsulation defect occurs and increases, to make chip patch
Cost it is higher；In encapsulation process, two tunnel ends need it is each make a call to a wires, but also cost increase；Simultaneously as
The integration packaging of multiple chips needs larger space, therefore the size of entire bidirectional transient voltage suppressor is larger, is not suitable for
Smaller packaging body.
Therefore, it is necessary to a kind of new, combining low capacitor design and the double of extraction electrode can be distinguished from tow sides
To Transient Voltage Suppressor.
Utility model content
In order to solve the above-mentioned problems of the prior art, the utility model provides a kind of Transient Voltage Suppressor, with full
Foot low cost, low capacitance, bidirectional transient voltage inhibit, small size encapsulates and have and can distinguish extraction electrode from tow sides
The market demands such as structure.
The utility model provides a kind of Transient Voltage Suppressor, wherein including：The semiconductor of first doping type serves as a contrast
Bottom, the semiconductor substrate are drawn as second electrode；Second epitaxial layer of the first doping type is set to the semiconductor lining
On the first surface at bottom；First buried layer of the second doping type is partly led from the first surface of the semiconductor substrate to described
Extend in body substrate, first buried layer includes first part and second part；Second buried layer of the first doping type, including the
A part and second part, the first part of second buried layer is from the first surface of the semiconductor substrate to the semiconductor
Extend in substrate, the second part of second buried layer prolongs from the first part of first buried layer into first buried layer
It stretches；First isolated area of the second doping type, first isolated area is from the upper table of second epitaxial layer towards described second
Extend in epitaxial layer, a part for first isolated area is connected with the first part of first buried layer with outside described second
Prolong and limit the first isolated island in layer, another part of first isolated area be connected with the second part of first buried layer with
The second isolated island is limited in second epitaxial layer；Second isolated area of the first doping type, second isolated area from
The upper table of second epitaxial layer in second epitaxial layer towards extending, a part for second isolated area and described second
The second part of buried layer is connected to limit the third isolated island of second epitaxial layer in first isolated island, and described the
Another part of two isolated areas is connected with the first part of second buried layer；First well region of the second doping type, described
One well region includes first part and second part, the first part of first well region from the upper table of second epitaxial layer towards
Extend in the third isolated island, the second part of first well region is from the upper table of second epitaxial layer towards described second
Extend in epitaxial layer and by first isolated area by the second of the first part of first buried layer and first buried layer
Part is electrically connected, and the second part of first well region is contacted with the second part of second isolated area；And first doping
Second well region of type is extended to from the upper surface of second epitaxial layer in second isolated island, second well region with
The first part of first well region is electrically connected and is drawn as first electrode.
Preferably, the first part of second buried layer be located at first buried layer first part and second part it
Between.
Preferably, contact surface of second isolated area between first isolated island and first isolated area is from institute
The upper table of the second epitaxial layer is stated towards extending to form the third isolated island in second epitaxial layer.
Preferably, the Transient Voltage Suppressor further includes metal layer, and the metal layer is set to the semiconductor substrate
Second surface, the first surface and the second surface of the semiconductor substrate be relative to each other.
Preferably, the Transient Voltage Suppressor further includes：Insulating layer is located at the upper surface of second epitaxial layer, and
It is equipped with contact hole in the first part of first well region, the corresponding position of second well region；Contact conductor, by described
The first part of first well region and the second well region are electrically connected to draw the first electrode by contact hole.
Preferably, the growth in advance of the first surface of the semiconductor substrate has the first epitaxial layer of the first doping type, institute
The first epitaxial layer is stated as sacrificial layer.
Preferably, the resistivity of the semiconductor substrate is less than 0.02 Ω cm, and the resistivity of first epitaxial layer is not
Less than 0.1 Ω cm.
Preferably, the doping concentration of second epitaxial layer is less than the doping concentration of first epitaxial layer.
Preferably, the thickness of first epitaxial layer is not less than 3 μm, and the thickness of second epitaxial layer is not less than 5 μm.
Preferably, the implantation dosage of first buried layer is not less than E14cm-2The doping of the order of magnitude, second buried layer is dense
Degree is not less than E19cm-3The doping concentration of the order of magnitude, first isolated area is not less than E18cm-3The order of magnitude, second isolation
The doping concentration in area is not less than E18cm-3The doping concentration of the order of magnitude, first well region is not less than E19cm-3The order of magnitude, it is described
The implantation dosage of second well region is not less than E14cm-2The order of magnitude.
Preferably, first doping type is N-type or p-type, and second doping type is another in N-type or p-type
It is a.
After the technical solution of the utility model, following advantageous effect can get：1, the performance of low capacitance can be realized
With the function of bidirectional transient voltage protection；2, first electrode and second electrode can be drawn respectively from tow sides；3, pass through choosing
With the semiconductor substrate of identical doping type, the first epitaxial layer and the second epitaxial layer, the manufacture difficulty of epitaxial layer is reduced, from
And it ensure that the stabilization of device parameters and performance；4, core devices mostly are completed in the upper surface of epitaxial layer different from conventional single-chip
Design and making Integrated Solution, chip is largely utilized according to Transient Voltage Suppressor provided by the utility model
Solid space, the larger power device of footprint area is produced on chip interior, only some have design rule it is tightened up
It is required that device be placed on epitaxial layer upper surface and complete the production, therefore chip area utilization rate higher, integrated level higher, chip size
It is further compressed, reduces packaging cost, have industrialization advantage.
Description of the drawings
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from.
Fig. 1 a show the structural schematic diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in the prior art.
Fig. 1 b show the structural schematic diagram of the bidirectional transient voltage suppressor with longitudinal direction NPN structures in the prior art.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series of utilization encapsulation of the prior art
Principle schematic.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor in two channel of the prior art.
Fig. 2 c show that a kind of of the prior art is sealed using more independent rectifier diodes and common Transient Suppression Diode
The principle schematic of the integrated bidirectional transient voltage suppressor of dress.
Fig. 3 shows the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3.
Fig. 5 shows the part-structure figure of Transient Voltage Suppressor in Fig. 3.
Fig. 6 a to 6j show each rank of manufacturing method according to the Transient Voltage Suppressor of the utility model first embodiment
The schematic cross-section of section.
Specific implementation mode
The utility model is described below based on embodiment, but the utility model is not restricted to these implementations
Example.It is detailed to describe some specific detail sections below in the datail description of the utility model embodiment, to this field
The description of part can also understand the utility model completely without these details for technical staff.In order to avoid obscuring this practicality
Novel essence, well known method, process, flow do not describe in detail.
In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in attached drawing
Various pieces are not necessarily to scale.In addition, certain well known parts may be not shown in figure.Flow chart, frame in attached drawing
Figure illustrates the system of the embodiments of the present invention, possible System Framework, the function and operation of method, apparatus, attached drawing
Box and box sequence are used only to the process and step of better diagram embodiment, without should be in this, as to utility model
The limitation of itself.
Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar
Reference numeral indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown
Certain well known parts.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
The form of presentation of face " or " A is on B and abuts therewith ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand,
The utility model can not be realized according to these specific details.
Fig. 3 shows the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.
The Transient Voltage Suppressor 100 that the utility model first embodiment provides is two-way TVS device, internal to have such as
Two-way inhibition equivalent circuit shown in Fig. 3, the two-way suppression circuit include the first rectifier diode D1, the second rectifier diode
D2, third rectifier diode D3, the first transient voltage suppressor diode T1 and the second transient voltage suppressor diode T2,
In, the anode of the first rectifier diode D1 is connected with the cathode of the second rectifier diode D2 using as (such as the positions first electrode P1
In the encapsulation front of Transient Voltage Suppressor 100), cathode and the third rectifier diode of the second transient voltage suppressor diode T2
The cathode of D3 is connected so that as second electrode P2 (such as positioned at encapsulation back side of Transient Voltage Suppressor 100), the second transient state is electric
The anode for constraining diode T2 processed is connected with the anode of the second rectifier diode D2, the anode and first of third rectifier diode D3
The anode of transient voltage suppressor diode T1 is connected, the cathode and the first rectifier diode of the first transient voltage suppressor diode T1
The cathode of D1 is connected.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3.Wherein, abscissa indicates transient state electricity
The voltage between the first electrode and second electrode of suppressor, the longitudinal axis is pressed to indicate from first electrode through Transient Voltage Suppressor 100
Flow to the electric current of second electrode.
From fig. 4, it can be seen that when reversed between the first electrode P1 and second electrode P2 of the Transient Voltage Suppressor 100
When voltage is more than certain threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of second electrode is by pincers
Position is to predeterminated level；When the forward voltage between the first electrode P1 and second electrode P2 of Transient Voltage Suppressor 100 is more than one
When determining threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of first electrode is clamped to predetermined water
It is flat.
Specifically, in conjunction with Fig. 3 it is found that when surge occurs：If bearing to bear between first electrode P1 and second electrode P2
Voltage, then the second rectifier diode D2 conductings, the second transient voltage suppressor diode T2 bears backward voltage, if the reversed electricity
The numerical value of pressure is higher than the breakdown voltage of the second transient voltage suppressor diode T2, then the work of the second transient voltage suppressor diode T2
A very low value can be dropped to allow high current to pass through, and at the same time by the voltage clamp of second electrode P2 immediately by making impedance
To predeterminated level, the electronic component being connected to protection between first electrode P1 and second electrode P2；If first electrode P1
Positive voltage is born between second electrode P2, then the first rectifier diode D1 and the D3 conductings of third rectifier diode, the first transient state
Voltage suppression diode T1 bears backward voltage, if the numerical value of the backward voltage is higher than the first transient voltage suppressor diode T1
Breakdown voltage, then the working impedance of the first transient voltage suppressor diode T1 can drop to a very low value immediately to allow
High current passes through, and at the same time the voltage clamp of first electrode P1 to predeterminated level is connected to first electrode P1 and to protect
Electronic component between two electrode P2 inhibits function to realize two-way transient voltage.
Fig. 5 shows the part-structure figure of Transient Voltage Suppressor in Fig. 3.
In the following description, it is specially one of p-type and N-type by the doping type for describing semi-conducting material.It is appreciated that
If inverting the doping type of each semi-conducting material, it is also possible to obtain the semiconductor devices of identical function.
As shown in figure 5, Transient Voltage Suppressor 100 includes first electrode P1, second electrode P2, semiconductor substrate 101, position
In on 101 first surface of semiconductor substrate the first epitaxial layer, the first buried layer 103, the second buried layer 104, be located at the first epitaxial layer
On the second epitaxial layer 105, the first isolated area 106, the second isolated area 107, the first well region 108 and the second well region 109.
Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, in order to form p-type or n type semiconductor layer or area
Domain can mix the dopant of respective type in semiconductor layer or region.For example, P-type dopant includes boron, N type dopant
Including phosphorus or arsenic or antimony.
In this embodiment, semiconductor substrate 101 is the heavily doped N-type substrate that resistivity is less than 0.02 Ω cm, doping
Agent is arsenic (As).Second electrode P2 is for example positioned at the second surface of semiconductor substrate 101, the first surface of semiconductor substrate 101
It is relative to each other with second surface.
First epitaxial layer is the lightly doped n type epitaxial layer for being grown in 101 first surface of semiconductor substrate, and resistivity is not small
In 0.1 Ω cm, and thickness is not less than 3 μm, and for the sacrificial layer as 101 first surface of semiconductor substrate, the sacrificial layer is most
At last by 101 back-diffusion of semiconductor substrate and compensate totally, therefore below part description in, be omitted to the first epitaxial layer
Description.
First buried layer 103 is, for example, p type buried layer.By sacrificial layer to the first surface injectant from semiconductor substrate 101
Amount is not less than E14cm-2The dopant (being, for example, boron) of the order of magnitude, and anneal, to form the first buried layer 103.First buried layer 103 wraps
Include first part and second part.
Second buried layer 104 is, for example, that doping concentration is not less than E19cm-3The N-type heavily doped region of the order of magnitude.Second buried layer 104
Including first part and second part, the first part of the second buried layer 104 extends to semiconductor substrate 101 from the first epitaxial layer
In, the second part of the second buried layer 104 is formed in the first part of the first buried layer 103 with first with the first buried layer 103
Divide and forms a PN junction.In Transient Voltage Suppressor 100, first part and the formation of semiconductor substrate 101 of the second buried layer 104
The conductive path of low-resistance.
Second epitaxial layer 105 is, for example, to cover to be grown in above the first surface of semiconductor substrate 101 of N-type heavy doping
N-type lightly doped district, the second buried layer 104 of covering, the first buried layer 103 and the first epitaxial layer, and resistivity is not less than 5 Ω
Cm, thickness are not less than 5 μm.Wherein, the resistivity of the second epitaxial layer 105 and thickness will determine the Transient Voltage Suppressor 100
Electric property, in actual implementation, those skilled in the art can freely adjust according to the needs of application.
First isolated area 106 is, for example, p-type isolated area, and doping concentration is not less than E18cm-3, dopant is, for example, boron.The
One isolated area 106 is extended to from the upper surface of the second epitaxial layer 105 in the second epitaxial layer 105, and with subsequent high temperature process
Further extend to the direction where semiconductor substrate 101, the second epitaxial layer is finally passed through in Transient Voltage Suppressor 100
105 with the first buried layer 103 to be connected.First isolated area 106 includes first part and second part, and the of the first isolated area 106
A part is connected with the first part of the first buried layer 103 to limit the first isolated island in the second epitaxial layer 105；First isolation
The second part in area 106 is connected with the second part of the first buried layer 103 and is isolated with limiting second in the second epitaxial layer 105
Island.
Second isolated area 107 is, for example, N-type isolated area, is not less than E18cm for doping concentration-3The N-type of the order of magnitude is heavily doped
Miscellaneous area, dopant are, for example, phosphorus.Second isolated area 107 include first part and second part, first of the second isolated area 107
Divide the upper table from the second epitaxial layer towards extension in the first isolated island and is connected with the second part of the second buried layer 104, thus
The third isolated island of the second epitaxial layer is further limited out in first isolated island, the third isolated island pass through the second isolated area
A part is connected with the second part of the second buried layer 104；The second part of second isolated area 107 is from 105 surface of the second epitaxial layer
The second epitaxial layer 105 is extended across to be connected with the first part of the second buried layer 104, to the second of the second isolated area 107
Partly, the first part of the second buried layer 104 forms a low resistance conductive for running through the second epitaxial layer 105 with semiconductor substrate 101
Access.Wherein, in order to form third isolated island, the first part of the second isolated area 107 and the first part of the first isolated area
Medial surface is least partially overlapped, i.e., the first part of the second isolated area 107 is isolated along the first part of the first isolated area with first
Contact surface between island extends to the second part of the second buried layer to form third isolated island from the upper surface of the second epitaxial layer.
First well region 108 is, for example, P type trap zone, is not less than E18cm for doping concentration-3The p-type heavily doped region of the order of magnitude,
Dopant is, for example, boron.First well region 108 includes first part and second part, and the first part of the first well region 108 is by second
Epitaxial layer 105 extends in third isolated island；The second part of first well region 108 is from 105 surface of the second epitaxial layer to outside second
Prolong and extends certain depth in layer 105 to connect first part and the second part of the first isolated area 106, to the first well region 108
First part the first part of the first buried layer 103 is connected with the second part of the first buried layer 103 by the first isolated area, and
The second part of first well region 108 is contacted with the second part of the second isolated area 107 to form PN junction.
Second well region 109 is, for example, N-type well region, is not less than E14cm for implantation dosage-2N-type heavily doped region, dopant
For example, phosphorus.Second well region 109 is extended to by 105 surface of the second epitaxial layer in the second isolated island.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, and insulating layer covers above the table of the second epitaxial layer 105
And it is equipped with contact hole in the corresponding position of the first part of the first well region 108 and the second well region 109 so that first electrode P1
The first part of first well region 108 and the second well region 109 can be electrically connected and drawn by contact hole by (being, for example, contact conductor)
Go out.
Insulation layers are such as made of silicon oxide or silicon nitride, first electrode P1 and second electrode P2 for example selected from gold, silver,
The metal or alloy such as copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
Corresponding to Fig. 3, in Transient Voltage Suppressor 100 shown in Fig. 5, semiconductor substrate 101 is as third rectification two
The cathode of pole pipe D3 is connected with second electrode P2, anode of first buried layer 103 as third rectifier diode D3, the first buried layer
Anode of 103 first part as the first transient voltage suppressor diode T1, the second part of the second buried layer 104 is as first
The cathode of transient voltage suppressor diode T1.
The first part of first well region 108 is extended in third isolated island by the second epitaxial layer 105 using as the first rectification
The anode of diode D1, third isolated island pass through the second isolated area 107 as the cathode of the first rectifier diode D1 first
Divide and is connected with the second part of the second buried layer 104 of the cathode as the first transient voltage suppressor diode T1.
The second part of second isolated area 107, the first part of the second buried layer 104 and semiconductor substrate 101 form one
Low resistance conductive access through the second epitaxial layer 105 is with the cathode collectively as the second transient voltage suppressor diode T2, and first
Anode of the second part of well region 108 as the second transient voltage suppressor diode T2, to the second part of the first well region 108
The second transient voltage suppressor diode T2 of subsurface diode structure is formed with the second part of the second isolated area 107.Due to
The influence of concentration, the breakdown interface of the PN junction of the second transient voltage suppressor diode T2 only include second of the first well region 108
Point and between the second part of the second isolated area 107 interface zone (because the second epitaxial layer 105 doping concentration it is relatively low,
Surface breakdown occurs for the interface zone therefore avoided between the second part of the first well region 108 and the second epitaxial layer 105).
The second rectifier diode is collectively formed in the second part of the second part of first isolated area 106 and the first buried layer 103
The anode of D2, the second well region 109 are extended in the second isolated island by 105 surface of the second epitaxial layer using as the second rectifier diode
The cathode of D2.Since the second part of the first well region 108 will be for the first part of the first isolated area 106 and second part phase
Even, therefore the anode of the second rectifier diode D2 is connected with the anode of the second transient voltage suppressor diode T2.
The first part of second well region 109 and the first well region 108 is electrically connected and is drawn by first electrode P1, to realize the
Connection between the anode of one rectifier diode D1 and the cathode of the second rectifier diode D2.
Fig. 6 a to 6j show each rank of manufacturing method according to the Transient Voltage Suppressor of the utility model first embodiment
The schematic cross-section of section.
As shown in Figure 6 a, the first epitaxial layer of N-type is formed in the first surface of the semiconductor substrate of N-type 101 using as partly
The sacrificial layer of the first surface of conductor substrate 101.
In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region
Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, semiconductor substrate 101
It is less than the heavily doped N-type substrate of 0.02 Ω cm for resistivity, dopant is arsenic (As).
The thickness of first epitaxial layer is not less than 3 μm, and resistivity is not less than 0.1 Ω cm, and final first epitaxial layer will be by half
101 back-diffusion of conductor substrate simultaneously compensates totally.
First epitaxial layer may be used known depositing technology and be formed.For example, depositing technology can be steamed selected from electron beam
One kind in hair, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in Figure 6 b, the first buried layer of p-type is formed in semiconductor substrate 101 through the first epitaxial layer.First buried layer is extremely
Include first part 103a and second part 103b less.
For example, being not less than E14cm to from the first surface implantation dosage of semiconductor substrate 101 by the first epitaxial layer-2Number
The dopant (being, for example, boron) of magnitude, and anneal, to form the first buried layer in semiconductor substrate 101.In actual implementation, this
Field technology personnel can freely adjust the doping concentration and junction depth of the first buried layer according to the needs of application.
As fig. 6 c, the second buried layer of N-type is formed.Second buried layer is, for example, that doping concentration is not less than E19cm-3The order of magnitude
N-type heavily doped region comprising first part 104a and second part 104b.The first part 104a of second buried layer is outside first
Prolong layer into semiconductor substrate 101 to extend, the second part 104b of the second buried layer is formed in the first part 103a of the first buried layer
In with the first part 103a of the first buried layer formed a PN junction.The first part 104a and semiconductor substrate of second buried layer
101 form the conductive path of low-resistance.
As shown in fig 6d, the second epitaxial layer 105 for forming N-type is buried with the first epitaxial layer of covering, the first buried layer and second
Layer.Second epitaxial layer 105 is, for example, N-type lightly doped district, and resistivity is not less than 5 Ω cm, and thickness is not less than 5 μm.Wherein,
The resistivity and thickness of two epitaxial layers 105 will determine the operating voltage and electric property of the Transient Voltage Suppressor 100, in reality
When implementation, those skilled in the art can freely adjust according to the needs of application.
Second epitaxial layer 105 may be used known depositing technology and be formed.For example, depositing technology can be selected from electron beam
One kind in evaporation, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in fig 6e, the first isolated area for forming p-type is extended to from the upper surface of the second epitaxial layer 105 outside second
Prolong in layer 105, and as subsequent high temperature process further extends to the direction where semiconductor substrate 101, eventually passes through the
Two epitaxial layers 105 with the first buried layer to be connected.
The doping concentration of first isolated area is for example not less than E18cm-3The order of magnitude, dopant are, for example, boron.
First isolated area includes first part 106a and second part 106b, wherein the first part of the first isolated area
106a is connected with the first part 103a of the first buried layer to limit the first isolated island 105a in the second epitaxial layer 105, and first
The second part 106b of isolated area is connected with the second part 103b of the first buried layer to limit second in the second epitaxial layer 105
Isolated island 105b.
As shown in Figure 6 f, the second isolated area of N-type is formed.Second isolated area is, for example, that doping concentration is not less than E18cm-3Number
The N-type heavily doped region of magnitude, dopant are, for example, phosphorus.
Second isolated area includes first part 107a and second part 107b, and the first part 107a of the second isolated area is from
The upper table of two epitaxial layers 105 is connected towards extension in the first isolated island 105a and with the second part 104b of the second buried layer, to
The third isolated island 105c of the second epitaxial layer 105 is further limited out in the second isolated island, third isolated island 105c passes through
The first part 107a of second isolated area is electrically connected with the second part 104b of the second buried layer；The second part of second isolated area
107b extends across the second epitaxial layer 105 with the first part 104a with the second buried layer from the upper surface of the second epitaxial layer 105
It is connected, to which the second part 107b of the second isolated area, the first part 104a of the second buried layer and semiconductor substrate 101 form one
A low resistance conductive access for running through the second epitaxial layer 105.Wherein, in order to form third isolated island 105c, the of the second isolated area
The medial surface of a part of 107a and the first part 106a of the first isolated area are least partially overlapped, i.e. first of the second isolated area
Divide contact surfaces of the 107a between the first part 106a and the first isolated island 105a of the first isolated area from the second epitaxial layer 105
Upper surface extends to the second part 104b of the second buried layer to form third isolated island 105c.
As shown in figure 6g, the first well region of p-type is formed.First well region is, for example, that doping concentration is not less than E18cm-3The order of magnitude
P-type heavily doped region, dopant is, for example, boron.
First well region includes first part 108a and second part 108b, and the first part 108a of the first well region is by outside second
The upper surface for prolonging layer 105 extends in third isolated island 105c；The second part 108b of first well region is by 105 table of the second epitaxial layer
Towards extension certain depth in the second epitaxial layer 105 to connect the first part 106a and second part 106b of the first isolated area,
To the first well region first part 108a by the first isolated area by the first part 103a of the first buried layer and the first buried layer
Second part 103b is connected, and the second part 108b of the first well region is contacted with the second part 107b of the second isolated area to be formed
PN junction.
As shown in figure 6h, the second well region 109 of N-type is formed.Second well region 109 is, for example, that implantation dosage is not less than E14cm-2
The N-type heavily doped region of the order of magnitude, dopant are, for example, phosphorus.Second well region 109 extends to by the upper surface of the second epitaxial layer 105
In two isolated island 105b.
As shown in Fig. 6 i, the first part 108a of the second well region 109 and the first well region is electrically connected with shape with contact conductor
It is connected with second electrode P2 at the first electrode P1 of Transient Voltage Suppressor 100, and by semiconductor substrate 101.
As shown in Fig. 6 j, second electrode P2 is for example formed in the second surface of semiconductor substrate 101, semiconductor substrate 101
First surface it is opposite with the second surface of semiconductor substrate 101.
Preferably, before semiconductor substrate 101 is connected with second electrode P2, first from the second of semiconductor substrate 101
Surface is to the thickness that semiconductor substrate 101 is thinned inside semiconductor substrate 101, to reduce the encapsulation of Transient Voltage Suppressor 100
Volume.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, and insulating layer covers the upper surface of the second epitaxial layer 105
And it is equipped with contact hole in the corresponding position of the first part 108a of the first well region and the second well region 109 so that first electrode P1
The first part 108a of the second well region 109 and the first well region can be electrically connected and be drawn by contact hole.
Insulation layers are such as made of silicon oxide or silicon nitride, first electrode P1 and second electrode P2 for example selected from gold, silver,
The metal or alloy such as copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
As can be seen that can be prepared by easy steps according to the Transient Voltage Suppressor that the utility model embodiment provides
It obtains, can realize the function of the performance and bidirectional transient voltage protection of low capacitance, and can respectively be drawn from tow sides
First electrode and second electrode.By selecting semiconductor substrate, the first epitaxial layer and the second epitaxial layer of identical doping type,
The manufacture difficulty for reducing epitaxial layer, to ensure that the stabilization of device parameters and performance.And exist different from conventional single-chip more
The Integrated Solution of design and the making of core devices is completed in the upper surface of epitaxial layer, according to transient voltage provided by the utility model
The solid space of chip is largely utilized in suppressor, and the larger power device of footprint area is produced on chip interior,
Only there is the device of tightened up requirement to be placed on epitaxial layer upper surface design rule some to complete the production, chip area utilization rate is more
Height, integrated level higher, chip size are further compressed, and packaging cost is reduced, and have industrialization advantage.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiments of the present invention, these embodiments there is no all details of detailed descriptionthe,
The specific embodiment that the utility model is only described is not limited yet.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With to enable skilled artisan to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (11)
1. a kind of Transient Voltage Suppressor, wherein including：
The semiconductor substrate of first doping type, the semiconductor substrate are drawn as second electrode；
Second epitaxial layer of the first doping type, is set on the first surface of the semiconductor substrate；
First buried layer of the second doping type extends from the first surface of the semiconductor substrate into the semiconductor substrate,
First buried layer includes first part and second part；
Second buried layer of the first doping type, including first part and second part, the first part of second buried layer is from institute
The first surface for stating semiconductor substrate extends into the semiconductor substrate, and the second part of second buried layer is from described first
The first part of buried layer extends into first buried layer；
First isolated area of the second doping type, first isolated area is from the upper table of second epitaxial layer towards described second
Extend in epitaxial layer, a part for first isolated area is connected with the first part of first buried layer with outside described second
Prolong and limit the first isolated island in layer, another part of first isolated area be connected with the second part of first buried layer with
The second isolated island is limited in second epitaxial layer；
Second isolated area of the first doping type, second isolated area is from the upper table of second epitaxial layer towards described second
Extend in epitaxial layer, a part for second isolated area be connected with the second part of second buried layer with described first every
The third isolated island of second epitaxial layer, another part of second isolated area and second buried layer are limited in Li Island
First part be connected；
First well region of the second doping type, first well region include first part and second part, first well region
First part from the upper table of second epitaxial layer towards extending in the third isolated island, the second part of first well region
From the upper table of second epitaxial layer towards extending in second epitaxial layer and by first isolated area by described first
The second part of the first part of buried layer and first buried layer is electrically connected, the second part and described second of first well region
The second part of isolated area contacts；And
Second well region of the first doping type is extended to from the upper surface of second epitaxial layer in second isolated island, institute
The first part for stating the second well region and first well region is electrically connected and is drawn as first electrode.
2. Transient Voltage Suppressor according to claim 1, wherein the first part of second buried layer is located at described the
Between the first part and second part of one buried layer.
3. Transient Voltage Suppressor according to claim 1, wherein second isolated area along first isolated island and
Contact surface between first isolated area is from the upper table of second epitaxial layer towards extending with shape in second epitaxial layer
At the third isolated island.
4. Transient Voltage Suppressor according to claim 1, wherein the Transient Voltage Suppressor further includes metal layer,
The metal layer is set to the second surface of the semiconductor substrate, the first surface of the semiconductor substrate and institute
It is relative to each other to state second surface.
5. Transient Voltage Suppressor according to claim 1, wherein the Transient Voltage Suppressor further includes：
Insulating layer is located at the upper surface of second epitaxial layer, and in the first part of first well region, second well region
Corresponding position be equipped with contact hole；
The first part of first well region and the second well region are electrically connected with described in extraction by contact conductor by the contact hole
First electrode.
6. Transient Voltage Suppressor according to claim 1, wherein the first surface of the semiconductor substrate is grown in advance
There is the first epitaxial layer of the first doping type, first epitaxial layer is as sacrificial layer.
7. Transient Voltage Suppressor according to claim 6, wherein the resistivity of the semiconductor substrate is less than 0.02
The resistivity of Ω cm, first epitaxial layer are not less than 0.1 Ω cm.
8. Transient Voltage Suppressor according to claim 6, wherein the doping concentration of second epitaxial layer is less than described
The doping concentration of first epitaxial layer.
9. Transient Voltage Suppressor according to claim 6, wherein the thickness of first epitaxial layer is not less than 3 μm, institute
The thickness for stating the second epitaxial layer is not less than 5 μm.
10. Transient Voltage Suppressor according to claim 1, wherein the implantation dosage of first buried layer is not less than
E14cm-2The doping concentration of the order of magnitude, second buried layer is not less than E19cm-3The doping of the order of magnitude, first isolated area is dense
Degree is not less than E18cm-3The doping concentration of the order of magnitude, second isolated area is not less than E18cm-3The order of magnitude, first well region
Doping concentration be not less than E19cm-3The implantation dosage of the order of magnitude, second well region is not less than E14cm-2The order of magnitude.
11. Transient Voltage Suppressor according to claim 1, wherein first doping type be N-type or p-type, it is described
Second doping type is another in N-type or p-type.
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|---|---|---|---|
| CN201820255346.XU CN207834297U (en) | 2018-02-12 | 2018-02-12 | Transient voltage suppressor |
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