CN108198813A - Transient Voltage Suppressor and its manufacturing method - Google Patents
Transient Voltage Suppressor and its manufacturing method Download PDFInfo
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- CN108198813A CN108198813A CN201810146821.4A CN201810146821A CN108198813A CN 108198813 A CN108198813 A CN 108198813A CN 201810146821 A CN201810146821 A CN 201810146821A CN 108198813 A CN108198813 A CN 108198813A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
The invention discloses Transient Voltage Suppressor and its manufacturing method, Transient Voltage Suppressor includes：The second epitaxial layer in Semiconductor substrate and its first surface；First buried layer, extends into Semiconductor substrate；Second buried layer, first part extends into Semiconductor substrate, second part extends into the first buried layer；First isolated area extends to limit the first isolated island and the second isolated island into the second epitaxial layer；Second isolated area extends into the second epitaxial layer, and first part limits third isolated island in the first isolated island, and second part is connected with the first part of the second buried layer；First well region, a part extension, another part into third isolated island are connected by the first isolated area with the first buried layer；The second well region in the second isolated island is extended to, is electrically connected with the first part of the first well region.Transient Voltage Suppressor provided by the invention has the function of bidirectional transient voltage inhibition, capacitance is low, it is small, be made simple, and extraction electrode can be distinguished from tow sides.
Description
Technical field
The present invention relates to semiconductor microelectronic technology field, more particularly, to a kind of Transient Voltage Suppressor and its system
Make method.
Background technology
Transient Voltage Suppressor (Transient Voltage Suppressor, TVS) is one kind of universal practicality at present
High-effect circuit brake, shape are no different with general-purpose diode, but its special structure and technological design can inhale
Receive up to thousands of watts of surge power.The working mechanism of Transient Voltage Suppressor is：Under the conditions of applied in reverse, work as transient voltage
When suppressor bears the big pulse of high-energy, working impedance can quickly be down to extremely low conduction value, so as to allow big electricity
Stream flows through, while voltage clamp in predeterminated level, and the general response time is only 10-12Second, therefore can effectively protect electricity
Precision components in sub-line road are from the damage of various surge pulses.
Relative to the unidirectional Transient Voltage Suppressor for being only capable of in a single direction protecting circuit, two-way transient state electricity
Pressure suppressor meets the feature for the classical electrical I-V curve for meeting almost symmetry in positive and negative both direction, so as to actually should
In, the both direction of circuit can be protected simultaneously, so application range is wider.
The market rapid development of consumer electronics, the electronic product performance using mobile phone and mobile terminal as representative constantly carry
It rises, mobile phone or mobile terminal etc. all have higher requirements to reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is transient state electricity
The rigid index that pressure suppressor must meet.
Bidirectional transient voltage suppressor of the prior art is generally made of the NPN or positive-negative-positive structure of longitudinal direction.Fig. 1 a show existing
There is the structure diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in technology, Fig. 1 b show have in the prior art
There is the structure diagram of the bidirectional transient voltage suppressor of longitudinal NPN structures.Transient voltage as illustrated in figs. 1A and ib inhibits
Although device can realize larger power and preferable voltage symmetry, and of low cost, simple for process, pair of this structure
It is larger to the capacitance of Transient Voltage Suppressor, it is impossible to meet the needs of existing market is to Transient Voltage Suppressor.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series encapsulation of utilization of the prior art
Principle schematic.It, can be by two groups of separation, the duplicate unidirectional transient state of performance to realize bidirectional transient voltage suppressor
Voltage suppressor connects to realize the smaller bidirectional transient voltage suppressor of capacitance according to mode shown in Fig. 3.It is however this double
Must have two groups of unidirectional Transient Voltage Suppressor Series Packages to Transient Voltage Suppressor, cost is higher, and for smaller
Packaging body, two groups of unidirectional Transient Voltage Suppressors can not encapsulate simultaneously, increase the difficulty in terms of manufacturing process.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor of two channel of the prior art.Such as
It, can be straight since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor of two channels are full symmetric shown in Fig. 2 b
Connect the transient state electricity two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor of two channels drawn to realize bidirectional low-capacitance
Constrain system.However, under this application, since two tunnel ends of the one-way low-capacitance Transient Voltage Suppressor of two channels are necessary
It is drawn simultaneously from front, therefore chip area can increase, is not suitable for smaller packaging body；Simultaneously as in encapsulation process, two
Two tunnel ends of the unidirectional Transient Voltage Suppressor of channel each must make a call to a wires to draw two tunnel ends, this also can
Increase manufacture cost.
Fig. 2 c show that a kind of of the prior art inhibits two poles using more independent rectifier diodes and common transient voltage
The principle schematic of the integrated bidirectional transient voltage suppressor of pipe encapsulation.As shown in Figure 2 c, since the bidirectional transient voltage inhibits
It needs to place 2 chips on Ji Dao in device, therefore is easy to cause the probability increase that encapsulation defect occurs, so as to make chip patch
Cost it is higher；In encapsulation process, two tunnel ends need it is each make a call to a wires, but also cost increase；Simultaneously as
The integration packaging of multiple chips needs larger space, therefore the size of entire bidirectional transient voltage suppressor is larger, is not suitable for
Smaller packaging body.
Therefore, it is necessary to a kind of new, combining low capacitor design and the double of extraction electrode can be distinguished from tow sides
To Transient Voltage Suppressor.
Invention content
In order to solve the above-mentioned problems of the prior art, the present invention provides a kind of Transient Voltage Suppressor and its manufacturer
Method, to meet, low cost, low capacitance, bidirectional transient voltage inhibit, small size encapsulates and have and can distinguish from tow sides
The market demands such as the structure of extraction electrode.
According to an aspect of the present invention, a kind of Transient Voltage Suppressor is provided, wherein, including：First doping type
Semiconductor substrate, the Semiconductor substrate are drawn as second electrode；Second epitaxial layer of the first doping type is set to described
On the first surface of Semiconductor substrate；First buried layer of the second doping type, from the first surface of the Semiconductor substrate to
Extend in the Semiconductor substrate, first buried layer includes first part and second part；The second of first doping type is buried
Layer, including first part and second part, the first part of second buried layer from the first surface of the Semiconductor substrate to
Extend in the Semiconductor substrate, the second part of second buried layer is from the first part of first buried layer to described first
Extend in buried layer；First isolated area of the second doping type, first isolated area from the upper table of second epitaxial layer towards
Extend in second epitaxial layer, a part for first isolated area is connected with the first part of first buried layer in institute
It states and the first isolated island is limited in the second epitaxial layer, second of another part of first isolated area and first buried layer
Split-phase connects to limit the second isolated island in second epitaxial layer；Second isolated area of the first doping type, described second
Isolated area from the upper table of second epitaxial layer towards second epitaxial layer in extend, a part for second isolated area with
The second part of second buried layer is connected is isolated with the third that second epitaxial layer is limited in first isolated island
Island, another part of second isolated area are connected with the first part of second buried layer；First trap of the second doping type
Area, first well region include first part and second part, and the first part of first well region is from second epitaxial layer
Upper table towards extending in the third isolated island, the second part of first well region is from the upper surface of second epitaxial layer
Extend into second epitaxial layer and by first isolated area by the first part of first buried layer and described first
The second part of buried layer is electrically connected, and the second part of first well region is contacted with the second part of second isolated area；With
And first doping type the second well region, extended in second isolated island from the upper surface of second epitaxial layer, it is described
The first part of second well region and first well region is electrically connected and first electrode is used as to draw.
Preferably, the first part of second buried layer be located at first buried layer first part and second part it
Between.
Preferably, second isolated area is along the contact surface between first isolated island and first isolated area from institute
The upper table of the second epitaxial layer is stated towards extension in second epitaxial layer to form the third isolated island.
Preferably, the Transient Voltage Suppressor further includes metal layer, and the metal layer is set to the Semiconductor substrate
Second surface, the first surface and the second surface of the Semiconductor substrate be relative to each other.
Preferably, the Transient Voltage Suppressor further includes：Insulating layer, positioned at the upper surface of second epitaxial layer, and
The corresponding position of first part, second well region in first well region is equipped with contact hole；Contact conductor, by described
The first part of first well region and the second well region are electrically connected to draw the first electrode by contact hole.
Preferably, the growth in advance of the first surface of the Semiconductor substrate has the first epitaxial layer of the first doping type, institute
The first epitaxial layer is stated as sacrificial layer.
Preferably, the resistivity of the Semiconductor substrate is less than 0.02 Ω cm, and the resistivity of first epitaxial layer is not
Less than 0.1 Ω cm.
Preferably, the doping concentration of second epitaxial layer is less than the doping concentration of first epitaxial layer.
Preferably, the thickness of first epitaxial layer is not less than 3 μm, and the thickness of second epitaxial layer is not less than 5 μm.
Preferably, the implantation dosage of first buried layer is not less than E14cm-2The order of magnitude, the doping of second buried layer are dense
Degree is not less than E19cm-3The order of magnitude, the doping concentration of first isolated area are not less than E18cm-3The order of magnitude, second isolation
The doping concentration in area is not less than E18cm-3The order of magnitude, the doping concentration of first well region are not less than E19cm-3The order of magnitude, it is described
The implantation dosage of second well region is not less than E14cm-2The order of magnitude.
Preferably, first doping type is N-type or p-type, and second doping type is another in N-type or p-type
It is a.
According to another aspect of the present invention, a kind of manufacturing method of Transient Voltage Suppressor is additionally provided, wherein, including：
Semiconductor substrate is provided；Form the first buried layer of the second doping type, first buried layer is from the first of the Semiconductor substrate
Surface extends into the Semiconductor substrate, and first buried layer includes first part and second part；Form the first doping class
Second buried layer of type, second buried layer include first part and second part, and the first part of second buried layer is from described
The first surface of Semiconductor substrate extends into the Semiconductor substrate, and the second part of second buried layer is buried from described first
The first part of layer extends into first buried layer；It is formed on the first surface of the Semiconductor substrate of the first doping type
Second epitaxial layer of the first doping type；Form the first isolated area of the second doping type, first isolated area is from described
The upper table of two epitaxial layers is towards extending in second epitaxial layer, a part for first isolated area and first buried layer
First part is connected to limit the first isolated island, another part of first isolated area and institute in second epitaxial layer
The second part for stating the first buried layer is connected to limit the second isolated island in second epitaxial layer；Form the first doping type
The second isolated area, second isolated area from the upper table of second epitaxial layer towards second epitaxial layer in extend, institute
It states a part for the second isolated area and the second part of second buried layer is connected to limit institute in first isolated island
State the third isolated island of the second epitaxial layer, first part's phase of another part of second isolated area and second buried layer
Even；The first well region of the second doping type is formed, first well region includes first part and second part, first well region
First part from the upper table of second epitaxial layer towards the third isolated island in extend, second of first well region
Extend in point from the upper table of second epitaxial layer towards second epitaxial layer and by first isolated area by described the
The second part of the first part of one buried layer and first buried layer is electrically connected, the second part of first well region and described the
The second part contact of two isolated areas；And the second well region of the first doping type is formed, from the upper table of second epitaxial layer
Face is extended in second isolated island, and the first part of second well region and first well region is electrically connected；Described in extraction
The first part of first well region and second well region are using as the first electrode；And the Semiconductor substrate is drawn to make
For second electrode.
Preferably, the first part of second buried layer be formed in first buried layer first part and second part it
Between.
Preferably, second isolated area from the upper table of second epitaxial layer towards second epitaxial layer in extend,
Second isolated area and the second part of second buried layer limit second epitaxial layer in first isolated island
Third isolated island the step of include：Second isolated area is along connecing between first isolated island and first isolated area
Contacting surface from the upper table of second epitaxial layer towards second epitaxial layer in extension to form the third isolated island.
Preferably, the Semiconductor substrate is drawn to include as the step of second electrode：In the Semiconductor substrate
Second surface forms metal layer, and the first surface and the second surface of the Semiconductor substrate are relative to each other.
Preferably, it before the step of second surface of the Semiconductor substrate forms metal layer, further includes：From described half
The Semiconductor substrate is thinned in the second surface of conductor substrate.
Preferably, draw first well region first part and second well region using the step as the first electrode
Suddenly include：Insulating layer is formed in the upper surface of second epitaxial layer；In the insulating layer and first of first well region
Divide and the corresponding position of second well region sets contact hole；And by the contact hole by the first of first well region
Part and second well region are electrically connected to draw the first electrode.
Preferably, the step of providing the Semiconductor substrate includes：In the pre- Mr. of the first surface of the Semiconductor substrate
First epitaxial layer of long first doping type, first epitaxial layer is as sacrificial layer.
Preferably, the doping concentration of second epitaxial layer is less than the doping concentration of first epitaxial layer.
Preferably, first doping type is N-type or p-type, and second doping type is another in N-type or p-type
It is a.
After technical solution using the present invention, following advantageous effect can be obtained：1st, the performance of low capacitance and double can be realized
The function of being protected to transient voltage；2nd, first electrode and second electrode can be drawn respectively from tow sides；3rd, by selecting phase
Semiconductor substrate, the first epitaxial layer and the second epitaxial layer with doping type reduce the manufacture difficulty of epitaxial layer, so as to protect
The stabilization of device parameters and performance is demonstrate,proved；4th, different from conventional single-chip mostly setting for core devices is completed in the upper surface of epitaxial layer
Meter and the Integrated Solution made, the solid that chip is largely utilized according to Transient Voltage Suppressor provided by the invention are empty
Between, the larger power device of footprint area is produced on chip interior, the device that some only have design rule to tightened up requirement
Part is placed on epitaxial layer upper surface and completes the production, therefore chip area utilization rate higher, integrated level higher, chip size are obtained into one
Step compression, reduces packaging cost, has industrialization advantage.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 a show the structure diagram of the bidirectional transient voltage suppressor with longitudinal P NP structures in the prior art.
Fig. 1 b show the structure diagram of the bidirectional transient voltage suppressor with longitudinal direction NPN structures in the prior art.
Fig. 2 a show the bidirectional transient voltage suppressor of two groups of one-way low-capacitance chip-in series encapsulation of utilization of the prior art
Principle schematic.
Fig. 2 b show a kind of principle schematic of the one-way low-capacitance Transient Voltage Suppressor of two channel of the prior art.
Fig. 2 c show that a kind of of the prior art is sealed using more independent rectifier diodes and common Transient Suppression Diode
The principle schematic of the integrated bidirectional transient voltage suppressor of dress.
Fig. 3 shows the circuit diagram for the Transient Voltage Suppressor that first embodiment of the invention provides.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3.
Fig. 5 shows the part-structure figure of Transient Voltage Suppressor in Fig. 3.
Fig. 6 a to 6j show the manufacturing method of Transient Voltage Suppressor according to a first embodiment of the present invention each stage
Schematic cross-section.
Specific embodiment
Below based on embodiment, present invention is described, but the present invention is not restricted to these embodiments.Under
Text is detailed to describe some specific detail sections in the datail description of the embodiment of the present invention, and those skilled in the art are come
The present invention can also be understood completely by saying the description of part without these details.It is well known in order to avoid obscuring the essence of the present invention
Method, process, flow do not describe in detail.
In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in attached drawing
Various pieces are not necessarily to scale.In addition, certain well known parts may be not shown in figure.Flow chart, frame in attached drawing
Figure illustrates possible System Framework, function and the operation of the system of the embodiment of the present invention, method, apparatus, the box of attached drawing
And box sequence is used only to the process and step of better diagram embodiment, without should be in this, as the limit to invention itself
System.
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown certain
Well known part.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, it is known as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
It if, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted directly against rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the present invention, such as the structure of device, material, size, processing work is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Fig. 3 shows the circuit diagram for the Transient Voltage Suppressor that first embodiment of the invention provides.
The Transient Voltage Suppressor 100 that first embodiment of the invention provides is two-way TVS device, internal to have such as Fig. 3
Shown two-way inhibition equivalent circuit, the two-way suppression circuit include the first rectifier diode D1, the second rectifier diode D2, the
Three rectifier diode D3, the first transient voltage suppressor diode T1 and the second transient voltage suppressor diode T2, wherein, first
The anode of rectifier diode D1 be connected with the cathode of the second rectifier diode D2 using as first electrode P1 (such as positioned at transient state electricity
Press the encapsulation front of suppressor 100), the cathode of the second transient voltage suppressor diode T2 and the cathode of third rectifier diode D3
It is connected so that as second electrode P2 (such as positioned at encapsulation back side of Transient Voltage Suppressor 100), the second transient voltage inhibits two
The anode of pole pipe T2 is connected with the anode of the second rectifier diode D2, the anode and the first transient voltage of third rectifier diode D3
The anode of diode T1 is inhibited to be connected, the cathode of the cathode of the first transient voltage suppressor diode T1 and the first rectifier diode D1
It is connected.
Fig. 4 shows the VA characteristic curve schematic diagram of Transient Voltage Suppressor in Fig. 3.Wherein, abscissa represents transient state electricity
The voltage between the first electrode and second electrode of suppressor is pressed, the longitudinal axis is represented from first electrode through Transient Voltage Suppressor 100
Flow to the electric current of second electrode.
From fig. 4, it can be seen that when reversed between the first electrode P1 of the Transient Voltage Suppressor 100 and second electrode P2
When voltage is more than certain threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of second electrode is by pincers
Position is to predeterminated level；When the forward voltage between the first electrode P1 of Transient Voltage Suppressor 100 and second electrode P2 is more than one
When determining threshold value, Transient Voltage Suppressor 100 being capable of transient switching high current so that the voltage of first electrode is clamped to predetermined water
It is flat.
Specifically, with reference to Fig. 3 it is found that when surge occurs：If it bears to bear between first electrode P1 and second electrode P2
Voltage, then the second rectifier diode D2 conductings, the second transient voltage suppressor diode T2 bears backward voltage, if the reversed electricity
The work of breakdown voltage, then second transient voltage suppressor diode T2 of the numerical value of pressure higher than the second transient voltage suppressor diode T2
A very low value can be dropped to so that high current to be allowed to pass through immediately by making impedance, and at the same time the voltage clamp by second electrode P2
To predeterminated level, so as to protect the electronic component being connected between first electrode P1 and second electrode P2；If first electrode P1
Positive voltage is born between second electrode P2, then the first rectifier diode D1 and third rectifier diode D3 conductings, the first transient state
Voltage suppression diode T1 bears backward voltage, if the numerical value of the backward voltage is higher than the first transient voltage suppressor diode T1
Breakdown voltage, then the working impedance of the first transient voltage suppressor diode T1 can drop to a very low value immediately to allow
High current passes through, and at the same time the voltage clamp of first electrode P1 to predeterminated level is connected to first electrode P1 and to protect
Electronic component between two electrode P2, it is achieved thereby that two-way transient voltage inhibits function.
Fig. 5 shows the part-structure figure of Transient Voltage Suppressor in Fig. 3.
In the following description, it is specially one of p-type and N-type by the doping type for describing semi-conducting material.It is appreciated that
If invert the doping type of each semi-conducting material, it is also possible to obtain the semiconductor devices of identical function.
As shown in figure 5, Transient Voltage Suppressor 100 includes first electrode P1, second electrode P2, Semiconductor substrate 101, position
In on 101 first surface of Semiconductor substrate the first epitaxial layer, the first buried layer 103, the second buried layer 104, positioned at the first epitaxial layer
On the second epitaxial layer 105, the first isolated area 106, the second isolated area 107, the first well region 108 and the second well region 109.
Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, in order to form p-type or n type semiconductor layer or area
Domain can mix the dopant of respective type in semiconductor layer or region.For example, P-type dopant includes boron, N type dopant
Including phosphorus or arsenic or antimony.
In this embodiment, Semiconductor substrate 101 is less than the heavily doped N-type substrate of 0.02 Ω cm, doping for resistivity
Agent is arsenic (As).Second electrode P2 is for example positioned at the second surface of Semiconductor substrate 101, the first surface of Semiconductor substrate 101
It is relative to each other with second surface.
First epitaxial layer is the lightly doped n type epitaxial layer for being grown in 101 first surface of Semiconductor substrate, and resistivity is not small
In 0.1 Ω cm, and thickness, not less than 3 μm, for the sacrificial layer as 101 first surface of Semiconductor substrate, the sacrificial layer is most
At last by 101 back-diffusion of Semiconductor substrate and compensate totally, therefore below part description in, be omitted to the first epitaxial layer
Description.
First buried layer 103 is, for example, p type buried layer.By sacrificial layer to the first surface injectant from Semiconductor substrate 101
Amount is not less than E14cm-2The dopant (being, for example, boron) of the order of magnitude, and anneal, to form the first buried layer 103.First buried layer 103 wraps
Include first part and second part.
Second buried layer 104 is, for example, that doping concentration is not less than E19cm-3The N-type heavily doped region of the order of magnitude.Second buried layer 104
Including first part and second part, the first part of the second buried layer 104 extends to Semiconductor substrate 101 from the first epitaxial layer
In, the second part of the second buried layer 104 is formed in the first part of the first buried layer 103 with first with the first buried layer 103
Divide and form a PN junction.In Transient Voltage Suppressor 100, first part and the Semiconductor substrate 101 of the second buried layer 104 are formed
The conductive path of low-resistance.
Second epitaxial layer 105 is, for example, to cover to be grown in above the first surface of Semiconductor substrate 101 of N-type heavy doping
N-type lightly doped district, the second buried layer 104 of covering, the first buried layer 103 and the first epitaxial layer, and resistivity is not less than 5 Ω
Cm, thickness are not less than 5 μm.Wherein, the resistivity of the second epitaxial layer 105 and thickness will determine the Transient Voltage Suppressor 100
Electric property, in actual implementation, those skilled in the art can freely adjust according to the needs of application.
First isolated area 106 is, for example, p-type isolated area, and doping concentration is not less than E18cm-3, dopant is, for example, boron.The
One isolated area 106 is extended to from the upper surface of the second epitaxial layer 105 in the second epitaxial layer 105, and with subsequent high temperature process
Further extend to the direction where Semiconductor substrate 101, the second epitaxial layer is finally passed through in Transient Voltage Suppressor 100
105 with the first buried layer 103 to be connected.First isolated area 106 includes first part and second part, and the of the first isolated area 106
A part is connected to limit the first isolated island in the second epitaxial layer 105 with the first part of the first buried layer 103；First isolation
The second part in area 106 is connected with the second part of the first buried layer 103 and is isolated with limiting second in the second epitaxial layer 105
Island.
Second isolated area 107 is, for example, N-type isolated area, is not less than E18cm for doping concentration-3The N-type of the order of magnitude is heavily doped
Miscellaneous area, dopant are, for example, phosphorus.Second isolated area 107 include first part and second part, first of the second isolated area 107
Divide in from the upper table of the second epitaxial layer towards the first isolated island and extend and be connected with the second part of the second buried layer 104, thus
The third isolated island of the second epitaxial layer is further limited in first isolated island, the third isolated island pass through the second isolated area
A part is connected with the second part of the second buried layer 104；The second part of second isolated area 107 is from 105 surface of the second epitaxial layer
It extends across the second epitaxial layer 105 with the first part with the second buried layer 104 to be connected, so as to the second of the second isolated area 107
Partly, the first part of the second buried layer 104 forms a low resistance conductive for running through the second epitaxial layer 105 with Semiconductor substrate 101
Access.Wherein, in order to form third isolated island, the first part of the second isolated area 107 and the first part of the first isolated area
Medial surface is least partially overlapped, i.e., the first part of the second isolated area 107 is isolated along the first part of the first isolated area with first
Contact surface between island extends to the second part of the second buried layer to form third isolated island from the upper surface of the second epitaxial layer.
First well region 108 is, for example, P type trap zone, is not less than E18cm for doping concentration-3The p-type heavily doped region of the order of magnitude,
Dopant is, for example, boron.First well region 108 includes first part and second part, and the first part of the first well region 108 is by second
Epitaxial layer 105 is extended in third isolated island；The second part of first well region 108 is from 105 surface of the second epitaxial layer outside second
Prolong and extend certain depth in layer 105 to connect the first part of the first isolated area 106 and second part, so as to the first well region 108
First part the first part of the first buried layer 103 is connected with the second part of the first buried layer 103 by the first isolated area, and
The second part of first well region 108 contacts to form PN junction with the second part of the second isolated area 107.
Second well region 109 is, for example, N-type well region, is not less than E14cm for implantation dosage-2N-type heavily doped region, dopant
For example, phosphorus.Second well region 109 is extended to by 105 surface of the second epitaxial layer in the second isolated island.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, and insulating layer is covered above the table of the second epitaxial layer 105
And it is equipped with contact hole in the first part of the first well region 108 and the corresponding position of the second well region 109 so that first electrode P1
The first part of first well region 108 and the second well region 109 can be electrically connected and drawn by contact hole by (being, for example, contact conductor)
Go out.
Insulation layers are such as made of silica or silicon nitride, first electrode P1 and second electrode P2 for example selected from gold, silver,
The metal or alloy such as copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
Corresponding to Fig. 3, in Transient Voltage Suppressor 100 shown in Fig. 5, Semiconductor substrate 101 is as third rectification two
The cathode of pole pipe D3 is connected with second electrode P2, anode of first buried layer 103 as third rectifier diode D3, the first buried layer
Anode of 103 first part as the first transient voltage suppressor diode T1, the second part of the second buried layer 104 is as first
The cathode of transient voltage suppressor diode T1.
The first part of first well region 108 is extended in third isolated island by the second epitaxial layer 105 using as the first rectification
The anode of diode D1, third isolated island pass through the second isolated area 107 as the cathode of the first rectifier diode D1 first
Divide and be connected with the second part of the second buried layer 104 of the cathode as the first transient voltage suppressor diode T1.
The second part of second isolated area 107, the first part of the second buried layer 104 and Semiconductor substrate 101 form one
Low resistance conductive access through the second epitaxial layer 105 is with the cathode collectively as the second transient voltage suppressor diode T2, and first
Anode of the second part of well region 108 as the second transient voltage suppressor diode T2, so as to the second part of the first well region 108
The second transient voltage suppressor diode T2 of subsurface diode structure is formed with the second part of the second isolated area 107.Due to
The influence of concentration, the breakdown interface of the PN junction of the second transient voltage suppressor diode T2 only include second of the first well region 108
Point and between the second part of the second isolated area 107 interface zone (because the second epitaxial layer 105 doping concentration it is relatively low,
Surface breakdown occurs for the interface zone therefore avoided between the second part of the first well region 108 and the second epitaxial layer 105).
The second rectifier diode is collectively formed in the second part of the second part of first isolated area 106 and the first buried layer 103
The anode of D2, the second well region 109 are extended in the second isolated island by 105 surface of the second epitaxial layer using as the second rectifier diode
The cathode of D2.Since the second part of the first well region 108 will be for the first part of the first isolated area 106 and second part phase
Even, therefore the anode of the second rectifier diode D2 is connected with the anode of the second transient voltage suppressor diode T2.
The first part of second well region 109 and the first well region 108 is electrically connected and drawn by first electrode P1, so as to fulfill
Connection between the cathode of the anode of one rectifier diode D1 and the second rectifier diode D2.
Fig. 6 a to 6j show the manufacturing method of Transient Voltage Suppressor according to a first embodiment of the present invention each stage
Schematic cross-section.
As shown in Figure 6 a, the first epitaxial layer of N-type is formed in the first surface of the Semiconductor substrate of N-type 101 using as partly
The sacrificial layer of the first surface of conductor substrate 101.
In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region
Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, Semiconductor substrate 101
It is less than the heavily doped N-type substrate of 0.02 Ω cm for resistivity, dopant is arsenic (As).
The thickness of first epitaxial layer is not less than 3 μm, and resistivity is not less than 0.1 Ω cm, and final first epitaxial layer will be by half
101 back-diffusion of conductor substrate simultaneously compensates totally.
First epitaxial layer may be used known depositing technology and be formed.For example, depositing technology can be steamed selected from electron beam
One kind in hair, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in Figure 6 b, the first buried layer of p-type is formed in Semiconductor substrate 101 through the first epitaxial layer.First buried layer is extremely
Include first part 103a and second part 103b less.
For example, E14cm is not less than to the first surface implantation dosage from Semiconductor substrate 101 by the first epitaxial layer-2Number
The dopant (being, for example, boron) of magnitude, and anneal, to form the first buried layer in Semiconductor substrate 101.In actual implementation, this
Field technology personnel can freely adjust the doping concentration and junction depth of the first buried layer according to the needs of application.
As fig. 6 c, the second buried layer of N-type is formed.Second buried layer is, for example, that doping concentration is not less than E19cm-3The order of magnitude
N-type heavily doped region, including first part 104a and second part 104b.The first part 104a of second buried layer is outside first
Prolong layer into Semiconductor substrate 101 to extend, the second part 104b of the second buried layer is formed in the first part 103a of the first buried layer
In with the first part 103a of the first buried layer formed a PN junction.The first part 104a and Semiconductor substrate of second buried layer
101 form the conductive path of low-resistance.
As shown in fig 6d, the second epitaxial layer 105 of N-type is formed, is buried with the first epitaxial layer of covering, the first buried layer and second
Layer.Second epitaxial layer 105 is, for example, N-type lightly doped district, and resistivity is not less than 5 Ω cm, and thickness is not less than 5 μm.Wherein,
The operating voltage and electric property that the resistivity and thickness of two epitaxial layers 105 will determine the Transient Voltage Suppressor 100, in reality
During implementation, those skilled in the art can freely adjust according to the needs of application.
Second epitaxial layer 105 may be used known depositing technology and be formed.For example, depositing technology can be selected from electron beam
One kind in evaporation, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in fig 6e, the first isolated area of p-type is formed, is extended to outside second from the upper surface of the second epitaxial layer 105
Prolong in layer 105, and as subsequent high temperature process further extends to the direction where Semiconductor substrate 101, eventually pass through the
Two epitaxial layers 105 with the first buried layer to be connected.
The doping concentration of first isolated area is for example not less than E18cm-3The order of magnitude, dopant are, for example, boron.
First isolated area includes first part 106a and second part 106b, wherein, the first part of the first isolated area
106a is connected to limit the first isolated island 105a in the second epitaxial layer 105 with the first part 103a of the first buried layer, and first
The second part 106b of isolated area is connected to limit second in the second epitaxial layer 105 with the second part 103b of the first buried layer
Isolated island 105b.
As shown in Figure 6 f, the second isolated area of N-type is formed.Second isolated area is, for example, that doping concentration is not less than E18cm-3Number
The N-type heavily doped region of magnitude, dopant are, for example, phosphorus.
Second isolated area includes first part 107a and second part 107b, and the first part 107a of the second isolated area is from the
The upper table of two epitaxial layers 105 is connected towards extension in the first isolated island 105a and with the second part 104b of the second buried layer, so as to
The third isolated island 105c of the second epitaxial layer 105 is further limited in the second isolated island, third isolated island 105c passes through
The first part 107a of second isolated area is electrically connected with the second part 104b of the second buried layer；The second part of second isolated area
107b extends across the second epitaxial layer 105 with the first part 104a with the second buried layer from the upper surface of the second epitaxial layer 105
It is connected, the first part 104a and Semiconductor substrate 101 of second part 107b, the second buried layer so as to the second isolated area form one
A low resistance conductive access for running through the second epitaxial layer 105.Wherein, in order to form third isolated island 105c, the of the second isolated area
The medial surface of a part of 107a and the first part 106a of the first isolated area are least partially overlapped, i.e. first of the second isolated area
Point 107a is along the contact surface between the first part 106a and the first isolated island 105a of the first isolated area from the second epitaxial layer 105
Upper surface extends to the second part 104b of the second buried layer to form third isolated island 105c.
As shown in figure 6g, the first well region of p-type is formed.First well region is, for example, that doping concentration is not less than E18cm-3The order of magnitude
P-type heavily doped region, dopant is, for example, boron.
First well region includes first part 108a and second part 108b, and the first part 108a of the first well region is by outside second
The upper surface for prolonging layer 105 is extended in third isolated island 105c；The second part 108b of first well region is by 105 table of the second epitaxial layer
Extend certain depth in towards the second epitaxial layer 105 to connect the first part 106a of the first isolated area and second part 106b,
So as to the first well region first part 108a by the first isolated area by the first part 103a of the first buried layer and the first buried layer
Second part 103b is connected, and the second part 108b of the first well region contacts to be formed with the second part 107b of the second isolated area
PN junction.
As shown in figure 6h, the second well region 109 of N-type is formed.Second well region 109 is, for example, that implantation dosage is not less than E14cm-2
The N-type heavily doped region of the order of magnitude, dopant are, for example, phosphorus.Second well region 109 extends to by the upper surface of the second epitaxial layer 105
In two isolated island 105b.
As shown in Fig. 6 i, the first part 108a of the second well region 109 and the first well region is electrically connected with shape with contact conductor
It is connected into the first electrode P1 of Transient Voltage Suppressor 100, and by Semiconductor substrate 101 with second electrode P2.
As shown in Fig. 6 j, second electrode P2 is for example formed in the second surface of Semiconductor substrate 101, Semiconductor substrate 101
First surface it is opposite with the second surface of Semiconductor substrate 101.
Preferably, before Semiconductor substrate 101 is connected with second electrode P2, first from the second of Semiconductor substrate 101
The thickness of Semiconductor substrate 101 is thinned to the inside of Semiconductor substrate 101 for surface, to reduce the encapsulation of Transient Voltage Suppressor 100
Volume.
Preferably, Transient Voltage Suppressor 100 further includes insulating layer, and insulating layer covers the upper surface of the second epitaxial layer 105
And it is equipped with contact hole in the first part 108a of the first well region and the corresponding position of the second well region 109 so that first electrode P1
The first part 108a of the second well region 109 and the first well region can be electrically connected and be drawn by contact hole.
Insulation layers are such as made of silica or silicon nitride, first electrode P1 and second electrode P2 for example selected from gold, silver,
The metal or alloy such as copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
As can be seen that the Transient Voltage Suppressor provided according to embodiments of the present invention can be prepared by easy steps
It arrives, can realize the performance of low capacitance and the function of bidirectional transient voltage protection, and the can be drawn respectively from tow sides
One electrode and second electrode.By selecting Semiconductor substrate, the first epitaxial layer and the second epitaxial layer of identical doping type, drop
The low manufacture difficulty of epitaxial layer, so as to ensure that the stabilization of device parameters and performance.And different from conventional single-chip mostly outside
Prolong the Integrated Solution of design and the making of the upper surface completion core devices of layer, according to Transient Voltage Suppressor provided by the invention
The solid space of chip is largely utilized, the larger power device of footprint area is produced on chip interior, only by one
There is the device of tightened up requirement to be placed on epitaxial layer upper surface to design rule a bit to complete the production, chip area utilization rate higher, collect
Into degree higher, chip size is further compressed, reduces packaging cost, have industrialization advantage.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any this practical relationship or sequence.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed or further include as this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
Also there are other identical elements in process, method, article or equipment including the element.
According to the embodiment of the present invention as described above, these embodiments are there is no all details of detailed descriptionthe, also not
It is only the specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle of the present invention and practical application, belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its four corner and equivalent.
Claims (20)
1. a kind of Transient Voltage Suppressor, wherein, including：
The Semiconductor substrate of first doping type, the Semiconductor substrate are drawn as second electrode；
Second epitaxial layer of the first doping type, is set on the first surface of the Semiconductor substrate；
First buried layer of the second doping type extends from the first surface of the Semiconductor substrate into the Semiconductor substrate,
First buried layer includes first part and second part；
Second buried layer of the first doping type, including first part and second part, the first part of second buried layer is from institute
The first surface for stating Semiconductor substrate extends into the Semiconductor substrate, and the second part of second buried layer is from described first
The first part of buried layer extends into first buried layer；
First isolated area of the second doping type, first isolated area is from the upper table of second epitaxial layer towards described second
Extend in epitaxial layer, a part for first isolated area is connected with the first part of first buried layer with outside described second
Prolong and the first isolated island limited in layer, another part of first isolated area be connected with the second part of first buried layer with
The second isolated island is limited in second epitaxial layer；
Second isolated area of the first doping type, second isolated area is from the upper table of second epitaxial layer towards described second
Extend in epitaxial layer, a part for second isolated area be connected with the second part of second buried layer with described first every
The third isolated island of second epitaxial layer, another part of second isolated area and second buried layer are limited in Li Island
First part be connected；
First well region of the second doping type, first well region include first part and second part, first well region
First part from the upper table of second epitaxial layer towards the third isolated island in extend, the second part of first well region
Extend in from the upper table of second epitaxial layer towards second epitaxial layer and by first isolated area by described first
The second part of the first part of buried layer and first buried layer is electrically connected, the second part and described second of first well region
The second part contact of isolated area；And
Second well region of the first doping type is extended to from the upper surface of second epitaxial layer in second isolated island, institute
The first part for stating the second well region and first well region is electrically connected and first electrode is used as to draw.
2. Transient Voltage Suppressor according to claim 1, wherein, the first part of second buried layer is located at described the
Between the first part of one buried layer and second part.
3. Transient Voltage Suppressor according to claim 1, wherein, second isolated area along first isolated island and
Contact surface between first isolated area from the upper table of second epitaxial layer towards second epitaxial layer in extension with shape
Into the third isolated island.
4. Transient Voltage Suppressor according to claim 1, wherein, the Transient Voltage Suppressor further includes metal layer,
The metal layer is set to the second surface of the Semiconductor substrate, the first surface of the Semiconductor substrate and institute
It is relative to each other to state second surface.
5. Transient Voltage Suppressor according to claim 1, wherein, the Transient Voltage Suppressor further includes：
Insulating layer, positioned at the upper surface of second epitaxial layer, and first part in first well region, second well region
Corresponding position be equipped with contact hole；
The first part of first well region and the second well region are electrically connected with described in extraction by contact conductor by the contact hole
First electrode.
6. Transient Voltage Suppressor according to claim 1, wherein, the first surface of the Semiconductor substrate is grown in advance
There is the first epitaxial layer of the first doping type, first epitaxial layer is as sacrificial layer.
7. Transient Voltage Suppressor according to claim 6, wherein, the resistivity of the Semiconductor substrate is less than 0.02
Ω cm, the resistivity of first epitaxial layer are not less than 0.1 Ω cm.
8. Transient Voltage Suppressor according to claim 6, wherein, the doping concentration of second epitaxial layer is less than described
The doping concentration of first epitaxial layer.
9. Transient Voltage Suppressor according to claim 6, wherein, the thickness of first epitaxial layer is not less than 3 μm, institute
The thickness for stating the second epitaxial layer is not less than 5 μm.
10. Transient Voltage Suppressor according to claim 1, wherein, the implantation dosage of first buried layer is not less than
E14cm-2The order of magnitude, the doping concentration of second buried layer are not less than E19cm-3The order of magnitude, the doping of first isolated area are dense
Degree is not less than E18cm-3The order of magnitude, the doping concentration of second isolated area are not less than E18cm-3The order of magnitude, first well region
Doping concentration be not less than E19cm-3The order of magnitude, the implantation dosage of second well region are not less than E14cm-2The order of magnitude.
11. Transient Voltage Suppressor according to claim 1, wherein, first doping type is N-type or p-type, described
Second doping type is another in N-type or p-type.
12. a kind of manufacturing method of Transient Voltage Suppressor, wherein, including：
Semiconductor substrate is provided；
Form the first buried layer of the second doping type, first buried layer is from the first surface of the Semiconductor substrate to described half
Extend in conductor substrate, first buried layer includes first part and second part；
The second buried layer of the first doping type is formed, second buried layer includes first part and second part, and described second buries
The first part of layer extends from the first surface of the Semiconductor substrate into the Semiconductor substrate, and the of second buried layer
Two parts extend from the first part of first buried layer into first buried layer；
The second epitaxial layer of the first doping type is formed on the first surface of the Semiconductor substrate of the first doping type；
Form the first isolated area of the second doping type, first isolated area is from the upper table of second epitaxial layer towards described
Extend in second epitaxial layer, a part for first isolated area is connected with the first part of first buried layer with described the
The first isolated island, the second part phase of another part of first isolated area and first buried layer are limited in two epitaxial layers
Connect to limit the second isolated island in second epitaxial layer；
Form the second isolated area of the first doping type, second isolated area is from the upper table of second epitaxial layer towards described
Extend in second epitaxial layer, a part for second isolated area is connected with the second part of second buried layer with described the
The third isolated island of second epitaxial layer, another part of second isolated area and described second are limited in one isolated island
The first part of buried layer is connected；
The first well region of the second doping type is formed, first well region includes first part and second part, first trap
The first part in area from the upper table of second epitaxial layer towards the third isolated island in extend, the second of first well region
Part from the upper table of second epitaxial layer towards second epitaxial layer in extend and by first isolated area will described in
The second part of the first part of first buried layer and first buried layer is electrically connected, the second part of first well region with it is described
The second part contact of second isolated area；And
The second well region of the first doping type is formed, second isolated island is extended to from the upper surface of second epitaxial layer
Interior, the first part of second well region and first well region is electrically connected；
Draw first well region first part and second well region using as the first electrode；And
The Semiconductor substrate is drawn using as second electrode.
13. the manufacturing method of Transient Voltage Suppressor according to claim 12, wherein, first of second buried layer
Divide and be formed between first part and the second part of first buried layer.
14. the manufacturing method of Transient Voltage Suppressor according to claim 12, wherein, second isolated area is from described
The upper table of second epitaxial layer is towards extending in second epitaxial layer, second of second isolated area and second buried layer
The step of limiting the third isolated island of second epitaxial layer in first isolated island is divided to include：
Second isolated area is along the contact surface between first isolated island and first isolated area from second extension
The upper table of layer is towards extension in second epitaxial layer to form the third isolated island.
15. the manufacturing method of Transient Voltage Suppressor according to claim 12, wherein, draw the Semiconductor substrate with
Include as the step of second electrode：
Metal layer, the first surface of the Semiconductor substrate and described the are formed in the second surface of the Semiconductor substrate
Two surfaces are relative to each other.
16. the manufacturing method of Transient Voltage Suppressor according to claim 15, wherein, the of the Semiconductor substrate
Before the step of two forming metal layer on surface, further include：
The Semiconductor substrate is thinned from the second surface of the Semiconductor substrate.
17. the manufacturing method of Transient Voltage Suppressor according to claim 12, wherein, draw the of first well region
A part of and described second well region as the step of first electrode to include：
Insulating layer is formed in the upper surface of second epitaxial layer；
In the corresponding position of the first part and second well region of the insulating layer and first well region, contact hole is set；
And
The first part of first well region and second well region are electrically connected to draw described first by the contact hole
Electrode.
18. the manufacturing method of Transient Voltage Suppressor according to claim 12, wherein, the Semiconductor substrate is provided
Step includes：
In the first epitaxial layer of advance one doping type of growth regulation of the first surface of the Semiconductor substrate, first epitaxial layer
As sacrificial layer.
19. the manufacturing method of Transient Voltage Suppressor according to claim 18, wherein, the doping of second epitaxial layer
Concentration is less than the doping concentration of first epitaxial layer.
20. the manufacturing method of Transient Voltage Suppressor according to claim 12, wherein, first doping type is N
Type or p-type, second doping type are another in N-type or p-type.
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