EP3454366B1 - Method for manufacturing a semiconductor structure with buried power rail - Google Patents

Method for manufacturing a semiconductor structure with buried power rail Download PDF

Info

Publication number
EP3454366B1
EP3454366B1 EP18191242.9A EP18191242A EP3454366B1 EP 3454366 B1 EP3454366 B1 EP 3454366B1 EP 18191242 A EP18191242 A EP 18191242A EP 3454366 B1 EP3454366 B1 EP 3454366B1
Authority
EP
European Patent Office
Prior art keywords
region
power rail
source
well region
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP18191242.9A
Other languages
German (de)
French (fr)
Other versions
EP3454366A1 (en
Inventor
Po-Chao Tsao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of EP3454366A1 publication Critical patent/EP3454366A1/en
Application granted granted Critical
Publication of EP3454366B1 publication Critical patent/EP3454366B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Definitions

  • the invention relates to a method for manufacturing a semiconductor structure with a power rail, more particularly a power rail embedded in a shallow trench isolation (STI) region.
  • a power rail more particularly a power rail embedded in a shallow trench isolation (STI) region.
  • STI shallow trench isolation
  • Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
  • EP 3 324 436 A1 relates to an integrated circuit chip with power delivery network on the backside of the chip. In an IC according to this reference, power and ground rails are incorporated in the front end of line (FEOL).
  • FEOL front end of line
  • power and ground rails are embedded in a trench etched into an STI region between two rows of fins.
  • the power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip.
  • the connection from the buried interconnects to the source and drain areas is established by so-called 'local interconnects'.
  • These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced.
  • the power delivery network of the IC is located in its entirety on the backside of the chip.
  • US 2018 151 494 A1 relates to a semiconductor device having a buried metal line and discloses a device that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines.
  • the first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell.
  • the pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply.
  • the pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
  • US 2018 151 494 A1 also discloses forming a power rail embedded in a trench etched into an STI region.
  • the invention provides a method according to claim 1. Embodiments are defined in the dependent claims.
  • a semiconductor structure which is not claimed but which can be a product of the claimed method comprises a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail.
  • Each of the transistors comprises at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin.
  • the fin is formed on the well region, and is extending in a first direction.
  • the gate electrode is extending in a second direction that is perpendicular to the first direction.
  • the power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction.
  • Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor.
  • the power rail is electrically connected to the well region of the substrate.
  • Each of the cells comprises at least one PMOS transistor formed over the N-type well region, and at least one NMOS transistor formed over the P-type well region.
  • the PMOS transistor is separated from the NMOS transistor by the STI region and the ILD layer.
  • the VDD line is formed in the STI region over the N-type well region and under the ILD layer, and is electrically connected to a source region of the PMOS transistor.
  • the VSS line is formed in the STI region over the P-type well region and under the ILD layer, and is electrically connected to a source region of the PMOS transistor.
  • FIGs. 1A-1E and 2 The following description is directed, in FIGs. 1A-1E and 2 , to a semiconductor structure which is not claimed but which can be manufactured according to the claimed method.
  • the description is further directed, with reference to FIGs. 3A-3H , to the best-contemplated mode of carrying out the invention.
  • This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense.
  • the scope of the invention is determined by the appended claims.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • FIGs. 1A-1E show block diagrams of a layout of features of a semiconductor structure 100 comprising one or more cells in an integrated circuit (IC).
  • FIGs. 1A through 1E illustrate features in different levels of the cells, which are consecutively described for clarity.
  • the cells may be the standard cells or the memory cells (e.g., SRAM cells) in the IC.
  • a P-type well region 15_1 is disposed at the middle of semiconductor structure 100, and two N-type well regions 10_1 and 10_2 are on opposite sides of P-type well region 15_1.
  • the fins 20_1 and 20_2 are formed on the N-type well region 10_1, the fins 20_3 through 20_6 are formed on the P-type well region 15_1, and the fins 20_7 and 20_8 are formed on the N-type well region 10_2.
  • the fins 20_1 through 20_8 are parallel with the X-direction.
  • the gate electrodes 30_1 through 30_17 are arranged parallel with the Y-direction, and the Y-direction is perpendicular to the X-direction.
  • the gate electrodes 30_1 through 30_6 form a plurality of PMOS transistors P1 through P6 with the underlying fins 20_1 and 20_2 over the N-type well region 10_1.
  • the gate electrodes 30_2, 30_4 and 30_7 through 30_9 form a plurality of NMOS transistors N1 through N6 with the underlying fins 20_3 and 20_4 over the P-type well region 15_1, and the gate electrodes 30_10 through 30_15 form a plurality of NMOS transistors N7 through N12 with the underlying fins 20_5 and 20_6 over the P-type well region 15_1.
  • the gate electrodes 30_10 through 30_12, 30_14, 30_16 and 30_17 form a plurality of PMOS transistors P7 through P12 with the underlying fins 20_7 and 20_8 over the N-type well region 10_2.
  • the PMOS transistors P1 through P12 and the NMOS transistor N1 through N12 are the dual-fin field effect transistors (FETs). In other examples, the PMOS transistors P1 through P12 and the NMOS transistor N1 through N12 are single-fin FETs.
  • the number of fins under the gate electrodes 30_1 through 30_17 may be the same or different.
  • each gate electrode is capable of connecting to an overlying level through the respective gate contact (also referred to as contact plug) in the IC.
  • the gate electrode 30_2 is shared by the PMOS transistor P2 and the NMOS transistor N2.
  • the gate electrode 30_4 is shared by the PMOS transistor P4 and the NMOS transistor N4.
  • the gate electrode 30_6 is shared by the PMOS transistor P6 and the NMOS transistor N6.
  • the gate electrode 30_10 is shared by the PMOS transistor P7 and the NMOS transistor N7.
  • the gate electrode 30_11 is shared by the PMOS transistor P8 and the NMOS transistor N8.
  • the gate electrode 30_12 is shared by the PMOS transistor P9 and the NMOS transistor N9.
  • the gate electrode 30_14 is shared by the PMOS transistor P11 and the NMOS transistor N11.
  • the power rails 40_1 through 40_3 are arranged parallel with the X-direction, and formed in the front end of line (FEOL) process of IC fabrication.
  • the power rails 40_1 through 40_3 are buried power rails that are embedded in shallow trench isolation (STI) region.
  • the power rail 40_1 is formed over the N-type well region 10_1, and is configured to electrically connect a positive power supply line (e.g., a VDD line).
  • the power rail 40_3 is formed over the N-type well region 10_2, and is configured to electrically connect a positive power supply line (e.g., a VDD line).
  • the power rail 40_2 is formed over the P-type well region 15_1, and is configured to electrically connect a grounding line (e.g., a VSS line).
  • the source/drain contacts 50_1 through 50_22 are arranged parallel with the Y-direction. Each source/drain contact is disposed between two adjacent gate electrodes. Furthermore, each source/drain contact (also referred to as "contact") is capable of connecting the source/drain region of corresponding transistor to the overlying level. For example, the source/drain contact 50_1 is disposed between the gate electrodes 30_1 and 30_2, and the source/drain contact 50_2 is disposed between the gate electrodes 30_2 and 30_3. Thus, the gate electrode 30_2 is disposed between the source/drain contacts 50_1 and 50_2. Therefore, the gate region of the PMOS transistor P2 is coupled to the gate electrode 30_2, and the source region and the drain region are coupled to the source/drain contacts 50_1 and 50_2, respectively.
  • the source/drain contacts 50_1 and 50_4 are extending above the power rail 40_1 and connecting down to the power rail 40_1 through the lower extension contact 55, thus the source regions of the PMOS transistors P1, P2, P4 and P5 are coupled to the positive power supply line (e.g., a VDD line) through the power rail 40_1 and the corresponding source/drain contact.
  • the source region of the PMOS transistor P1 is coupled to the power rail 40_1 through the source/drain contact 50_1.
  • the source/drain contacts 50_18, 50_20 and 50_22 are extending above the power rail 40_3 and connecting down to the power rail 40_3 through the lower extension contact 55, thus the source regions of the PMOS transistors P8 through P12 are coupled to the positive power supply line (e.g., a VDD line) through the power rail 40_3 and the corresponding source/drain contact.
  • the positive power supply line e.g., a VDD line
  • the source/drain contacts 50_7 and 50_10 are extending to cross the power rail 40_2 and connecting down to the power rail 40_2 through the lower extension contact 55, thus the source regions of the NMOS transistors N1, N2, N4, N5, N7, N8, N10 and N11 are coupled to a grounding line (e.g., a VSS line) through the power rail 40_2 and the corresponding source/drain contact.
  • a grounding line e.g., a VSS line
  • the source region of the NMOS transistor N11 is coupled to the power rail 40_2 through the source/drain contact 50_10.
  • the conductive lines 60_1 through 60_6 are arranged parallel with the X-direction. In order to simplify the description, only the conductive lines 60_1 through 60_6 are shown in FIG. 1E , and other conductive lines are omitted.
  • the conductive line 60_1 is disposed over the power rail 40_1, and the conductive line 60_1 is coupled to the power rail 40_1 through the vias 65_1 and 65_2 and the corresponding source/drain contacts 50_1 and 50_4. Furthermore, the vias 65_1 and 65_2 are disposed over the lower extension contacts 55.
  • the via 65_3 is connected between the gate electrode 30_1 and the conductive line 60_2, which is used to electrically connected the gate region of the PMOS transistor P1 to the conductive line 60_2.
  • the via 65_4 is connected between the gate electrode 30_2 and the conductive line 60_3, which is used to electrically connect the gate region of the PMOS transistor P1 and the NMOS transistor N2 to the conductive line 60_3.
  • the via 65_5 is connected between the source/drain contact 50_8 and the conductive line 60_4, which is used to electrically connected the drain region of the NMOS transistor N2 to the conductive line 60_4.
  • the conductive line 60_5 is disposed over the power rail 40_2, and the conductive line 60_5 is coupled to the power rail 40_2 through the vias 65_6 and 65_7 and the corresponding source/drain contacts 50_7 and 50_10. Furthermore, the vias 65_6 and 65_7 are disposed over the lower extension contacts 55.
  • the conductive line 60_6 is disposed over the power rail 40_3, and the conductive line 60_6 is electrically connected to the power rail 40_3 through the via 65_8 and the corresponding source/drain contact 50_20. Furthermore, the via 65_8 is disposed over one of the lower extension contacts 55 on the power rail 40_3. In the example shown, only the via 65_8 is used to connect the conductive line 60_6 to the power rail 40_3. However, the source/drain contacts 50_18 and 50_22 are connected to the power rail 40_3 through the corresponding lower extension contacts 55. Thus, the source/drain contacts 50_18 and 50_22 are also electrically connected to the conductive line 60_6.
  • the conductive line 60_6 and 60_1 are coupled together through the upper conductive lines and the vias between the upper conductive lines over the conductive line 60_6 and 60_1. Due to no via and no conductive line are arranged over the source/drain contacts 50_18 and 50_22, the area over the source/drain contacts 50_18 and 50_22 can be used to provide additional routing area for the signals different from the power lines (e.g., VDD line or VSS line), thereby decreasing layout complexity.
  • the power lines e.g., VDD line or VSS line
  • FIG. 2 shows a cross-sectional view of the semiconductor structure 100 along section line AA-A of FIG. 1E .
  • the N-type well region 10_1 and the P-type well region 15_1 are formed on a substrate 210.
  • the substrate 210 can be a Si substrate.
  • the fins 20_3 and 20_4 are formed on the P-type well region 15_1.
  • the fins 20_3 and 20_4 include an appropriate concentration of P-type dopants (e.g., boron (such as 11B), boron, boron fluorine (BF2), or a combination thereof).
  • the fins 20_1 and 20_2 are formed on the N-type well region 10_1.
  • the fins 20_1 and 20_2 include an appropriate concentration of n-type dopants (e.g., phosphorous (such as 31P), arsenic, or a combination thereof).
  • n-type dopants e.g., phosphorous (such as 31P), arsenic, or a combination thereof.
  • the fins 20_1 through 20_4 are separated from each other by the shallow trench isolation (STI) region 220.
  • STI shallow trench isolation
  • the power rail 40_1 is formed on the N-type well region 10_1, and the power rail 40_2 is formed on the P-type well region 15_1.
  • the power rails 40_1 and 40_2 are separated from the fins 20_1 through 20_4 by the STI region 220. Furthermore, the power rails 40_1 and 40_2 are separated from the STI region 220, the N-type well region 10_1 and the P-type well region 15_1 by the barrier layer 45.
  • Inter-Layer Dielectric (ILD) layer 230 is formed over the STI region 220.
  • the ILD layer 230 may be formed of an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like.
  • PSG Phospho-Silicate Glass
  • BSG Boro-Silicate Glass
  • BPSG Boron-Doped Phospho-Silicate Glass
  • TEOS Tetra Ethyl Ortho Silicate
  • the P-type doping regions 25_1 and 25_2 form the source/drain regions on the fins 20_1 and 20_2
  • the N-type doping regions 27_1 and 27_2 form the source/drain regions on the fins 20_3 and 20_4.
  • the material of the N-type doping regions 27_1 and 27_2 includes epitaxy profile.
  • the epitaxy material is selected from a group consisting of SiP content, SiC content, SiPC, SiAs, Si, or combination. Furthermore, the material of the P-type doping regions 25_1 and 25_2 includes epitaxy profile. The epitaxy material is selected from a group consisting of SiGe content, SiGeC content, Gecontent, or combination.
  • the source/drain contact 50_1 is formed around the P-type doping regions 25_1 and 25_2 corresponding to the fins 20_1 and 20_2.
  • the source/drain contact 50_1 is electrically connected to the power rail 40_1 through the lower extension contact 55.
  • the source/drain contact 50_7 is formed around the N-type doping regions 27_1 and 27_2 corresponding to the fins 20_3 and 20_4.
  • the source/drain contact 50_1 is formed over the P-type doping regions 25_1 and 25_2, and the source/drain contact 50_7 is formed over the N-type doping regions 27_1 and 27_2.
  • the source/drain contact 50_7 is electrically connected to the power rail 40_2 through the lower extension contact 55.
  • the source/drain contacts 50_1 and 50_7 and the corresponding lower extension contacts 55 are separated from the ILD layer 230 and STI region 220 by the blocking layer 235. It should be noted that the N-type doping regions 27_1 and 27_2 and the P-type doping regions 25_1 and 25_2 are formed in the ILD layer 230, and the power rails 40_1 and 40_2 are formed in the STI region 220. Thus, the power rails 40_1 and 40_2 are disposed below the N-type doping regions 27_1 and 27_2 and the P-type doping regions 25_1 and 25_2.
  • Inter-metallization dielectric (IMD) layer 240 is formed over the ILD layer 230.
  • the vias 65_1 and 65_6 and the conductive lines 60_1 through 60_5 are formed in the IMD layer 240.
  • the conductive lines 60_1 through 60_5 are metal lines.
  • the source/drain contact 50_1 is electrically connected to the conductive line 60_1 through the via 65_1, thus the conductive line 60_1 over the power rail 40_1 is electrically connected to the power rail 40_1.
  • the source/drain contact 50_7 is electrically connected to the conductive line 60_5 through the via 65_6, thus the conductive line 60_5 over the power rail 40_2 is electrically connected to the power rail 40_2.
  • FIGs. 3A-3H show cross-sectional representations of various stages of forming a semiconductor structure according to an embodiment of the invention.
  • a substrate 210 is provided.
  • the substrate 102 may be made of silicon or other semiconductor materials.
  • the substrate 102 is a wafer.
  • the N-type well region 10_1 and the P-type well region 15_1 are formed on the substrate 210.
  • the N-type well region 10_1 may be doped with n-type dopants, such as phosphorus (P) or arsenic (As), and the P-type well region 15_1 may be doped with p-type dopants, such as boron or BF2.
  • a plurality of fins 20 and a plurality of dummy fins 20D are formed over the N-type well region 10_1 and the P-type well region 15_1. Furthermore, the STI region 220 is formed over the N-type well region 10_1 and the P-type well region 15_1.
  • the STI region 220 is an isolation structure that is used to define and electrically isolate the fins 20 and the dummy fins 20D. It should be noted that the dummy fin 20D is wider than the fin 20, i.e., W2>W1. Furthermore, each fin 20 is used to form a transistor in the semiconductor structure, and each dummy fin 20D is used to form a power rail embedded in the STI region 220.
  • an ILD planarization is completed on the semiconductor structure.
  • the P-type doping regions 25 are formed on the fins 20 over the N-type well region 10_1.
  • the N-type doping regions 27 are formed on the fins 20 over the P-type well region 15_1.
  • the ILD layer 230 is formed over the STI region 220.
  • a spacer 237 is formed between the dummy fin 20D and the ILD layer 230.
  • a plurality of openings 250 of the ILD layer 230 are formed above the dummy fins 20D. Furthermore, the spacer 237 and the ILD layer 230 over each dummy fin 20D are removed.
  • a wet etching process is performed on the semiconductor structure, so as to remove the dummy fins 20D over the N-type well region 10_1 and the P-type well region 15_1 through the openings 250.
  • the trenches 255 are formed over the N-type well region 10_1 and the P-type well region 15_1.
  • the barrier layer 45 and the conducting layer 40 are filled up the trenches 255.
  • the barrier layer 45 protects the underlying N-type well region 10_1 and P-type well region 15_1 from contacting the conducting material of the conducting layer 40 when the conducting layer 40 is later formed.
  • a chemical-mechanical planarization (CMP) is performed on the conducting layer 40, and then the conducting layer 40 in the trench 255 is recessed to a specific height.
  • CMP chemical-mechanical planarization
  • the remaining conducting layer 40 in the trench 255 forms the power rail (e.g., 40_1 and 40_2 of FIG. 2 ) in the STI region 220.
  • the specific height of the power rail 40 is less than that of the fins 20. In some embodiments, the specific height of the power rail 40 is below the P-type doping regions 25_1 and 25_2 and the N-type doping regions 27_1 and 27_2.
  • a deposition process is performed to form the hard mask 260 over the power rail 40.
  • the subsequent processes before a middle-of-line (MoL) process are performed.
  • a replacement metal gate (RMG) is performed on the gate electrodes of the semiconductor structure.
  • the source/drain contacts 50a/50b are formed around the P-type doping regions 25 and the N-type doping regions 27.
  • each source/drain contact 50a/50b is coupled to the source/drain region of a transistor comprising a dual-fin structure.
  • each source/drain contact 50a is connecting down to the adjacent power rail 40 through the corresponding lower extension contact 55.
  • the source/drain contact 50a is configured to connect the source region of the PMOS transistor M1 (i.e., the P-type doping region 25 on the right).
  • the source region of the PMOS transistor M1 is electrically connected to the power rail 40 over the N-type well region 10_1 through the source/drain contact 50a and the corresponding lower extension contact 55. Furthermore, the N-type well region 10_1 is also electrically connected to the power rail 40. In some embodiments, the power rail 40 over the N-type well region 10_1 and the N-type well region 10_1 are coupled to the positive power supply line (e.g., a VDD line). Similarity, for the NMOS transistor M2 over the P-type well region 15_1, the source/drain contact 50a is configured to connect the source region of the NMOS transistor M2.
  • the source region of the NMOS transistor M2 is electrically connected to the power rail 40 over the P-type well region 15_1 through the source/drain contact 50a and the corresponding lower extension contact 55.
  • the P-type well region 15_1 is also electrically connected to the power rail 40.
  • the power rail 40 over the P-type well region 15_1 and the P-type well region 15_1 are coupled to a grounding line (e.g., a VSS line).

Description

    BACKGROUND OF THE INVENTION Field of the Invention
  • The invention relates to a method for manufacturing a semiconductor structure with a power rail, more particularly a power rail embedded in a shallow trench isolation (STI) region.
    • Description of the Related Art
  • Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
  • The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node. With the increased demands for miniaturization, higher speed, greater bandwidth, lower power consumption, and lower latency, chip layout has become more complicated and difficult to achieve in the production of semiconductor dies. For example, the routing area has decreased.
    EP 3 324 436 A1 relates to an integrated circuit chip with power delivery network on the backside of the chip. In an IC according to this reference, power and ground rails are incorporated in the front end of line (FEOL). These power and ground rails are embedded in a trench etched into an STI region between two rows of fins. The power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by so-called 'local interconnects'. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. Further, the power delivery network of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled vias of the type known as 'through-semiconductor vias' or 'through silicon vias' (TSV).
    US 2018 151 494 A1 relates to a semiconductor device having a buried metal line and discloses a device that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively. US 2018 151 494 A1 also discloses forming a power rail embedded in a trench etched into an STI region.
    • BRIEF SUMMARY OF THE INVENTION
  • The invention provides a method according to claim 1. Embodiments are defined in the dependent claims.
  • A semiconductor structure which is not claimed but which can be a product of the claimed method comprises a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors comprises at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.
  • An integrated circuit which is not claimed but which can be a product of the claimed method comprises a substrate, an N-type well region on the substrate, a P-type well region on the substrate, a shallow trench isolation (STI) region on the P-type well region and the N-type well region, an interlayer dielectric (ILD) layer over the STI region, a plurality of cells, a VDD line and a VSS line. Each of the cells comprises at least one PMOS transistor formed over the N-type well region, and at least one NMOS transistor formed over the P-type well region. The PMOS transistor is separated from the NMOS transistor by the STI region and the ILD layer. The VDD line is formed in the STI region over the N-type well region and under the ILD layer, and is electrically connected to a source region of the PMOS transistor. The VSS line is formed in the STI region over the P-type well region and under the ILD layer, and is electrically connected to a source region of the PMOS transistor.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
    • FIGs. 1A-1E show block diagrams of a layout of features of a semiconductor structure comprising one or more cells in an integrated circuit (IC) which can be manufactured according to an embodiment of the invention;
    • FIG. 2 shows a cross-sectional view of the semiconductor structure along section line AA-A of FIG. 1E which can be manufactured according to an embodiment of the invention; and
    • FIGs. 3A-3H show cross-sectional representations of various stages of forming a semiconductor structure according to an embodiment of the invention.
    DETAILED DESCRIPTION OF THE INVENTION
  • The following description is directed, in FIGs. 1A-1E and 2, to a semiconductor structure which is not claimed but which can be manufactured according to the claimed method. The description is further directed, with reference to FIGs. 3A-3H, to the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by the appended claims.
  • Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
  • Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • FIGs. 1A-1E show block diagrams of a layout of features of a semiconductor structure 100 comprising one or more cells in an integrated circuit (IC). FIGs. 1A through 1E illustrate features in different levels of the cells, which are consecutively described for clarity. In some examples, the cells may be the standard cells or the memory cells (e.g., SRAM cells) in the IC.
  • In FIG. 1A, a P-type well region 15_1 is disposed at the middle of semiconductor structure 100, and two N-type well regions 10_1 and 10_2 are on opposite sides of P-type well region 15_1. The fins 20_1 and 20_2 are formed on the N-type well region 10_1, the fins 20_3 through 20_6 are formed on the P-type well region 15_1, and the fins 20_7 and 20_8 are formed on the N-type well region 10_2. The fins 20_1 through 20_8 are parallel with the X-direction.
  • In FIG. 1B, the gate electrodes 30_1 through 30_17 are arranged parallel with the Y-direction, and the Y-direction is perpendicular to the X-direction. The gate electrodes 30_1 through 30_6 form a plurality of PMOS transistors P1 through P6 with the underlying fins 20_1 and 20_2 over the N-type well region 10_1. Furthermore, the gate electrodes 30_2, 30_4 and 30_7 through 30_9 form a plurality of NMOS transistors N1 through N6 with the underlying fins 20_3 and 20_4 over the P-type well region 15_1, and the gate electrodes 30_10 through 30_15 form a plurality of NMOS transistors N7 through N12 with the underlying fins 20_5 and 20_6 over the P-type well region 15_1. Moreover, the gate electrodes 30_10 through 30_12, 30_14, 30_16 and 30_17 form a plurality of PMOS transistors P7 through P12 with the underlying fins 20_7 and 20_8 over the N-type well region 10_2. Here, the PMOS transistors P1 through P12 and the NMOS transistor N1 through N12 are the dual-fin field effect transistors (FETs). In other examples, the PMOS transistors P1 through P12 and the NMOS transistor N1 through N12 are single-fin FETs. The number of fins under the gate electrodes 30_1 through 30_17 may be the same or different. Furthermore, each gate electrode is capable of connecting to an overlying level through the respective gate contact (also referred to as contact plug) in the IC.
  • In FIG. 1B, the gate electrode 30_2 is shared by the PMOS transistor P2 and the NMOS transistor N2. The gate electrode 30_4 is shared by the PMOS transistor P4 and the NMOS transistor N4. The gate electrode 30_6 is shared by the PMOS transistor P6 and the NMOS transistor N6. The gate electrode 30_10 is shared by the PMOS transistor P7 and the NMOS transistor N7. The gate electrode 30_11 is shared by the PMOS transistor P8 and the NMOS transistor N8. The gate electrode 30_12 is shared by the PMOS transistor P9 and the NMOS transistor N9. The gate electrode 30_14 is shared by the PMOS transistor P11 and the NMOS transistor N11.
  • In FIG. 1C, the power rails 40_1 through 40_3 are arranged parallel with the X-direction, and formed in the front end of line (FEOL) process of IC fabrication. Compared with the traditional power rails formed by the metal layers that are formed in the back end of line (BEOL) process of IC fabrication, the power rails 40_1 through 40_3 are buried power rails that are embedded in shallow trench isolation (STI) region. The power rail 40_1 is formed over the N-type well region 10_1, and is configured to electrically connect a positive power supply line (e.g., a VDD line). Similarly, the power rail 40_3 is formed over the N-type well region 10_2, and is configured to electrically connect a positive power supply line (e.g., a VDD line). The power rail 40_2 is formed over the P-type well region 15_1, and is configured to electrically connect a grounding line (e.g., a VSS line).
  • In FIG. 1D, the source/drain contacts 50_1 through 50_22 are arranged parallel with the Y-direction. Each source/drain contact is disposed between two adjacent gate electrodes. Furthermore, each source/drain contact (also referred to as "contact") is capable of connecting the source/drain region of corresponding transistor to the overlying level. For example, the source/drain contact 50_1 is disposed between the gate electrodes 30_1 and 30_2, and the source/drain contact 50_2 is disposed between the gate electrodes 30_2 and 30_3. Thus, the gate electrode 30_2 is disposed between the source/drain contacts 50_1 and 50_2. Therefore, the gate region of the PMOS transistor P2 is coupled to the gate electrode 30_2, and the source region and the drain region are coupled to the source/drain contacts 50_1 and 50_2, respectively.
  • In FIG. 1D, the source/drain contacts 50_1 and 50_4 are extending above the power rail 40_1 and connecting down to the power rail 40_1 through the lower extension contact 55, thus the source regions of the PMOS transistors P1, P2, P4 and P5 are coupled to the positive power supply line (e.g., a VDD line) through the power rail 40_1 and the corresponding source/drain contact. For example, for the PMOS transistor P1, the source region of the PMOS transistor P1 is coupled to the power rail 40_1 through the source/drain contact 50_1. Similarly, the source/drain contacts 50_18, 50_20 and 50_22 are extending above the power rail 40_3 and connecting down to the power rail 40_3 through the lower extension contact 55, thus the source regions of the PMOS transistors P8 through P12 are coupled to the positive power supply line (e.g., a VDD line) through the power rail 40_3 and the corresponding source/drain contact. Furthermore, the source/drain contacts 50_7 and 50_10 are extending to cross the power rail 40_2 and connecting down to the power rail 40_2 through the lower extension contact 55, thus the source regions of the NMOS transistors N1, N2, N4, N5, N7, N8, N10 and N11 are coupled to a grounding line (e.g., a VSS line) through the power rail 40_2 and the corresponding source/drain contact. For example, for the NMOS transistor N11, the source region of the NMOS transistor N11 is coupled to the power rail 40_2 through the source/drain contact 50_10.
  • In FIG. 1E, the conductive lines 60_1 through 60_6 are arranged parallel with the X-direction. In order to simplify the description, only the conductive lines 60_1 through 60_6 are shown in FIG. 1E, and other conductive lines are omitted. The conductive line 60_1 is disposed over the power rail 40_1, and the conductive line 60_1 is coupled to the power rail 40_1 through the vias 65_1 and 65_2 and the corresponding source/drain contacts 50_1 and 50_4. Furthermore, the vias 65_1 and 65_2 are disposed over the lower extension contacts 55. The via 65_3 is connected between the gate electrode 30_1 and the conductive line 60_2, which is used to electrically connected the gate region of the PMOS transistor P1 to the conductive line 60_2. The via 65_4 is connected between the gate electrode 30_2 and the conductive line 60_3, which is used to electrically connect the gate region of the PMOS transistor P1 and the NMOS transistor N2 to the conductive line 60_3. The via 65_5 is connected between the source/drain contact 50_8 and the conductive line 60_4, which is used to electrically connected the drain region of the NMOS transistor N2 to the conductive line 60_4. The conductive line 60_5 is disposed over the power rail 40_2, and the conductive line 60_5 is coupled to the power rail 40_2 through the vias 65_6 and 65_7 and the corresponding source/drain contacts 50_7 and 50_10. Furthermore, the vias 65_6 and 65_7 are disposed over the lower extension contacts 55.
  • In FIG. 1E, the conductive line 60_6 is disposed over the power rail 40_3, and the conductive line 60_6 is electrically connected to the power rail 40_3 through the via 65_8 and the corresponding source/drain contact 50_20. Furthermore, the via 65_8 is disposed over one of the lower extension contacts 55 on the power rail 40_3. In the example shown, only the via 65_8 is used to connect the conductive line 60_6 to the power rail 40_3. However, the source/drain contacts 50_18 and 50_22 are connected to the power rail 40_3 through the corresponding lower extension contacts 55. Thus, the source/drain contacts 50_18 and 50_22 are also electrically connected to the conductive line 60_6. Furthermore, the conductive line 60_6 and 60_1 are coupled together through the upper conductive lines and the vias between the upper conductive lines over the conductive line 60_6 and 60_1. Due to no via and no conductive line are arranged over the source/drain contacts 50_18 and 50_22, the area over the source/drain contacts 50_18 and 50_22 can be used to provide additional routing area for the signals different from the power lines (e.g., VDD line or VSS line), thereby decreasing layout complexity.
  • FIG. 2 shows a cross-sectional view of the semiconductor structure 100 along section line AA-A of FIG. 1E. The N-type well region 10_1 and the P-type well region 15_1 are formed on a substrate 210. The substrate 210 can be a Si substrate. The fins 20_3 and 20_4 are formed on the P-type well region 15_1. In some examples, the fins 20_3 and 20_4 include an appropriate concentration of P-type dopants (e.g., boron (such as 11B), boron, boron fluorine (BF2), or a combination thereof). The fins 20_1 and 20_2 are formed on the N-type well region 10_1. In some examples, the fins 20_1 and 20_2 include an appropriate concentration of n-type dopants (e.g., phosphorous (such as 31P), arsenic, or a combination thereof). The fins 20_1 through 20_4 are separated from each other by the shallow trench isolation (STI) region 220.
  • The power rail 40_1 is formed on the N-type well region 10_1, and the power rail 40_2 is formed on the P-type well region 15_1. The power rails 40_1 and 40_2 are separated from the fins 20_1 through 20_4 by the STI region 220. Furthermore, the power rails 40_1 and 40_2 are separated from the STI region 220, the N-type well region 10_1 and the P-type well region 15_1 by the barrier layer 45.
  • Inter-Layer Dielectric (ILD) layer 230 is formed over the STI region 220. The ILD layer 230 may be formed of an oxide such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like. The P-type doping regions 25_1 and 25_2 form the source/drain regions on the fins 20_1 and 20_2, and the N-type doping regions 27_1 and 27_2 form the source/drain regions on the fins 20_3 and 20_4. In some examples, the material of the N-type doping regions 27_1 and 27_2 includes epitaxy profile. The epitaxy material is selected from a group consisting of SiP content, SiC content, SiPC, SiAs, Si, or combination. Furthermore, the material of the P-type doping regions 25_1 and 25_2 includes epitaxy profile. The epitaxy material is selected from a group consisting of SiGe content, SiGeC content, Gecontent, or combination.
  • The source/drain contact 50_1 is formed around the P-type doping regions 25_1 and 25_2 corresponding to the fins 20_1 and 20_2. The source/drain contact 50_1 is electrically connected to the power rail 40_1 through the lower extension contact 55. Similarly, the source/drain contact 50_7 is formed around the N-type doping regions 27_1 and 27_2 corresponding to the fins 20_3 and 20_4. In some examples, the source/drain contact 50_1 is formed over the P-type doping regions 25_1 and 25_2, and the source/drain contact 50_7 is formed over the N-type doping regions 27_1 and 27_2. The source/drain contact 50_7 is electrically connected to the power rail 40_2 through the lower extension contact 55. The source/drain contacts 50_1 and 50_7 and the corresponding lower extension contacts 55 are separated from the ILD layer 230 and STI region 220 by the blocking layer 235. It should be noted that the N-type doping regions 27_1 and 27_2 and the P-type doping regions 25_1 and 25_2 are formed in the ILD layer 230, and the power rails 40_1 and 40_2 are formed in the STI region 220. Thus, the power rails 40_1 and 40_2 are disposed below the N-type doping regions 27_1 and 27_2 and the P-type doping regions 25_1 and 25_2.
  • Inter-metallization dielectric (IMD) layer 240 is formed over the ILD layer 230. The vias 65_1 and 65_6 and the conductive lines 60_1 through 60_5 are formed in the IMD layer 240. In some examples, the conductive lines 60_1 through 60_5 are metal lines. The source/drain contact 50_1 is electrically connected to the conductive line 60_1 through the via 65_1, thus the conductive line 60_1 over the power rail 40_1 is electrically connected to the power rail 40_1. Similarity, the source/drain contact 50_7 is electrically connected to the conductive line 60_5 through the via 65_6, thus the conductive line 60_5 over the power rail 40_2 is electrically connected to the power rail 40_2.
  • Embodiments for a method for manufacturing the above-described semiconductor structure are provided in the following. FIGs. 3A-3H show cross-sectional representations of various stages of forming a semiconductor structure according to an embodiment of the invention.
  • Referring to FIG. 3A, a substrate 210 is provided. The substrate 102 may be made of silicon or other semiconductor materials. In some embodiments, the substrate 102 is a wafer. Next, the N-type well region 10_1 and the P-type well region 15_1 are formed on the substrate 210. In some embodiments, the N-type well region 10_1 may be doped with n-type dopants, such as phosphorus (P) or arsenic (As), and the P-type well region 15_1 may be doped with p-type dopants, such as boron or BF2. Next, a plurality of fins 20 and a plurality of dummy fins 20D are formed over the N-type well region 10_1 and the P-type well region 15_1. Furthermore, the STI region 220 is formed over the N-type well region 10_1 and the P-type well region 15_1. The STI region 220 is an isolation structure that is used to define and electrically isolate the fins 20 and the dummy fins 20D. It should be noted that the dummy fin 20D is wider than the fin 20, i.e., W2>W1. Furthermore, each fin 20 is used to form a transistor in the semiconductor structure, and each dummy fin 20D is used to form a power rail embedded in the STI region 220.
  • As shown in FIG. 3B, an ILD planarization is completed on the semiconductor structure. The P-type doping regions 25 are formed on the fins 20 over the N-type well region 10_1. Furthermore, the N-type doping regions 27 are formed on the fins 20 over the P-type well region 15_1. The ILD layer 230 is formed over the STI region 220. A spacer 237 is formed between the dummy fin 20D and the ILD layer 230.
  • In FIG. 3C, a plurality of openings 250 of the ILD layer 230 are formed above the dummy fins 20D. Furthermore, the spacer 237 and the ILD layer 230 over each dummy fin 20D are removed.
  • In FIG. 3D, a wet etching process is performed on the semiconductor structure, so as to remove the dummy fins 20D over the N-type well region 10_1 and the P-type well region 15_1 through the openings 250. Thus, the trenches 255 are formed over the N-type well region 10_1 and the P-type well region 15_1.
  • In FIG. 3E, the barrier layer 45 and the conducting layer 40 are filled up the trenches 255. The barrier layer 45 protects the underlying N-type well region 10_1 and P-type well region 15_1 from contacting the conducting material of the conducting layer 40 when the conducting layer 40 is later formed.
  • In FIG. 3F, a chemical-mechanical planarization (CMP) is performed on the conducting layer 40, and then the conducting layer 40 in the trench 255 is recessed to a specific height. Thus, the remaining conducting layer 40 in the trench 255 forms the power rail (e.g., 40_1 and 40_2 of FIG. 2) in the STI region 220. Furthermore, the specific height of the power rail 40 is less than that of the fins 20. In some embodiments, the specific height of the power rail 40 is below the P-type doping regions 25_1 and 25_2 and the N-type doping regions 27_1 and 27_2.
  • In FIG. 3G, a deposition process is performed to form the hard mask 260 over the power rail 40. Next, the subsequent processes before a middle-of-line (MoL) process are performed. For example, a replacement metal gate (RMG) is performed on the gate electrodes of the semiconductor structure.
  • In FIG. 3H, the source/drain contacts 50a/50b are formed around the P-type doping regions 25 and the N-type doping regions 27. In the embodiment, each source/drain contact 50a/50b is coupled to the source/drain region of a transistor comprising a dual-fin structure. In the embodiment, each source/drain contact 50a is connecting down to the adjacent power rail 40 through the corresponding lower extension contact 55. For example, for the PMOS transistor M1 over the N-type well region 10_1, the source/drain contact 50a is configured to connect the source region of the PMOS transistor M1 (i.e., the P-type doping region 25 on the right). Thus, the source region of the PMOS transistor M1 is electrically connected to the power rail 40 over the N-type well region 10_1 through the source/drain contact 50a and the corresponding lower extension contact 55. Furthermore, the N-type well region 10_1 is also electrically connected to the power rail 40. In some embodiments, the power rail 40 over the N-type well region 10_1 and the N-type well region 10_1 are coupled to the positive power supply line (e.g., a VDD line). Similarity, for the NMOS transistor M2 over the P-type well region 15_1, the source/drain contact 50a is configured to connect the source region of the NMOS transistor M2. Thus, the source region of the NMOS transistor M2 is electrically connected to the power rail 40 over the P-type well region 15_1 through the source/drain contact 50a and the corresponding lower extension contact 55. Furthermore, the P-type well region 15_1 is also electrically connected to the power rail 40. In some embodiments, the power rail 40 over the P-type well region 15_1 and the P-type well region 15_1 are coupled to a grounding line (e.g., a VSS line).

Claims (4)

  1. A method for manufacturing a semiconductor structure, comprising:
    providing a substrate;
    forming at least one fin (20) and at least one dummy fin (20D) over a well region (10_1, 15_1) on the substrate, wherein the fin and the dummy fin are parallel with a first direction, and the dummy fin is wider than the fin;
    forming a shallow trench isolation, STI, region (220) over the substrate, wherein the fin and the dummy fin are separated from each other by the STI;
    removing the dummy fin (20D) to form a trench (255) in the STI region; and
    filling the trench (255) with conducting material (40); and
    recessing the conducting material (40) to a specific height to form a power rail from the remaining conducting material (40).
  2. The method as claimed in claim 1, further comprising:
    forming a doping region (25, 27) on the fin (20),
    wherein the power rail (40) is disposed at a level below the doping region (25, 27).
  3. The method as claimed in claim 2, further comprising:
    forming a source contact (50a) extending from the doping region (25, 27) to the power rail (40),
    wherein the doping region is electrically connected to the power rail through the source contact.
  4. The method as claimed in one of claims 1 to 3, wherein the well region comprises a P-type well region (15_1), and the doping region comprises an N-type doping region (27), wherein the doping region forms a source region of an NMOS transistor corresponding to the fin (20); or wherein the well region comprises an N-type well region (10_1), and the doping region comprises a P-type doping region (25), wherein the doping region forms a source region of a PMOS transistor corresponding to the fin (20).
EP18191242.9A 2017-09-12 2018-08-28 Method for manufacturing a semiconductor structure with buried power rail Active EP3454366B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762557204P 2017-09-12 2017-09-12
US16/059,196 US11094594B2 (en) 2017-09-12 2018-08-09 Semiconductor structure with buried power rail, integrated circuit and method for manufacturing the semiconductor structure

Publications (2)

Publication Number Publication Date
EP3454366A1 EP3454366A1 (en) 2019-03-13
EP3454366B1 true EP3454366B1 (en) 2024-03-13

Family

ID=63490217

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18191242.9A Active EP3454366B1 (en) 2017-09-12 2018-08-28 Method for manufacturing a semiconductor structure with buried power rail

Country Status (4)

Country Link
US (2) US11094594B2 (en)
EP (1) EP3454366B1 (en)
CN (1) CN109599400B (en)
TW (1) TWI710132B (en)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700207B2 (en) * 2017-11-30 2020-06-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device integrating backside power grid and related integrated circuit and fabrication method
JP6934540B2 (en) * 2018-02-02 2021-09-15 東京エレクトロン株式会社 Manufacturing method of semiconductor devices
US11404423B2 (en) * 2018-04-19 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd Fin-based strap cell structure for improving memory performance
US10672665B2 (en) * 2018-09-28 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor device structure and method for forming the same
US11063041B2 (en) 2018-10-31 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device including a power supply line and method of forming the same
US11093684B2 (en) * 2018-10-31 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Power rail with non-linear edge
US11195797B2 (en) 2019-05-21 2021-12-07 Samsung Electronics Co., Ltd. Applications of buried power rails
US11233008B2 (en) 2019-06-19 2022-01-25 Samsung Electronics Co., Ltd. Method of manufacturing an integrated circuit with buried power rail
KR20210013447A (en) 2019-07-25 2021-02-04 삼성전자주식회사 Semiconductor device
US10950546B1 (en) 2019-09-17 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
US11114366B2 (en) * 2019-10-01 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with buried conductive line and method for forming the same
CN114503256A (en) * 2019-10-18 2022-05-13 株式会社索思未来 Semiconductor integrated circuit device having a plurality of semiconductor chips
EP3836196B1 (en) 2019-12-13 2023-04-26 Imec VZW Self-aligned contacts for nanosheet field effect transistor devices
EP3840054B1 (en) 2019-12-20 2023-07-05 Imec VZW Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices
US11145550B2 (en) * 2020-03-05 2021-10-12 International Business Machines Corporation Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor
US11600707B2 (en) * 2020-05-12 2023-03-07 Micron Technology, Inc. Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features
DE102021107950A1 (en) * 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENTS WITH DIFFERENT ARCHITECTURES AND SEMICONDUCTOR COMPONENTS MANUFACTURED THEREOF
WO2021259479A1 (en) * 2020-06-25 2021-12-30 Huawei Technologies Co., Ltd. Semiconductor device, semiconductor die, and method of manufacturing a semiconductor device
US11637069B2 (en) * 2020-08-31 2023-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with V2V rail and methods of making same
US11908910B2 (en) * 2020-10-27 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having embedded conductive line and method of fabricating thereof
US11521927B2 (en) 2020-11-10 2022-12-06 International Business Machines Corporation Buried power rail for scaled vertical transport field effect transistor
US11769728B2 (en) 2020-11-13 2023-09-26 Samsung Electronics Co., Ltd. Backside power distribution network semiconductor package and method of manufacturing the same
JPWO2022138324A1 (en) * 2020-12-25 2022-06-30
US11621332B2 (en) 2021-01-14 2023-04-04 International Business Machines Corporation Wraparound contact to a buried power rail
US20220310514A1 (en) * 2021-03-23 2022-09-29 Intel Corporation Integrated circuit structures with gate cuts above buried power rails
US20220336355A1 (en) * 2021-04-19 2022-10-20 Samsung Electronics Co., Ltd. Thermal budget enhanced buried power rail and method of manufacturing the same
US11810919B2 (en) * 2021-06-17 2023-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure with conductive via structure and method for forming the same
US20230009640A1 (en) * 2021-07-06 2023-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Backside power rail for physical failure analysis (pfa)
US11804436B2 (en) 2021-09-03 2023-10-31 International Business Machines Corporation Self-aligned buried power rail cap for semiconductor devices
US20230087690A1 (en) * 2021-09-20 2023-03-23 International Business Machines Corporation Semiconductor structures with power rail disposed under active gate
US20230154783A1 (en) * 2021-11-16 2023-05-18 International Business Machines Corporation Replacement buried power rail
US20230411292A1 (en) * 2022-06-17 2023-12-21 International Business Machines Corporation Multiple critical dimension power rail

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583045B1 (en) 2001-11-16 2003-06-24 Taiwan Semiconductor Manufacturing Company Chip design with power rails under transistors
JP2008153435A (en) * 2006-12-18 2008-07-03 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
US8980719B2 (en) * 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8890260B2 (en) * 2009-09-04 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Polysilicon design for replacement gate technology
US8293602B2 (en) * 2010-11-19 2012-10-23 Micron Technology, Inc. Method of fabricating a finFET having cross-hair cells
US8507957B2 (en) 2011-05-02 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layouts with power rails under bottom metal layer
US9515076B2 (en) * 2013-08-06 2016-12-06 Renesas Electronics Corporation Semiconductor integrated circuit device
US20150145041A1 (en) * 2013-11-22 2015-05-28 International Business Machines Corporation Substrate local interconnect integration with finfets
US9263340B2 (en) 2014-05-02 2016-02-16 Globalfoundries Inc. Methods for removing selected fins that are formed for finFET semiconductor devices
JP6449082B2 (en) * 2014-08-18 2019-01-09 ルネサスエレクトロニクス株式会社 Semiconductor device
EP3324436B1 (en) 2016-11-21 2020-08-05 IMEC vzw An integrated circuit chip with power delivery network on the backside of the chip
US10170413B2 (en) * 2016-11-28 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having buried metal line and fabrication method of the same
US10475692B2 (en) * 2017-04-07 2019-11-12 Globalfoundries Inc. Self aligned buried power rail
US10290635B2 (en) * 2017-07-26 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Buried interconnect conductor
US10446555B2 (en) * 2017-08-31 2019-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Buried metal track and methods forming same

Also Published As

Publication number Publication date
EP3454366A1 (en) 2019-03-13
US20190080969A1 (en) 2019-03-14
US20210335675A1 (en) 2021-10-28
TWI710132B (en) 2020-11-11
CN109599400B (en) 2021-06-08
CN109599400A (en) 2019-04-09
TW201914011A (en) 2019-04-01
US11094594B2 (en) 2021-08-17

Similar Documents

Publication Publication Date Title
EP3454366B1 (en) Method for manufacturing a semiconductor structure with buried power rail
US9646973B2 (en) Dual-port SRAM cell structure with vertical devices
US7193262B2 (en) Low-cost deep trench decoupling capacitor device and process of manufacture
US7176125B2 (en) Method of forming a static random access memory with a buried local interconnect
CN102820280B (en) For the overstepping one's bounds laminar metal level of integrated circuit
CN111801798B (en) Three-dimensional memory device
TW202042319A (en) Replacement buried power rail in backside power delivery
US11616077B2 (en) 3D NAND memory device and method of forming the same
CN111801799B (en) Method for forming three-dimensional memory device
US11735498B2 (en) Through via electrode and device isolation structure including oxide layer pattern and nitride layer pattern sequentially stacked on inner surface of trench
CN111801800B (en) Three-dimensional memory device
CN112041986A (en) Method for forming three-dimensional memory device having support structure for staircase region
US10043571B1 (en) SRAM structure
CN113410243A (en) Method for forming three-dimensional memory device
US6974987B2 (en) Semiconductor device
US6140174A (en) Methods of forming wiring layers on integrated circuits including regions of high and low topography
US20230116911A1 (en) Semiconductor device including through-silicon via and method of forming the same
US20230104818A1 (en) Methods for Three-Dimensional CMOS Integrated Circuit Formation
US20240120257A1 (en) Layer-By-Layer Formation Of Through-Substrate Via
US20230369219A1 (en) Backside power plane
KR20070054791A (en) Mos transistor and cmos inverter, and method for manufacturing the same
TW202145363A (en) Method of forming semiconductor devices
TW202211325A (en) Method for forming on-chip capacitor structures in semiconductor devices
KR101051813B1 (en) CMOS device and its manufacturing method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20190829

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20210210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230607

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602018066500

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0021823800

Ipc: H01L0021336000

Ref country code: DE

Ref legal event code: R079

Free format text: PREVIOUS MAIN CLASS: H01L0021823800

Ipc: H01L0021336000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 29/78 20060101ALI20231009BHEP

Ipc: H01L 27/092 20060101ALI20231009BHEP

Ipc: H01L 23/528 20060101ALI20231009BHEP

Ipc: H01L 21/8238 20060101ALI20231009BHEP

Ipc: H01L 21/768 20060101ALI20231009BHEP

Ipc: H01L 21/74 20060101ALI20231009BHEP

Ipc: H01L 21/336 20060101AFI20231009BHEP

INTG Intention to grant announced

Effective date: 20231102

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TSAO, PO-CHAO

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602018066500

Country of ref document: DE