KR20060122139A - Method for fabricating flash memory device - Google Patents

Abstract

A method for manufacturing a flash memory device is provided to remove voids and seams in a polysilicon layer as a floating gate by depositing the polysilicon layer using two-step process in self-aligned floating gate processing. A protrudent isolation layer(15) is formed at a field region of a semiconductor substrate(10). A gate oxide layer is formed at an active region of the substrate. A polysilicon layer(17) as a floating gate is deposited on the resultant structure. At this time, the polysilicon layer is deposited by using two-step processes to not have voids and seams in the polysilicon layer.

Description

Manufacturing method of flash memory device {Method for fabricating flash memory device}

1A to 1H are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

2 is a view for explaining a polysilicon film deposition method according to a first method of the present invention

3 is a view for explaining a polysilicon film deposition method according to a second method of the present invention;

4 is a view for explaining a polysilicon film deposition method according to a third method of the present invention

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 15 device isolation film

16 tunnel oxide film 17 polysilicon film for floating gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device for forming a polysilicon film for a floating gate having no seam or void.

Due to the high integration of flash memory devices, many difficulties have arisen in the construction of device isolation layers. Among them, the most important problem is the gap fill gap of a trench having a large aspect ratio having a narrow width and a deep depth.

As the integration from 90nm to 70nm increases, the self-aligned Shallow Trench Isolation (STI) process and the High Density Plasma (HDP) oxide gap fill are not available. It is concluded that securing space is not possible through simple masking and etching.

Thus, a self-aligned floating gate (hereinafter referred to as 'SAFG') process has been introduced as an alternative process.

The SAFG process forms a screen oxide film and a pad nitride film on a semiconductor substrate, forms a trench by etching a pad nitride film, a screen oxide film, and a semiconductor substrate in a field region, forms an isolation layer in the trench, and then forms the pad nitride film and the screen. After the oxide film is removed to expose the semiconductor substrate in the active region, a gate oxide film is formed on the semiconductor substrate in the active region, a polysilicon film is deposited on the entire surface, and CMP is used to form a floating gate.

When using the SAFG process, the thickness of the pad nitride layer must be thick to ensure an appropriate thickness of the floating gate. Meanwhile, the pad nitride layer has a positive slope during the etching process for forming the trench, and the device isolation layer has a negative slope as opposed to the pad nitride layer.

Polysilicon films have relatively good step coverage and deposition characteristics, but when the device isolation layer has a negative slope, polysilicon film deposition characteristics deteriorate, which inevitably forms voids and seams in the polysilicon film. Will be.

The voids and shims are then enlarged during the pre-cleaning process before the interlayer dielectric film deposition, and are buried by the interlayer dielectric film during the interlayer dielectric film deposition.

The interlayer dielectric film embedded in the void and the shim is increased in the sidewall oxidation process after forming the polysilicon film for the control gate and patterning the gate, thereby reducing the coupling ratio between the floating gate and the control gate. Let's do it. As a result, a problem arises in that the speed of the device is lowered and the voltage required for device operation is increased.

On the other hand, the interlayer dielectric film embedded in the void and the shim acts as an etch barrier during the gate patterning process, thereby preventing the etching of the floating silicon polysilicon film, thereby preventing the etching process from proceeding properly and causing a poly residue.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method of manufacturing a flash memory device for forming a polysilicon film for floating gates having no voids and seams.

Another object of the present invention is to improve the coupling ratio between the floating gate and the control gate to improve the speed of the device and to lower the operating voltage of the device.

It is another object of the present invention to prevent the generation of poly residues in the gate etching process.

According to an aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method comprising: forming device isolation layers so that an upper portion protrudes from a surface of the semiconductor substrate in a field region of a semiconductor substrate in which a field region and an active region are defined; Forming a gate oxide film on a semiconductor substrate, and depositing a polysilicon film for a floating gate on the entire surface, and performing a deposition process by dividing the polysilicon film for a floating gate in at least two steps so that the floating gate polysilicon film does not have voids and seams.

According to another aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method comprising: forming device isolation layers so that an upper portion protrudes from a surface of the semiconductor substrate in a field region of a semiconductor substrate in which a field region and an active region are defined; Forming a gate oxide film on the semiconductor substrate, depositing a polysilicon film for floating gate on the entire surface, and performing a heat treatment process to remove voids and seams generated in the floating gate polysilicon film.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1H are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

In order to manufacture a flash memory device according to the present invention, first, as shown in FIG. 1A, a screen oxide film 11 is formed on a semiconductor substrate 10 with a thickness of 50 kΩ or less, and well ions and various threshold voltages are adjusted. After implanting ions, a pad nitride film 12 is deposited on the screen oxide film 11.

The pad nitride layer 12 is deposited to be thicker than the existing deposition thickness to secure the height of the floating gate.

Next, the trench 13 is formed by etching the pad nitride layer 12, the screen oxide layer 11, and the semiconductor substrate 10 in the field region by a photolithography process. In order to facilitate the etching process, a hard mask process may be introduced.

Due to the influence of the carbon component of the photoresist used in the trench etching process, a polymer is generated during the trench etching process, and as the polymer is deposited on the side of the trench 13, the trench 13 has a positive slope. The pad nitride layer 12 also has a positive slope.

Next, as shown in FIG. 1C, a sidewall oxide film 14 is formed on the surface of the semiconductor substrate 10 on which the trench 13 is formed by sidewall oxidation to mitigate etching damage generated during the etching of the trench 13. Form.

As the critical dimension (CD) of the active region decreases, the thickness of the screen oxide film 11 is re-grown during the sidewall oxidation process to increase the thickness, and the screen oxide film 11 having a thickness of 50 μm or less is 100. The sidewall oxidation process is sufficiently performed to regrow to ˜150 Pa, thereby forming the side wall oxide film 14 to a thick thickness of about 50 to 300 ° C.

If the screen oxide film 11 is formed in such a thick manner, there is an advantage in that a thinning phenomenon in which the tunnel oxide film does not grow well in the trench top corner may be suppressed.

Subsequently, as shown in FIG. 1D, an oxide film is deposited on the entire surface of the trench 13 so as to fill the trench 13, and the entire surface is CMP to form the device isolation film 15 in the trench 13.

The CMP process is performed using the pad nitride layer 12 as a target, but over 1/3 to 1/2 of the thickness of the initial pad nitride layer 12 is removed so that oxide residues do not occur on the pad nitride layer 12. CMP.

Then, a post cleaning process is performed using BOE or HF to remove the oxide film remaining on the pad nitride film 12.

As shown in FIG. 1E, the pad nitride layer 12 is removed by a phosphoric acid (H ₃ PO ₄ ) dip process to expose the upper portion of the device isolation layer 15 protruding from the surface of the semiconductor substrate 10. As such, the portion of the device isolation layer 15 protruding from the surface of the semiconductor substrate 10 is referred to as an element isolation film nipple.

Since the device isolation layer 15 is self-aligned to the pad nitride layer 12 having the positive slope, the device isolation layer 15 has a negative slope as opposed to the pad nitride layer 12.

Subsequently, as shown in FIG. 1F, the device isolation layer 15 is etched by a predetermined thickness so that a sufficient space for forming the floating gate is secured while the screen oxide layer 11 is removed by an etching process using diluted HF or BOE. do.

Then, the polysilicon film for the floating gate should be formed. When the device isolation film 15 has a negative slope, a void and a seam inevitably exist in the polysilicon film when the process is performed by the conventional polysilicon film deposition process. In the present invention, as shown in FIG. 1G, the tunnel oxide film 16 is formed on the semiconductor substrate 10 in the active region, and then the polysilicon film is divided into at least two steps or more. By depositing to form a polysilicon film for floating gates having no voids and seams or by forming a polysilicon film for floating gates by a conventional polysilicon film deposition process, and then heat transfer process to promote the silicon atoms of the polysilicon film to promote the floating gate poly By removing the voids and seams generated in the silicon film, the voids and seams are finally To form a polysilicon film 17 for the floating gate do not have.

A method of forming the polysilicon film 17 for the floating gate according to the present invention will be described in more detail as follows.

First method

2 is a view showing a method of forming a polysilicon film for a floating gate according to the first method of the present invention.

As described above, the semiconductor substrate 10 completed until the tunnel oxide film 16 formation process is loaded into the polysilicon film deposition apparatus.

Then, after raising the temperature of the equipment to the polysilicon film deposition temperature and a predetermined time for temperature stabilization evaporate the polysilicon film by supplying the polysilicon deposition gas at a low pressure of 0.1 ~ 3 Torr.

Then, when the thickness of the deposited polysilicon film is a certain thickness to compensate for the negative slope effect of the device isolation film 15, purge the nitrogen gas while maintaining the pressure inside the equipment to maintain the polysilicon deposition gas Removal to stop polysilicon film deposition.

Then, after a predetermined time has elapsed, the polysilicon deposition gas is supplied again to deposit the polysilicon film secondarily to form a floating gate polysilicon film 17 having no seams and voids.

The thickness of the polysilicon film formed during the deposition of the primary polysilicon film is preferably greater than the thickness of the polysilicon film formed during the deposition of the second polysilicon film, and the thickness of the polysilicon film formed during the deposition of the primary polysilicon film Is a thickness corresponding to 1/5 to 1/3 of the width of the active region between the device isolation layers 15.

On the other hand, if the nitrogen gas purge time is too short, since the polysilicon film deposition processes are continuous, it is preferable to set the nitrogen gas purge time to about 30 to 120 minutes.

In the above description, only the case where the process of removing and supplying the polysilicon deposition gas during the formation of the floating gate polysilicon film 17 is supplied once, may be performed one or more times as necessary.

Second method

3 is a view showing a method of forming a polysilicon film for a floating gate according to a second method of the present invention.

In the first method, the pressure in the equipment is maintained at a low pressure when purging nitrogen gas, but in the second method, the pressure in the equipment is raised to normal pressure when purging the nitrogen gas as if the process was completed, and then the pressure was lowered to 0.1 to 3 Torr again. The secondary polysilicon film deposition process is performed.

The first and second methods have a similar effect of forming a polysilicon film for floating gates having no voids and seams.

In the case of the first method, if the nitrogen gas purge time is too short, it does not show a large difference from the existing deposition method, and thus, a sufficient purge time of about 30 to 120 minutes should be given as described above.

On the other hand, the second method is a clear distinction between the polysilicon film deposition process, but there is a disadvantage in that the process time is very high as the pressure must be changed.

Third method

4 is a view showing a method of forming a polysilicon film for a floating gate according to a third method of the present invention.

In the third method of the present invention, the polysilicon film 17 for the floating gate is formed on the semiconductor substrate 10 having completed the process of forming the tunnel oxide film 16 as described above in one deposition process.

Since the isolation layer 15 has a negative slope, the polysilicon film 17 for the floating gate inevitably has sufficient thermal margin to have a void and a seam so that the floating silicon polysilicon film ( A heat treatment process is performed to promote the migration of silicon atoms in 17) so that voids and seams can be removed spontaneously.

The heat treatment step is preferably performed at 570 to 650 ° C., which is a temperature at which the polysilicon film can be crystallized, and the heat treatment time is about 30 to 120 minutes. As a gas of the heat treatment step, a mixed gas of nitrogen gas and hydrogen gas is used, and the mixing ratio is set to N2: H2 = 3: 1.

After forming the floating gate polysilicon film 17 having no seams and voids through the above methods, the floating gate polysilicon film 17 is exposed to expose the device isolation layer 15 as illustrated in FIG. 1H. ) Is CMP to form floating gate 17a.

Subsequently, although not shown in the drawings, an interlayer dielectric film and a polysilicon film for a control gate are sequentially formed, and a gate of the flash memory device is formed by etching the polysilicon film for the control gate, the interlayer dielectric film, and the floating gate 17a by a photolithography process. The flash memory device is manufactured by performing a normal process.

As described above, the present invention has the following effects.

First, since the polysilicon film for floating gates having no voids and seams can be formed, the coupling ratio between the floating gate and the control gate due to the interlayer dielectric film embedded in the voids and seams can be prevented from being reduced. Therefore, the speed of the flash memory element can be improved and the operating voltage can be lowered.

Second, since the operating voltage of the device can be lowered, the size of the high voltage device can be reduced. Therefore, the degree of integration of the device can be improved.

Third, since a polysilicon film for floating gates having no voids and seams can be formed, poly residues can be prevented due to the interlayer dielectric film embedded in the voids and seams.

Claims (16)

(a) forming device isolation layers in the field region of the semiconductor substrate in which the field region and the active region are defined so that an upper portion thereof protrudes above the surface of the semiconductor substrate; (b) forming a gate oxide film on the semiconductor substrate in the active region; (c) depositing a polysilicon film for floating gate on the entire surface, and dividing the polysilicon film for at least two steps to prevent the floating gate polysilicon film from having voids and seams. The method of claim 1, Step (c) is a first step of depositing a polysilicon film of a predetermined thickness on the semiconductor substrate by supplying a polysilicon deposition gas; A second step of stopping the polysilicon film deposition for a predetermined time by purging the polysilicon deposition gas; And re-depositing the polysilicon film by resupplying the polysilicon film deposition gas, wherein the first to the third steps are performed at least one or more times. The method of claim 2, The first to third steps are performed at a constant pressure. The method of claim 3, wherein The constant pressure is a method of manufacturing a flash memory device, characterized in that 0.1 ~ 3 Torr. The method of claim 2, The predetermined time is 30 to 120 minutes manufacturing method of a flash memory device. The method of claim 2, And in the second step, nitrogen gas is flowed to purge the polysilicon deposition gas. The method of claim 2, The first and third steps are performed at a pressure lower than the normal pressure, and the second step is performed at the normal pressure. The method of claim 7, wherein A method of manufacturing a flash memory device comprising performing the first and third steps at 0.1 to 3 Torr. The method of claim 2, And the thickness of the polysilicon film deposited in the first step is thicker than the thickness of the polysilicon film deposited in the second step. The method of claim 2, And a thickness of the polysilicon film deposited in the first step is 1/5 to 1/3 of the width of the active region between the device isolation layers. Forming device isolation layers in the field region of the semiconductor substrate having the field region and the active region defined therein, the upper portion protruding from the surface of the semiconductor substrate; Forming a gate oxide film on the semiconductor substrate in the active region; Depositing a polysilicon film for a floating gate on the front surface; And removing voids and shims generated in the floating gate polysilicon film by performing a heat treatment process. The method of claim 11, And the heat treatment step is performed at a temperature at which the floating gate polysilicon film can be recrystallized. The method of claim 12, The heat treatment process is carried out at 570 ~ 650 ℃ manufacturing method of a flash memory device. The method of claim 11, The heat treatment process is carried out in a nitrogen gas and hydrogen gas atmosphere, characterized in that the manufacturing method of the flash memory device. The method of claim 14, And a mixing ratio of the nitrogen gas and the hydrogen gas is set to 3: 1. The method of claim 11, A method of manufacturing a flash memory device, characterized in that the heat treatment step is performed for 30 to 120 minutes.

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