JPH04239761A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a leakage current between a source and a drain of a MOSFET in a high withstand voltage CMOS semiconductor device, to prevent damage of an element connected to a high stage, and to prevent a latchup generated at a CMOS semiconductor itself. CONSTITUTION:A conductor is provided on a field oxide film between a gate electrode and a guard region except source, drain regions. The conductor is connected to a gate electrode or the guard region through a contact hole. With this configuration, a potential under the oxide film can be fixed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage CMOS semiconductor device used particularly for driving flat panel displays such as LCDs and PDPs.

0002

2. Description of the Related Art Generally, high voltage CMOS semiconductor devices have a structure to prevent latch-up. There is a conventional technique disclosed in Japanese Patent Application Laid-Open No. 61-207052, which will be described below with reference to FIGS. 5 to 8.

FIG. 5 shows a high breakdown voltage C in the first prior art.
1 is a cross-sectional view of a MOS semiconductor device. 1 is an N-type silicon substrate, 2 is a P-type well region, and the field region of the N-type silicon substrate 1 and P-type well region 2 is LOCOS (L
ocal Oxidation of Sili
Buried field oxide film 3 formed by con) method
is formed. On the surface of the N-type silicon substrate 1, there is a P-type M layer consisting of P+ type source and drain regions 4, 5 and a polysilicon gate electrode 7 on a gate oxide film 6, respectively.
An OSFET 8 is formed, and an N-type MOSFET 13 is formed on the surface of the P-type well region 2, each consisting of N+-type source and drain regions 9, 10 and a polysilicon gate electrode 12 on a gate oxide film 11.

FIG. 6 shows a top view of the structure of a high voltage CMOS semiconductor device according to the first prior art. P-type MOS
The FET 8a and the N-type MOSFET 13a are connected to each other through a contact hole at a point 19b by an aluminum electrode 19 indicated by a dotted line, thereby forming an inverter circuit. However, the aluminum electrode 19, each element formed on the surfaces of the N-type silicon substrate 1a and the P-type well region 2, and the aluminum electrode 19 are insulated from each other by an insulating film except for the point 19b.

As shown in FIG. 5, the feature of this first prior art is the structure below the field oxide film 3. Below field oxide film 3, channel stopper regions 14 and 15 with low impurity concentration and guard regions 16 and 17 with high impurity concentration are provided. That is, an N-type channel stopper region 14 is provided on the entire surface under the field oxide film 3 of the silicon substrate 1a.
N+ in the channel stopper region 14 apart from the P-type source/drain regions 4 and 5 of the MOSFET 8a.
A mold guard region 16 is formed. Further, a P-type channel stopper region 15 is provided on the entire surface under the field oxide film 3 of the P-type well region 2, and an N-type MOSFET 13a is provided.
A P-type guard region 17 is formed in the channel stopper region 15 apart from the N+-type source/drain regions 9 and 10, respectively. Normally, in a high voltage CMOS semiconductor device, it is necessary to lower the impurity concentration of the channel stopper regions 14, 15 in order to increase the junction voltage between the source regions 4, 9, the drain regions 5, 10, and the channel stopper regions 14, 15. However, the channel stopper region 14,
If 15 is formed with a low impurity concentration, there is a drawback that inversion occurs under the field oxide film 3, creating a parasitic MOS, and latch-up is likely to occur. In this first prior art, in order to solve this drawback, the channel stopper region 14,
15 is set to a sufficiently low concentration, and guard regions 16 and 17 are set to a high concentration to realize a high breakdown voltage CMOS transistor.

However, in the first prior art, the guard area 1
6 and 17 required two photolithography steps and two ion implantation steps, which was unsatisfactory because the additional steps would increase costs and reduce yield.

In order to eliminate the increase in the number of steps, there is a second conventional technique, which will be explained with reference to FIGS. 7 and 8.

FIG. 7 shows a high voltage CM in the second prior art.
FIG. 2 is a cross-sectional view of an OS semiconductor device. 21a is an N-type silicon substrate, 22 is a P-type well region, and the silicon substrate 21
a and the field region of the P-type well region 22.
A buried field oxide film 23 formed by the COS method is formed. P-type MOSFET 28a is formed of P+ type source/drain regions 24, 25 and a polysilicon gate electrode 27 on gate oxide film 26, and N-type MOSFET 33a is formed of N+ type source/drain regions 29, 30 and gate oxide film 31, respectively. It is formed with the polysilicon gate electrode 32 above.

FIG. 8 shows a high voltage CM in the second prior art.
FIG. 2 is a top view of an OS semiconductor device. FIG. 8 will be explained below. A P-type MOSFET 28 is installed on the surface of the N-type silicon substrate 21.
a is formed, and an N-type MOS is formed on the surface of the P-type well region 22.
A FET 33a is formed. Guard areas 36, 37
is formed so as to surround the P-type MOSFET 28a and the N-type MOSFET 33a, and is fixed to the ground potential VSS. Further, the N-type silicon substrate 21a has a power supply voltage VD
It is fixed at D.

As shown in FIG. 7, the feature of the second prior art is that an N+ type guard region 36 and a P+ type guard region 37 are provided in the field regions of the N type silicon substrate 21a and the P type well region 22 for both MOSFETs. This is because it is formed at the same time as the source and drain regions.
This prevents an increase in the number of steps and solves the drawbacks of the first prior art.

[0011]

[Problem to be solved by the invention] However, the first problem
The device described in the second prior art has a problem in that a leakage current flows between the source and the drain.

The amount of leakage current is determined by the distance A between the polysilicon gate electrode 32 and the guard region 37, the source region 30 and the drain region 2 in the structure of the semiconductor device as shown in FIG.
It is related to the distance B that extends beyond 9. That is, since the potential under the field oxide film located directly under the polysilicon gate electrode 32 in areas other than the channel formation region is fixed by the polysilicon gate electrode 32, the depletion layer 101 extending from the source region 29 and the drain region 30 is connected to the polysilicon gate. It cannot extend to the region on the opposite side of the electrode 32. However, as indicated by the dotted line 103, the gate electrode 3
In a region 103 under the field oxide film which is not located directly below the field oxide film, the potential is not fixed because there is nothing above to apply a potential. Therefore, since the depletion layer 101 can extend to the opposite side with the polysilicon gate electrode 32 in between, the voltage applied to the source region 30 and the drain region 29 acts on the hole-electron pairs generated within the depletion layer 101. Leakage current flows.

Therefore, it is conceivable to form the polysilicon gate electrode 27 extending in the direction of the guard region 22. However, since there is a portion in the guard region 22 where high concentration impurities cannot be introduced, leakage current still occurs.

[0014]Also, it is conceivable to increase the distance between the MOSFET and the guard region and increase the distance B by the protrusion of the gate electrode to substantially prevent the growth of the depletion layer, but this would result in miniaturization of the semiconductor device.

In order to prevent this, it is conceivable to create a structure in which the distance A is set to zero and the source/drain regions 29 and 30 are electrically separated by a region where the potential is fixed. However, with photolithography technology, alignment misalignment occurs and it is not possible to set the potential to zero accurately, causing leakage current to flow through the region 103 (under the field oxide film) where the potential is not fixed, resulting in deterioration of the characteristics of the semiconductor device and damage to the subsequent stage. There is a problem in that connected elements (for example, flat display panels such as LCD and PDP) may be damaged.

[0016]

[Means for Solving the Problems] In order to solve the problem of leakage current flowing, the present invention relates to a semiconductor device, particularly a high voltage CMOS semiconductor device, and provides source and drain regions formed on the surface of a first conductivity type semiconductor substrate. , a second conductivity type channel MOSFET consisting of a gate electrode, and formed apart from the MOSFET on the surface of the semiconductor substrate,
a guard region of a first conductivity type with a high impurity concentration surrounding the MOSFET; an insulating film formed on the semiconductor substrate including the MOSFET and the guard region; There is provided a semiconductor device characterized in that the gate electrode or the guard region formed across the guard region excluding the drain region and the gate electrode are at the same potential.

[0017]

[Operation] According to the present invention, a region under the field oxide film other than the source region and the drain region, where the potential is not fixed between the guard region and the gate electrode, is placed on the intermediate insulating film with the intermediate insulating film in between. A potential can be applied from Therefore, the depletion layer extending from the source region or the drain region cannot extend to the opposite side across the gate electrode, so that leakage current can be reduced.

[0018]

[Embodiment] Fig. 1 shows a high breakdown voltage C which is a first embodiment of the present invention.
FIG. 2 is a top view of a MOS semiconductor device. The first embodiment will be described below with reference to FIG.

[0019] On the surface of the N-type silicon substrate 11a, there is a P-type MO.
SFET 12a is formed, and N-type MOSFET 18a is formed on the surface of P-type well region 13. Guard regions 15 and 16 are P-type MOSFET 12a and N-type MOSFET
It surrounds ET18a. Further, the N-type silicon substrate 11a is fixed to the power supply voltage VDD, and the P-type well region 1
3 is fixed to the ground potential VSS. source area 4
, 9 and the guard region 1 excluding the drain regions 5 and 10
5 and gate electrode 17, between guard region 16 and gate electrode 1
Between 4 and 4 are aluminum electrodes 2 and 2, respectively, as shown by dotted lines.
(The gate electrode 17 and the gate electrode 14 are connected to each other by an aluminum electrode 21 beyond the guard regions 15 and 16.) The gate electrode 17 is covered with contact holes 22 and 23, respectively.
, 14.

FIG. 3 is a sectional view of a high voltage CMOS semiconductor device according to the first embodiment of the present invention. The relationship between the aluminum electrode 25, the contact hole 23, and the guard region 16 in the first embodiment will be described below with reference to FIG. Note that the cross-sectional view is a cross-sectional view of the gate electrode taken in the horizontal direction, and only a portion including the main points of the invention is shown.

An aluminum electrode 25 formed on the intermediate insulating film 102 covers the guard region 16 and the gate electrode 14 and is further connected to the gate electrode 14 through a contact hole 23 . That is, a region under the field oxide film 3 where the potential between the guard region 16 and the gate electrode 14 is not fixed is indirectly covered by the aluminum electrode 25 on the intermediate insulating film 102.

FIG. 2 is a top view of a high voltage CMOS semiconductor device according to a second embodiment of the present invention. The difference between the second embodiment and the first embodiment is the way the aluminum electrodes 24 and 25 are connected. In the second embodiment, aluminum electrodes 24, 25 are connected to guard regions 15, 25 by contact holes 22, 23, respectively. FIG. 4 is a cross-sectional view of a high voltage CMOS semiconductor device according to a second embodiment of the present invention. Hereinafter, the relationship among the aluminum electrode 25, contact hole 23, and guard region 16 in the second embodiment will be explained using FIG. An aluminum electrode 25 formed on the intermediate insulating film 102 covers the guard region 16 and the gate electrode 14, and is further connected to the guard region 16 through a contact hole 23. That is, a region under the field oxide film 3 between the guard region 16 and the gate electrode 14 is indirectly covered by the aluminum electrode 25 on the intermediate insulating film 102.

When an inverter circuit is configured with either of the above structures, leakage current is prevented, so output characteristics can be stabilized, and leakage current also triggers latch-up, so this should be prevented. As a result, a high breakdown voltage CMOS semiconductor device without malfunction can be obtained.

In this embodiment, a high voltage CMOSFET semiconductor device with a P-type well structure formed on an N-type semiconductor substrate was described, but the same applies to a high-voltage CMOS semiconductor device with an N-type well structure formed on a P-type semiconductor substrate. The effects can be expected. Furthermore, LDD, which is known as a high voltage MOS structure,
(Lightly Doped Drain) structure, DDD (Double Defused Dr.
ain) structure It can also be applied to offset structures.

[0025]

According to the present invention, an intermediate insulating film is sandwiched between the guard region and the gate electrode in a region under the field oxide film other than the source region and the drain region where the potential is not fixed. By applying a potential (same potential as the gate electrode or the same potential as the guard region) from above the film, it is possible to prevent the depletion layer from extending to the opposite side across the gate electrode. By preventing the depletion layer from expanding, it is possible to prevent unnecessary leakage current from flowing between the source and drain. That is, when a high voltage CMOS semiconductor device having this structure is used to drive a flat display such as an LCD or PDP, the display elements will not be damaged by leakage current when the display is turned off. Furthermore, since leakage current also serves as a trigger for latch-up, by preventing leakage current, latch-up can be prevented and damage to the semiconductor device itself can also be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit pattern diagram for explaining a first embodiment of the present invention.

FIG. 2 is a circuit pattern diagram for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view for explaining the first embodiment of the present invention.

FIG. 4 is a sectional view for explaining a second embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the first prior art.

FIG. 6 is a top view for explaining the first prior art.

FIG. 7 is a cross-sectional view for explaining a second prior art.

FIG. 8 is a top view for explaining a second prior art.

FIG. 9 is a circuit pattern diagram for explaining the problem to be solved by the invention.

[Explanation of symbols]

1a, 21a, 11a N-type silicon substrate 2, 2
2, 13 P-type well region 3, 23 Field oxide film 4, 5, 9, 10, 24, 25, 29, 30 Source, drain region 6, 11, 26, 31 Gate oxide film 7, 12,
27, 32 Polysilicon gate electrode 8a, 28
a, 12a P-type MOSFET 13a, 33a,
18a N-type MOSFET14, 15, 34, 3
5 Channel stopper region 16, 17, 36, 3
7 Guard region 101 Depletion layer 102 Intermediate insulating film

Claims (3)

[Claims] 1. A source region and a drain region formed on the surface of a first conductivity type semiconductor substrate, and a second conductivity type channel formed between the source region and the drain region,
a second gate electrode formed on the channel;
a conductivity type channel MOSFET, a first conductivity type guard region surrounding the MOSFET and having a high impurity concentration formed on the surface of the semiconductor substrate, and a first conductivity type guard region formed on the semiconductor substrate including the MOSFET and the guard region. and a conductor having a predetermined potential formed on the insulating film and spanning the guard region excluding the source region and the drain region and the gate electrode. Device. 2. The semiconductor device according to claim 1, wherein the predetermined potential is the same potential as the gate electrode. 3. The semiconductor device according to claim 1, wherein the predetermined potential is the same potential as the guard region.