JPS54131888A - Manufacture of mos-type semiconductor device - Google Patents

Manufacture of mos-type semiconductor device

Info

Publication number
JPS54131888A
JPS54131888A JP3943378A JP3943378A JPS54131888A JP S54131888 A JPS54131888 A JP S54131888A JP 3943378 A JP3943378 A JP 3943378A JP 3943378 A JP3943378 A JP 3943378A JP S54131888 A JPS54131888 A JP S54131888A
Authority
JP
Japan
Prior art keywords
layer
selectively
sio
mask
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3943378A
Other languages
Japanese (ja)
Inventor
Sunao Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3943378A priority Critical patent/JPS54131888A/en
Publication of JPS54131888A publication Critical patent/JPS54131888A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To realize the miniaturization, high-degree integration and high performance for the element without complicating the conventional manufacturing process.
CONSTITUTION: Selective oxidation 14 is given to SiO212 on p-type Si substrate 11 via the mask of Si3N413. Mask 13 is removed selectively, and the phosphorus is diffused to form n+ layer 15 which is then turned to the internal wiring layer of about 5Ω/opening through the 10-minute treatment at 1000°C. Then film 13 and 12 are removed with SiO216 and poly Si electrode 17 formed selectively, and n+ layer 18 and 19 are formed by injection of the As ion. Layer 19 and 15 are then unified together. Then the substrate is covered with CVDSiO2 with the opening drilled selectively to complete the Al wiring. In this way, the microstructure of the gate length 4μm or less can be obtained under the good controlability to promote the integration furthermore. At the same time, the layer resistance can be reduced since internal wiring layer 15 is formed previously, avoiding the signal delay and a large amount of voltage drop.
COPYRIGHT: (C)1979,JPO&Japio
JP3943378A 1978-04-04 1978-04-04 Manufacture of mos-type semiconductor device Pending JPS54131888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3943378A JPS54131888A (en) 1978-04-04 1978-04-04 Manufacture of mos-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3943378A JPS54131888A (en) 1978-04-04 1978-04-04 Manufacture of mos-type semiconductor device

Publications (1)

Publication Number Publication Date
JPS54131888A true JPS54131888A (en) 1979-10-13

Family

ID=12552856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3943378A Pending JPS54131888A (en) 1978-04-04 1978-04-04 Manufacture of mos-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS54131888A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397715A (en) * 1993-10-21 1995-03-14 Micrel, Incorporated MOS transistor having increased gate-drain capacitance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397715A (en) * 1993-10-21 1995-03-14 Micrel, Incorporated MOS transistor having increased gate-drain capacitance
US5625216A (en) * 1993-10-21 1997-04-29 Micrel, Inc. MOS transistor having increased gate-drain capacitance

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