JPS54137983A - Manufacture of mos semiconductor device - Google Patents

Manufacture of mos semiconductor device

Info

Publication number
JPS54137983A
JPS54137983A JP4611878A JP4611878A JPS54137983A JP S54137983 A JPS54137983 A JP S54137983A JP 4611878 A JP4611878 A JP 4611878A JP 4611878 A JP4611878 A JP 4611878A JP S54137983 A JPS54137983 A JP S54137983A
Authority
JP
Japan
Prior art keywords
film
poly
oxidized
thin
oxidized film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4611878A
Other languages
Japanese (ja)
Other versions
JPS6135711B2 (en
Inventor
Keizo Sakiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4611878A priority Critical patent/JPS54137983A/en
Publication of JPS54137983A publication Critical patent/JPS54137983A/en
Publication of JPS6135711B2 publication Critical patent/JPS6135711B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To simplify the design of an element and to prevent characteristics from deteriorating, by growing the 1st poly-Si thinner and by automatically positioning the 1st poly-Si through thermal oxidation after etching the 2nd poly-Si film into a desirable pattern. CONSTITUTION:On the Si substrate, field oxidized film 12 and oxidized film 13 are formed and doped poly-Si thin film 14 approximate one fifth as thin as conventional one is formed. Further, the 2nd poly-Si thick film 16 and oxidized film 17 are stacked via oxidized film 15. Films 17 and 16 are etched selectively to expose film 14 partially; as a result, since thin film 14 is provided with additional phosphorus to high density, exposed layer 14 is oxidized completely and film 14 is positioned automatically to film 16. This oxidized film is provided with an opening and a N<+> layer is provided. Afterwards, floating gate MOSs of the double structure and single structure are formed on the same substrate at the same time through a wiring process. In the above constitution, the design of the element is simplified and the substrate surface never comes in direct contact with an etching solution at the single gate part so as to prevent element characteristics from deteriorating, so that a device with excellent characteristics can be obtained.
JP4611878A 1978-04-18 1978-04-18 Manufacture of mos semiconductor device Granted JPS54137983A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4611878A JPS54137983A (en) 1978-04-18 1978-04-18 Manufacture of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4611878A JPS54137983A (en) 1978-04-18 1978-04-18 Manufacture of mos semiconductor device

Publications (2)

Publication Number Publication Date
JPS54137983A true JPS54137983A (en) 1979-10-26
JPS6135711B2 JPS6135711B2 (en) 1986-08-14

Family

ID=12738070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4611878A Granted JPS54137983A (en) 1978-04-18 1978-04-18 Manufacture of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS54137983A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023681A (en) * 1988-10-08 1991-06-11 Hyundai Electronics Industries Co., Ltd. Method for arranging EEPROM cells and a semiconductor device manufactured by the method
US5599727A (en) * 1994-12-15 1997-02-04 Sharp Kabushiki Kaisha Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023681A (en) * 1988-10-08 1991-06-11 Hyundai Electronics Industries Co., Ltd. Method for arranging EEPROM cells and a semiconductor device manufactured by the method
US5599727A (en) * 1994-12-15 1997-02-04 Sharp Kabushiki Kaisha Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed

Also Published As

Publication number Publication date
JPS6135711B2 (en) 1986-08-14

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