JPS56114375A - Manufacture of nonvolatile semiconductor memory - Google Patents
Manufacture of nonvolatile semiconductor memoryInfo
- Publication number
- JPS56114375A JPS56114375A JP1763780A JP1763780A JPS56114375A JP S56114375 A JPS56114375 A JP S56114375A JP 1763780 A JP1763780 A JP 1763780A JP 1763780 A JP1763780 A JP 1763780A JP S56114375 A JPS56114375 A JP S56114375A
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- type
- reverse
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To manufacture the memory corresponded to the performance of a final device at a stage of forming a wafer by a method wherein N type source region and drain region are formed on the surface of a P type Si semiconductor substrate and an N type region is formed on the reverse of the substrate. CONSTITUTION:A field SiO2 film 3 is formed in an inactive region on the surface 2 of the P type Se semiconductor substrate 1. Thin SiO2 films 4 and 6 are formed on the film 3 by a thermal oxidation method and a polycrystalline Si film 7 is formed on the film 6. Thereafter, a photoetching technology or the like removes the films 7-4 in sequence selectively, exposes a part of the substrate surface and exposes the whole of the reverse 8. Then, a thermal diffusion method forms the N type source region 9 and drain region 10 and further, forms the N type region 11 on the reverse. In addition, a film 12 containing is formed, source and drain contact openings 13, 14 being perforated, an Al evaporation being applied to the whole surface, draw-out electrodes 15, 16 being provided and the region 11 being removed. Whereby the memory enables to be manufactured corresponded to the performance of the final device at the stage of forming the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1763780A JPS56114375A (en) | 1980-02-15 | 1980-02-15 | Manufacture of nonvolatile semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1763780A JPS56114375A (en) | 1980-02-15 | 1980-02-15 | Manufacture of nonvolatile semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56114375A true JPS56114375A (en) | 1981-09-08 |
Family
ID=11949373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1763780A Pending JPS56114375A (en) | 1980-02-15 | 1980-02-15 | Manufacture of nonvolatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56114375A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5737878A (en) * | 1980-08-19 | 1982-03-02 | Toshiba Corp | Semiconductor integrated circuit |
-
1980
- 1980-02-15 JP JP1763780A patent/JPS56114375A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5737878A (en) * | 1980-08-19 | 1982-03-02 | Toshiba Corp | Semiconductor integrated circuit |
| JPS6318866B2 (en) * | 1980-08-19 | 1988-04-20 | Tokyo Shibaura Electric Co |
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