JPS6318866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit in which a complementary MOS transistor and a MOS transistor having a floating gate are formed on the same semiconductor substrate.

In general, EPROM (Erasable Programmable
The peripheral circuit of a Read Only Memory (Read Only Memory) consists of a write circuit made of N-channel MOS transistors, a sense amplifier, etc. However, due to the current demands for higher density integration, higher speed, and lower power consumption, the peripheral circuits mentioned above are CMOS with inherently high speed and low power consumption
(complementary MOS) configuration, and some products are currently being commercialized. However, in CMOS, there is a phenomenon in which an abnormal current flows (latch-up phenomenon) due to external noise current (voltage) turning on a parasitic thyristor formed inside the CMOS, and this abnormal current causes problems such as malfunction and destruction. On the other hand, in SAMOS, when data is written, many carriers (holes in the case of a P-type substrate) are generated near the drain.
Flows through the substrate. Therefore, when configuring CMOS and SAMOS on the same substrate to create a more organic device, the CMOS latch-up phenomenon caused by the substrate current flowing from SAMOS becomes a problem, and countermeasures are being considered.

Figure 1 shows N-channel SAMOS and N-well CMOS.
FIG. 2 is a concrete explanatory diagram of the latch-up phenomenon that occurs in FIG. In the figure, 1 is a P-type silicon substrate, and its specific resistance is, for example, 10 Ω-cm. 2 is an N-well layer, 3 is a CMOS inverter formed on the substrate 1 and N-well layer 2, 4 is a P-channel transistor of this inverter 3, 5 is an N-channel transistor,
6 is the source layer of the P channel transistor 4, 7 is the drain layer, 8 is the gate (polysilicon), and 9 is N ⁺ for holding the N well layer 2 at the power supply V _DD potential.
It is a layer. 10 is the source layer of the N-channel transistor 5, 11 is the drain layer, 12 is the gate, 1
3 is P ⁺ for holding the P substrate 1 at the power supply V _SS potential
It is a layer. 15 is a source of the SAMOS 14, 16 is a drain, 17 is a control gate (polysilicon), and 18 is a floating gate (polysilicon).

The above latch-up phenomenon occurs when the N ⁺ type source layer 10
It is composed of a horizontal NPN transistor Tr 1 consisting of a P type substrate ₁ and an N well layer 2, and a vertical PNP transistor Tr ₂ consisting of a P ⁺ type drain layer 7, an N well layer 2 and a P type substrate 1. This is a phenomenon in which an external noise current enters the PNPN parasitic thyristor from the input Vin, the output Vout, or from inside the board, the PNPN parasitic thyristor turns on, and an abnormal current (for example, several hundred mA) flows between the power supply V _DD and the ground V _SS . especially
When writing data to the SAMOS 14, a substrate current _i1 consisting of many carriers (holes in a P type substrate) generated near the drain 16 flows through the substrate 1, enters the P ⁺ layer 13, and becomes a trigger current for a parasitic thyristor. This causes the aforementioned latch-up phenomenon. According to experiments, it has been confirmed that a latch-up phenomenon occurs when the substrate current generated from SAMOS enters a CMOS inverter in excess of several mA. Furthermore, in the structure shown in FIG. 1, the back surface of the substrate is grounded to absorb the aforementioned substrate current. The substrate current generated in the vicinity of the drain 16 of the SAMOS 14 is divided into the inverse ratio of the resistance R ₁ between the layers 13 and 16 and the resistance R ₂ between the layer 16 and the back surface of the substrate, and flows in the SAMOS 14.
In a structure where the CMOS inverter is close to 50 to 100 μm relative to the substrate thickness (approximately 300 μm), approximately 2/3 is CMOS
Experiments have confirmed that the latch-up is likely to occur due to the inverter flowing into the inverter.

The present invention was made in view of the above circumstances, and
When configuring CMOS and SAMOS on the same semiconductor substrate, a semiconductor layer of the same conductivity type and higher resistivity is formed on the semiconductor substrate, and the substrate current generated when writing data to SAMOS is reduced to a lower resistivity. By absorbing it by flowing it to the substrate side,
By reducing the substrate current flowing to the CMOS side,
The present invention aims to provide a semiconductor integrated circuit that can prevent the CMOS latch-up phenomenon from occurring.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a cross-sectional view of an integrated circuit showing the same embodiment. Since this configuration corresponds to that of FIG. 1, corresponding parts are given the same reference numerals and explanations will be omitted. , only the characteristic points will be extracted and explained. The feature of this example is that the specific resistance is 0.01 to 0.1Ω−
A P-type semiconductor layer ₁₂ with a specific resistance of, for example, 10Ω-cm is formed on a P-type substrate ₁₁ with a low resistivity of 10Ω-cm by a known vapor phase growth method, and a CMOS circuit 3 and a SAMOS1 are formed on this layer ₁₂ .
4 will be provided. That is, in this configuration, in order to increase the absorption efficiency of the substrate current on the back surface of the substrate, the specific resistance of the back surface side 1 ₁ of the substrate is made lower than that of the front surface side 1 ₂ of the substrate.
The resistance between the SAMOS drain layer 16 and the back surface of the substrate is
On a substrate with a structure that is considerably smaller than the resistance between the drain layer 16 and the CMOS inverter 3,
It consists of CMOS and SAMOS.

In the conventional structure shown in Figure 1, when a 1kΩ external resistor is attached to the back of the board, the board current generated from the SAMOS 14 flows to the CMOS inverter 3 side, making the latch-up phenomenon of the CMOS inverter 3 more likely to occur. Experimental results have been obtained, and in the configuration shown in Figure 2, the resistance between the drain layer 16 of the SAMOS 14, which is the substrate current generation source, and the back surface of the substrate ₁₁ is lower than that in Figure 1, and the substrate current is
Since most of the current flows to the back side of the substrate ₁₁ like _i2 , the latch-up phenomenon of the CMOS inverter 3 does not occur.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, the present invention is not limited to the above embodiments.
Similar measures can be taken for CMOS configurations, and FAMOS (Floating
Gate Avalanche MOS), etc.
Various applications are possible.

As explained above, according to the present invention, since the substrate current that causes the latch-up phenomenon in a CMOS circuit can be absorbed, a semiconductor integrated circuit that does not cause the latch-up phenomenon can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional configuration diagram showing a conventional semiconductor integrated circuit, and FIG. 2 is a cross-sectional configuration diagram showing an embodiment of the present invention. 1 ₁ ... Low resistivity substrate, 1 ₂ ... High resistivity semiconductor layer, 3 ... CMOS inverter, 14 ...
SAMOS.

Claims (1)

[Claims] 1. A semiconductor layer of the same conductivity type and having a high specific resistance value with respect to the semiconductor substrate is deposited on a semiconductor substrate of a first conductivity type, and a complementary MOS transistor circuit and a flowchart are formed on the surface side of the semiconductor layer. 1. A semiconductor integrated circuit formed by forming a MOS transistor having a leading gate.