JPS6135711B2 - - Google Patents
Info
- Publication number
- JPS6135711B2 JPS6135711B2 JP4611878A JP4611878A JPS6135711B2 JP S6135711 B2 JPS6135711 B2 JP S6135711B2 JP 4611878 A JP4611878 A JP 4611878A JP 4611878 A JP4611878 A JP 4611878A JP S6135711 B2 JPS6135711 B2 JP S6135711B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- polycrystalline silicon
- gate
- film
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 description 75
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、二重ゲート構造の不揮発性書き換え
可能な記憶蓄積機能を備えたMOS半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS semiconductor device having a double gate structure and a non-volatile rewritable memory storage function.
近年開発された不揮発性半導体メモリには、浮
動ゲートMOSとMNOS（Metal―Nitride―Oxide
―Semiconductor）の２種類があり、本発明は前
者の浮動ゲート構造をもつ書き控え可能なROM
に関する。 Nonvolatile semiconductor memories developed in recent years include floating gate MOS and MNOS (Metal-Nitride-Oxide).
- Semiconductor), and the present invention is a writable ROM with a floating gate structure.
Regarding.
浮動ゲートMOSは第１図に示す如く、浮動ゲ
ートFG及びコントロールゲートCGの２重Siゲー
トを備えたＮチヤネルMOSトランジスタで、浮
動ゲートFGに電子を蓄えている状態が書込み状
態である。該書込み動作は、コントロールゲート
CGとドレインＤに正パルスを印加する。該正パ
ルスの印加によつて浮動ゲートの電位ＶFが正に
上昇し、トランジスタは導通して電流が流れる。
この時空乏層の電界はさほど強くないため電子な
だれ降状は生じないが、イオン化は生じる。イオ
ン化率は低いがドレイン電流が大きいため高エネ
ルギー電子が多数発生する。この電子がコントロ
ールゲートCGに引つ張られてSiO2膜のエネルギ
ー障壁を越すことにより書込みが達成される。一
方読み出しはコントロールゲートから見たしきい
値電圧ＶTCの差を利用し、浮動ゲートに電子が蓄
積していればＶTCは高くなり、電子がなければ低
い電圧となることに基いて読み出しが行われる。 As shown in FIG. 1, the floating gate MOS is an N-channel MOS transistor equipped with a double Si gate of a floating gate FG and a control gate CG, and the state in which electrons are stored in the floating gate FG is the write state. The write operation is controlled by a control gate.
Apply a positive pulse to CG and drain D. By applying the positive pulse, the potential V F of the floating gate rises positively, the transistor becomes conductive, and current flows.
At this time, the electric field in the depletion layer is not very strong, so no electron avalanche occurs, but ionization does occur. Although the ionization rate is low, many high-energy electrons are generated because the drain current is large. Writing is achieved when these electrons are pulled by the control gate CG and cross the energy barrier of the SiO 2 film. On the other hand, readout uses the difference in the threshold voltage VTC seen from the control gate; if electrons are accumulated in the floating gate, VTC will be high, and if there are no electrons, the voltage will be low. It will be done.
この種の半導体記憶素子はシリコン半導体チツ
プに組み込まれるが、同一チツプ内の全素子が２
重ゲートで構成されることはほとんどなく、マイ
クロコンピユータ等のROMとして利用される場
合、通常の１重ゲートMOSと共に併用してメモ
リー部が構成される。従つて半導体装置を製造す
る場合、２重ゲート構造と１重ゲート構造の両者
のことが配慮されて製造工程が実行されねばなら
ない。 This type of semiconductor memory element is built into a silicon semiconductor chip, but all the elements within the same chip are
It is rarely constructed with heavy gates, and when used as a ROM for microcomputers, it is used together with a normal single gate MOS to form a memory section. Therefore, when manufacturing a semiconductor device, both the double gate structure and the single gate structure must be taken into consideration during the manufacturing process.
まず従来の浮動ゲートMOSを備えた半導体装
置の製造方法を第２図及び第３図を用いて説明す
る。第２図ａ〜ｇは２重ゲートMOSの製造工程
を、第３図ａ〜ｇは１重ゲートMOSの製造工程
を示し、両図のａ〜ｇは夫々対応するもので、同
一半導体チツプ内の２重ゲート部及び１重ゲート
部を夫々抽出してその断面を示す。図ａに於て１
はＰ型シリコン基板で、各トランジスタ領域が位
置決めされてフイールド部選択酸化２が既に施こ
され、第１絶縁酸化膜３上に第１多結晶シリコン
膜４の成長がなされる。該第１シリコン膜４は浮
動ゲートFGを設けるためのもので、従つて第
２，第３図ｂに示す如く２重ゲート部はトランジ
スタ領域を覆つて残されるが、１重ゲート部はエ
ツチング除去される。上記第１シリコン膜４に
N+拡散（但し多結晶シリコン膜４の成長時に既
にＮ型不純物を含んで膜成長がなされた場合は必
要としない）が行われ、第１シリコン膜４に低抵
抗処理がなされる。次に１重ゲート部及び第１シ
リコン膜４上に成長した酸化膜を一旦除去した後
再度所望厚さの第２酸化膜５を形成してゲート酸
化処理する（第２，第３図ｃ）。上部第２酸化膜
５を形成した後第２，第３図ｄに示す如く第２多
結晶シリコン膜６を成長させ、続いて該シリコン
膜６上にマスク作用を果させるための第３の熱酸
化膜７が設けられる。上記第２多結晶シリコン膜
６は２重ゲート部ではコントロールゲートとして
作用し、１重ゲート部では通常のゲートとして作
用する。上記第３酸化膜７及び第２シリコン膜６
が所望パターンにエツチングされ、２重シリコン
ゲート部では第１シリコン膜４が露出した状態
に、１重シリコンゲート部ではソース及びドレイ
ンのトランジスタ領域が露出した状態に加工され
る（第２，第３図ｅ）。２重ゲート部では残留し
た第３酸化膜７及び第２シリコン膜６をマスクと
して第１シリコン膜４がエツチング加工され、両
トランジスタ領域共にソース，ドレイン領域のシ
リコン基板が露出した状態（第２，第３図ｆ）と
なり、続いてN+拡散が施こされてソース及びド
レインが設けられると共に第２シリコン膜６にも
N+拡散が施こされて低抵抗処理がなされ、浮動
ゲートMOSを備えた半導体装置が製造される。 First, a method of manufacturing a semiconductor device including a conventional floating gate MOS will be described with reference to FIGS. 2 and 3. Figures 2a to 2g show the manufacturing process of a double gate MOS, and Figures 3a to 3g show the manufacturing process of a single gate MOS. The double gate part and the single gate part are extracted and their cross sections are shown. In figure a 1
is a P-type silicon substrate, on which each transistor region has been positioned and field selective oxidation 2 has been performed, and a first polycrystalline silicon film 4 is grown on a first insulating oxide film 3. The first silicon film 4 is for providing a floating gate FG, and therefore, as shown in FIGS. 2 and 3b, the double gate portion is left covering the transistor region, but the single gate portion is removed by etching. be done. The first silicon film 4
N + diffusion (however, this is not necessary if the polycrystalline silicon film 4 has already grown containing N-type impurities) is performed, and the first silicon film 4 is subjected to a low-resistance treatment. Next, after removing the oxide film grown on the single gate portion and the first silicon film 4, a second oxide film 5 of a desired thickness is formed again and gate oxidation treatment is performed (FIGS. 2 and 3 c). . After forming the upper second oxide film 5, a second polycrystalline silicon film 6 is grown as shown in FIGS. An oxide film 7 is provided. The second polycrystalline silicon film 6 acts as a control gate in the double gate portion, and acts as a normal gate in the single gate portion. The third oxide film 7 and the second silicon film 6
is etched into a desired pattern, and the first silicon film 4 is exposed in the double silicon gate part, and the source and drain transistor regions are exposed in the single silicon gate part (second and third Figure e). In the double gate area, the first silicon film 4 is etched using the remaining third oxide film 7 and second silicon film 6 as a mask, and the silicon substrate in the source and drain regions of both transistor regions is exposed (second, FIG. 3 f), and then N + diffusion is performed to provide the source and drain, and also to the second silicon film 6.
N + diffusion is performed to provide a low resistance treatment and a semiconductor device with a floating gate MOS is manufactured.
上記従来の製造工程において、第２図ｆに示し
た第２シリコン膜６をマスクとして第１シリコン
膜４をエツチング除去する過程で、第１シリコン
膜４は既にＮ型不純物が注入されているため、エ
ツチング条件を選ぶことによつて第２シリコン膜
６を残留させた状態で第１シリコン膜４をエツチ
ングすることは可能である。しかし第１シリコン
膜４、第２シリコン膜６共に多結晶シリコンより
成るため、エツチング条件を選択することが難か
しく、また実際の作業においても寸法制御が難し
い等の問題があり、パターン精度を損う惧れがあ
つた。更にこのエツチング工程で同一チツプ内に
組込まれる１重ゲート部のソース部及びドレイン
となるシリコン基板が直接エツチング液に晒され
ることになり、表面が侵されて電気的特性に不良
をきたす惧れがあつた。 In the conventional manufacturing process described above, in the process of etching and removing the first silicon film 4 using the second silicon film 6 as a mask as shown in FIG. By selecting etching conditions, it is possible to etch the first silicon film 4 while leaving the second silicon film 6 remaining. However, since both the first silicon film 4 and the second silicon film 6 are made of polycrystalline silicon, it is difficult to select etching conditions, and there are also problems such as difficulty in controlling the dimensions in actual work, resulting in a loss of pattern accuracy. I was filled with fear. Furthermore, in this etching process, the silicon substrate that will become the source and drain parts of the single gate part incorporated into the same chip will be directly exposed to the etching solution, and there is a risk that the surface will be corroded and the electrical characteristics will deteriorate. It was hot.
本発明は上記従来の製造工程における問題点に
鑑みてなされたもので、第１多結晶シリコン膜を
従来に比べて薄く成長させ、第２多結晶シリコン
膜を所望パターンにエツチング加工した後熱酸化
の処理によつて自動的に第１多結晶シリコン膜の
位置決めがなされる半導体装置の製造方法を提供
するもので、次に第４図ａ〜ｈ及び第５図ａ〜ｈ
を用いて本発明を工程順に説明する。 The present invention has been made in view of the above-mentioned problems in the conventional manufacturing process, and involves growing a first polycrystalline silicon film thinner than before, etching a second polycrystalline silicon film into a desired pattern, and then thermally oxidizing it. The present invention provides a method for manufacturing a semiconductor device in which the first polycrystalline silicon film is automatically positioned by the process shown in FIGS. 4a-h and 5a-h.
The present invention will be explained step by step using the following.
第４図及び第５図は前記従来工程の説明と同様
に、同一半導体チツプ内に組込まれる２重Siゲー
トをもつ浮動ゲートMOS及び通常の１重Siゲー
トMOSの各工程におけるチツプ断面図を示す。 4 and 5 show chip cross-sectional views in each process of a floating gate MOS with double Si gates and a normal single Si gate MOS built into the same semiconductor chip, similar to the explanation of the conventional process described above. .
第４，第５図ａにおいて、既にトランジスタ領
域を決めるためフイールド部選択拡散１２がなさ
れたシリコン基板上に第１絶縁酸化膜１３を介し
て1000〜2000A°程度の膜厚に第１多結晶シリコ
ン膜１４が形成される。該第１シリコン膜１４は
前記従来例の膜厚に比べて1/3〜1/5程度に薄く設
けられる。第１シリコン膜１４は、記憶蓄積機能
をもたせるための浮動ゲートとして作用させる限
りにおいては、上記膜厚程度の薄いシリコン膜で
あつても充分に機能を果させることができ、電気
的に絶縁された状態で電荷蓄積用ゲートとして利
用される。上記第１シリコン膜１４は電荷蓄積機
能を持たせるために低抵抗にされるが、シリコン
膜１４の気相成長過程で予めリン等の不純物をド
ープさせるか、或いはシリコン膜１４の成長後
に、１重ゲート部を覆うシリコン膜をエツチング
除去し、残留した２重ゲート部を覆う第１シリコ
ン膜１４にN+拡散を施こして所望の抵抗値を備
えたシリコン膜１４を形成する。次に１重ゲート
部を覆う酸化膜及び第１シリコン膜１３上に新た
に成長した酸化膜を一旦完全に除去し、第４，第
５図ｃに示す如く再度酸化処理して所望膜厚の第
２絶縁酸化膜１５を２重ゲート部、１重ゲート部
を覆つて形成する。次に該第２絶縁酸化膜１５上
に第２多結晶シリコン膜１６及び該第２シリコン
膜１６を覆う第３絶縁酸化膜１７を成長させる。
上記第２シリコン膜１６は電気的接続がなされて
情報の書込み及び読み出し動作に利用されるコン
トロールゲートとなるもので、膜厚は4000〜
10000A°程度に比較的厚く設計される。上記第
３絶縁酸化膜１７及び第２シリコン膜１６は、２
重ゲート部及び１重ゲート部で夫々MOSトラン
ジスタのゲートとなる領域を残して第４，第５図
ｅに示す如くエツチング除去される。該工程によ
つて２重ゲート部は第１シリコン膜１４の一部が
露出し、１重ゲート部ではソース・ドレインとな
る領域のシリコン基板表面が露出する。上記工程
に続いてシリコン基板が酸化雰囲気に晒され、露
出した第１シリコン膜１４及び１重ゲート部のシ
リコン基板表面が熱酸化される。該熱酸化は第
４，第５図ｆに示す如く特に第１シリコン膜１４
の露出した部分が完全に酸化されるまで行われ
る。上記第１シリコン膜１４は予め薄く設計され
ており、且つＮ型不純物となるリン濃度が高くド
ープされているため酸化速度が速く、厚さ方向に
完全に酸化が進行した状態で第２シリコン膜１６
で覆われた部分の第１シリコン膜１４はわずかに
形状が縮少するだけで酸化されずに残り、結果と
して第２シリコン膜１６に対する第１シリコン膜
１４の自動位置合せがなされ、２重ゲート部及び
１重ゲート部のいずれもが、ゲート，ソース及び
ドレインの位置決めが自動的になされる。上記酸
化処理の後、ソース，ドレイン及び第２シリコン
膜を覆う酸化膜を第４，第５図ｇの如く除去し、
所定の不純物をドープして第４，第５図ｈに示す
N+拡散領域及び第２シリコン膜１４の低抵抗処
理を施こす。 In FIGS. 4 and 5 a, a first polycrystalline silicon film with a thickness of about 1000 to 2000 A is deposited on a silicon substrate on which selective diffusion 12 in the field area has already been performed to determine the transistor region, with a first insulating oxide film 13 interposed therebetween. A film 14 is formed. The first silicon film 14 is provided to be approximately 1/3 to 1/5 thinner than the film thickness of the conventional example. As long as the first silicon film 14 acts as a floating gate to provide a memory storage function, even a silicon film as thin as the above-mentioned film thickness can function satisfactorily, and is electrically insulated. In this state, it is used as a charge storage gate. The first silicon film 14 is made to have a low resistance in order to have a charge storage function, but it may be doped with an impurity such as phosphorus in advance during the vapor phase growth process of the silicon film 14, or it may be doped with 1 after the growth of the silicon film 14. The silicon film covering the double gate portion is removed by etching, and the first silicon film 14 covering the remaining double gate portion is subjected to N + diffusion to form a silicon film 14 having a desired resistance value. Next, the oxide film covering the single gate portion and the newly grown oxide film on the first silicon film 13 are completely removed, and then oxidized again as shown in FIGS. 4 and 5 c to obtain the desired film thickness. A second insulating oxide film 15 is formed to cover the double gate portion and the single gate portion. Next, a second polycrystalline silicon film 16 and a third insulating oxide film 17 covering the second silicon film 16 are grown on the second insulating oxide film 15 .
The second silicon film 16 is electrically connected and serves as a control gate used for information writing and reading operations, and has a film thickness of 4,000 to 4,000 nm.
It is designed to be relatively thick at around 10000A°. The third insulating oxide film 17 and the second silicon film 16 are
The double gate portion and the single gate portion are etched away, leaving regions that will become the gates of MOS transistors, respectively, as shown in FIGS. 4 and 5e. By this step, a part of the first silicon film 14 is exposed in the double gate part, and the silicon substrate surface in the region to be the source and drain is exposed in the single gate part. Following the above steps, the silicon substrate is exposed to an oxidizing atmosphere, and the exposed first silicon film 14 and the silicon substrate surface of the single gate portion are thermally oxidized. The thermal oxidation is performed particularly on the first silicon film 14 as shown in FIGS. 4 and 5 f.
The process is continued until the exposed areas are completely oxidized. The first silicon film 14 is designed to be thin in advance and is doped with a high concentration of phosphorus, which serves as an N-type impurity, so that the oxidation rate is fast, and the second silicon film is completely oxidized in the thickness direction. 16
The portion of the first silicon film 14 covered by the . The positioning of the gate, source, and drain is automatically performed for both the double gate section and the single gate section. After the above oxidation treatment, the oxide film covering the source, drain and second silicon film is removed as shown in FIGS. 4 and 5 g,
Doped with specified impurities and shown in Figures 4 and 5 h.
The N + diffusion region and the second silicon film 14 are subjected to low resistance treatment.
上記図ｆの熱酸化工程で、たとえ酸化が充分に
達成されなかつたとしても、図ｇのエツチング工
程で基板表面を覆う薄い第１絶縁酸化膜１３をも
除去する際に同時に除去されるため問題ない。 Even if sufficient oxidation is not achieved in the thermal oxidation process shown in Figure f above, there is a problem because it is removed at the same time when the thin first insulating oxide film 13 covering the substrate surface is also removed in the etching process shown in Figure G. do not have.
上記工程に続いて従来公知の配線処理等を経て
同一半導体チツプ内に２重構造の浮動ゲート
MOS及び通常の１重ゲートMOSを同時に製造す
ることができ、書き換え可能なROMを得ること
ができる。 Following the above process, a double structure floating gate is created within the same semiconductor chip through conventionally known wiring processing, etc.
A MOS and a normal single-gate MOS can be manufactured at the same time, and a rewritable ROM can be obtained.
以上本発明によれば、２重ゲート構造のMOS
製造において、所望パターンにエツチングされた
第２多結晶シリコン膜をマスクとして第１多結晶
シリコン膜から浮動ゲートを位置決めする際、第
１多結晶シリコン膜が予め薄い膜厚に設けられて
いるため、熱酸化処理によつて自動的に位置決め
がなされ、素子の設計が容易になると共に１重ゲ
ート部においてシリコン基板表面が直接エツチン
グ液に晒されることがないため、エツチング液等
基因する素子特性の劣化がなく、同一半導体基板
内に１重ゲート構造のMOSと２重ゲート構造の
MOSを互いに他方の特性を損うことなく共通の
プロセスを利用して作成することがき、簡単な工
程によつて製造が容易で且つ特性のすぐれた半導
体装置を得ることができる。 As described above, according to the present invention, a MOS with a double gate structure
During manufacturing, when positioning the floating gate from the first polycrystalline silicon film using the second polycrystalline silicon film etched into a desired pattern as a mask, since the first polycrystalline silicon film is previously provided with a thin film thickness, The thermal oxidation process automatically positions the device, making it easier to design the device, and since the silicon substrate surface is not directly exposed to the etching solution in the single gate area, deterioration of device characteristics caused by the etching solution is avoided. There is no MOS with a single gate structure and a MOS with a double gate structure on the same semiconductor substrate.
MOSs can be created using a common process without damaging the characteristics of the other, and a semiconductor device that is easy to manufacture and has excellent characteristics can be obtained through a simple process.
第１図は浮動ゲートMOS構造を示す断面図、
第２図ａ〜ｇ、第３図ａ〜ｇは従来の製造工程を
示す半導体チツプ断面図、第４図ａ〜ｈ及び第５
図ａ〜ｈは本発明による製造工程を示す半導体チ
ツプ断面図である。
１１：シリコン基板、１３：第１絶縁酸化膜、
１４：第１多結晶シリコン膜、１５：第２絶縁酸
化膜、１６：第２多結晶シリコン膜、１７：第３
絶縁酸化膜。
Figure 1 is a cross-sectional view showing a floating gate MOS structure.
Figures 2a to 3g and 3a to 3g are cross-sectional views of semiconductor chips showing conventional manufacturing processes, and Figures 4a to 5h and 5
Figures a to h are cross-sectional views of a semiconductor chip showing the manufacturing process according to the present invention. 11: silicon substrate, 13: first insulating oxide film,
14: first polycrystalline silicon film, 15: second insulating oxide film, 16: second polycrystalline silicon film, 17: third
Insulating oxide film.
Claims (1)
動ゲートを備えた２重SiゲートMOSとを組込ん
でなる半導体装置の製造方法において、 半導体基板に第１絶縁膜を介して薄い低抵抗第
１多結晶シリコン膜を形成する工程と、 ２重ゲートMOS領域を被う部分を除いて上記
第１多結晶シリコン膜を除去する工程と、 第２絶縁膜を介して厚い第２多結晶シリコン膜
及び第３絶縁膜を形成する工程と、 第２多結晶シリコン膜を所望パターンにエツチ
ングする工程と、 残留第２多結晶シリコン膜をマスクとして上記
第２絶縁膜をエツチングして１重ゲートMOS領
域のソース，ドレインのための半導体基板及び２
重ゲートMOS領域の第１多結晶シリコン膜を露
出させる工程と、 第２多結晶シリコン膜及び第３絶縁膜をマスク
に上記露出した第１多結晶シリコン膜を酸化する
工程と、 該酸化膜をエツチング除去して該除去部及び第
２多結晶シリコン膜に不純物を注入してソース，
ドレイン及び低抵抗シリコン膜を形成する工程と
からなり、浮動ゲートの自動位置決めがなされる
ことを特徴とするMOS半導体装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device in which a single gate MOS and a double Si gate MOS with a floating gate are incorporated in the same semiconductor chip, comprising the steps of: forming a thin, low-resistance first polycrystalline silicon film; removing the first polycrystalline silicon film except for a portion covering the double gate MOS region; and forming a thick second polycrystalline silicon film via a second insulating film. a step of forming a polycrystalline silicon film and a third insulating film; a step of etching the second polycrystalline silicon film into a desired pattern; etching the second insulating film using the remaining second polycrystalline silicon film as a mask; Semiconductor substrate and 2 for source and drain of heavy gate MOS region
a step of exposing the first polycrystalline silicon film in the heavy gate MOS region; a step of oxidizing the exposed first polycrystalline silicon film using the second polycrystalline silicon film and the third insulating film as a mask; After removing the etching, impurities are implanted into the removed portion and the second polycrystalline silicon film to form a source.
1. A method for manufacturing a MOS semiconductor device, comprising the steps of forming a drain and a low-resistance silicon film, and comprising automatic positioning of a floating gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4611878A JPS54137983A (en) | 1978-04-18 | 1978-04-18 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4611878A JPS54137983A (en) | 1978-04-18 | 1978-04-18 | Manufacture of mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54137983A JPS54137983A (en) | 1979-10-26 |
| JPS6135711B2 true JPS6135711B2 (en) | 1986-08-14 |
Family
ID=12738070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4611878A Granted JPS54137983A (en) | 1978-04-18 | 1978-04-18 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54137983A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5023681A (en) * | 1988-10-08 | 1991-06-11 | Hyundai Electronics Industries Co., Ltd. | Method for arranging EEPROM cells and a semiconductor device manufactured by the method |
| US5599727A (en) * | 1994-12-15 | 1997-02-04 | Sharp Kabushiki Kaisha | Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed |
-
1978
- 1978-04-18 JP JP4611878A patent/JPS54137983A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54137983A (en) | 1979-10-26 |
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