JPS57103347A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS57103347A
JPS57103347A JP18006380A JP18006380A JPS57103347A JP S57103347 A JPS57103347 A JP S57103347A JP 18006380 A JP18006380 A JP 18006380A JP 18006380 A JP18006380 A JP 18006380A JP S57103347 A JPS57103347 A JP S57103347A
Authority
JP
Japan
Prior art keywords
substrate
recess
type
region
type regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18006380A
Other languages
Japanese (ja)
Inventor
Masayuki Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP18006380A priority Critical patent/JPS57103347A/en
Publication of JPS57103347A publication Critical patent/JPS57103347A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology
    • H01L21/8249Bipolar and MOS technology

Abstract

PURPOSE:To simplify a bipolar MOS production process and to improve the integration and the characteristics of an element by diffusing a reverse conductive type high density region with a recess formed in a substrate and employing a substrate structure grown with a reverse conductive type epitaxial layer in the recess. CONSTITUTION:A window is, for example, opened at a PMOS and a bipolar element forming region of an oxidized film 37 on a p type substrate 1, recesses 38-40 are etched at the substrate 1, and n<+> region 41-43 are then diffused. Subsequently, n type regions 44-46 are epitaxially grown in the recess, and an oxidized film 37 is covered on the overall surface. Thereafter, B and phosphorus are sequentially selectively diffused to form p<+> type regions 44-51 and n<+> type regions 52-54, gate oxidized films 55, 56 are then formed, aluminum is, for example, deposited, is then patterned to form electrodes is then made composite with a bipolar MOS to form an IC. Thus, the production process can be simplified to provide a high density, and parasitic effect can be reduced to improve the characteristics of the element.
JP18006380A 1980-12-18 1980-12-18 Manufacture of integrated circuit Pending JPS57103347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18006380A JPS57103347A (en) 1980-12-18 1980-12-18 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18006380A JPS57103347A (en) 1980-12-18 1980-12-18 Manufacture of integrated circuit

Publications (1)

Publication Number Publication Date
JPS57103347A true JPS57103347A (en) 1982-06-26

Family

ID=16076823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18006380A Pending JPS57103347A (en) 1980-12-18 1980-12-18 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS57103347A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0404180A2 (en) * 1989-06-22 1990-12-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of making the same
US5198880A (en) * 1989-06-22 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of making the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0404180A2 (en) * 1989-06-22 1990-12-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of making the same
US5198880A (en) * 1989-06-22 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of making the same

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