JPS6064473A - Mos type transistor - Google Patents
Mos type transistorInfo
- Publication number
- JPS6064473A JPS6064473A JP17336683A JP17336683A JPS6064473A JP S6064473 A JPS6064473 A JP S6064473A JP 17336683 A JP17336683 A JP 17336683A JP 17336683 A JP17336683 A JP 17336683A JP S6064473 A JPS6064473 A JP S6064473A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type
- withstand voltage
- transistor
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000013078 crystal Substances 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract 2
- 239000010703 silicon Substances 0.000 claims abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 244000007853 Sarothamnus scoparius Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
本発明は、集積化に適した高耐圧ＭＯ８型トランジスタ
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage MO8 type transistor suitable for integration.
高耐圧ＭＯ８型トランジスタに関しては、従来より、第
１図に示すオフセットゲート構造ＭＯ８型トランジスタ
、第２図に示ず縦３ｆｆｉ ］） Ｓ Ａ構造ＭＯ８型
トランジスタ等が知られているが、次のような欠点を有
している。Regarding high-voltage MO8 type transistors, the offset gate structure MO8 type transistor shown in Fig. 1, the vertical 3ffi (not shown in Fig. 2) SA structure MO8 type transistor, etc. are conventionally known. It has some drawbacks.
縦形ＤＳＡ構造ＭＯ８＠’Ｊ）ランジスタに関しては、
その構造及び電流経路から集積化は適さない。Regarding the vertical DSA structure MO8@'J) transistor,
Its structure and current path make it unsuitable for integration.
又、オフセットゲート構造ＭＯ８型トランジスタに於て
り２、第１図に示すように、ドレイン−基板間の接合耐
圧を向上させるために、ドレイン拡散層＝１を、同極性
のウェル：２で囲んでいるが、ウェルの拡散層がシが大
きいため、面積が増大してし捷う。さらに、同一半導体
７！！：４ｉｖ上に高耐圧ＣＭ ＯＳ ＠’ｆｉ造を形
成しようとする七、第１図の構造？ ｐ 型Ｍ ＯＢ
）ランジスタにも応用しようとすれば、ドレインを囲む
ｐ型ウェルよりさらに深いｎ型ウェルを作らねばならず
、必然的に、ｐ型工ピタキシャル層：３も厚くしなけれ
ばならない。In addition, in an MO8 type transistor with an offset gate structure, as shown in Fig. 1, the drain diffusion layer 1 is surrounded by a well 2 of the same polarity in order to improve the junction breakdown voltage between the drain and the substrate. However, since the diffusion layer of the well is large, the area increases and becomes unwieldy. Furthermore, the same semiconductor 7! ! 7. The structure shown in Figure 1 when trying to form a high voltage CM OS @'fi structure on 4iv? p-type MOB
) If the present invention is to be applied to transistors, an n-type well must be made deeper than the p-type well surrounding the drain, and the p-type epitaxial layer 3 must also be made thicker.
さらに果梗化するためには、基板電極の取り出し方もく
ふうする必要がある。又、ドレインをウェルで回着なけ
れば、耐圧はイｉ・下してｔ、−Ｆう。本発明け、かか
る欠点を除去１７たものである。Furthermore, in order to make a fruit stalk, it is necessary to think about how to take out the substrate electrode. Also, if the drain is not wrapped around the well, the withstand voltage will be lowered to -F. The present invention eliminates these drawbacks.
本発明は、集積化に適し、従来の０ＭＯ８製造技術の延
長で作成でき、従来のセルファラインゲート構造ＭＯ８
型トランジスタ集積半導体装置と同一工程数で作成でき
る高耐圧ＭＯ８型トランジスタを提供することにある。The present invention is suitable for integration, can be created by extending the conventional 0MO8 manufacturing technology, and can be manufactured using the conventional self-line gate structure MO8.
An object of the present invention is to provide a high-voltage MO8 type transistor that can be manufactured in the same number of steps as a type transistor integrated semiconductor device.
以下、実施例に基づき本発明の詳細な説明する。Hereinafter, the present invention will be described in detail based on Examples.
婢３図に、本発明のトランジスタを用いｆｒＯＭＯ８梢
造の模式図を示す。低耐圧０Ｍ０Ｅ１回路部：３１と、
高耐圧ＣＭＯ８回路部が同時に形成されている。ｐ型半
導体基板：３３上にｎ型ウェル；５４を形成し、素子分
離、ソース、ドレイン、基＄２電位取り出し口として、
ｐ型拡散層；６５及びｎ散拡散層＝６６が形成されてい
る。低耐圧トランジスタのｐ型セルファライン拡散層及
び、高耐圧トランジスタのオフセラトル散拡ＨＩ＠：ｓ
７が同時に形成さね、同様に、ｎ型拡散層：３８も同様
に同時に形成される。ここで、高耐圧トランジスタのド
レイン拡散層が、オフセット拡散層でかこ筐れ、見かけ
上基板及びウェルとの接合の曲率半径が大きくなり、ド
レイ／耐圧が向上する。Figure 3 shows a schematic diagram of a frOMO8 structure using the transistor of the present invention. Low withstand voltage 0M0E1 circuit section: 31,
A high voltage CMO8 circuit section is formed at the same time. An n-type well 54 is formed on the p-type semiconductor substrate 33, and serves as an element isolation, source, drain, and base $2 potential extraction port.
A p-type diffusion layer 65 and an n-diffusion layer 66 are formed. P-type self-line diffusion layer of low breakdown voltage transistor and off cellat diffusion HI@:s of high breakdown voltage transistor
Similarly, the n-type diffusion layer 38 is also formed at the same time. Here, the drain diffusion layer of the high breakdown voltage transistor is surrounded by the offset diffusion layer, and the apparent radius of curvature of the junction with the substrate and well becomes large, improving the drain/breakdown voltage.
又、イ氏耐圧トランジスタ領域は、ドレイン引出ｆａｔ
１ｍをオフセット拡散層で囲号ないことより、面積の
′ｌ？？大ケ着ねかたい。In addition, the withstand voltage transistor region has a drain lead fat
Since 1m is not enclosed by an offset diffusion layer, the area 'l? ? I don't want to wear it.
第４図に、本発明ｌ特許請求の範囲（１）のＭｏｓｐｇ
トランジスタの構造枠４式図ｔ、第５図１に本発明ｌ特
許請求の範囲（２）の１Ａ０８型トランジスタの構造模
式図を示す。第４図と第５図全比べると、第５図には、
第４図に存在するドレイン拡散１ｉ′！ｌ： ５２のチ
ャネル仲１と反対方向にあるオフセット拡ｉＷハ巽力（
、チャネルとして活用されて（ｂること〃二わ力）Ｚ）
。このように、オフセットゲート構造ＭＯ８型トランジ
スタ全、ドレイン金中心に向かい合わせに３１成するこ
とにより、相対的に面＊！： （Ｚ） ＆ｉ少％） ｉ
ｉ、 ７’Ｊ’ Ｚ）ことが出来る。また、ドレイン拡
散層ヲメ゛フセット領域拡散層で聞Ａ７でいる六−め、
内１圧はイ琢：ｌ”１．、かい。FIG. 4 shows Mospg according to the present invention and claim (1).
A schematic diagram of the structure of the 1A08 type transistor according to claim (2) of the present invention is shown in FIG. Comparing Figures 4 and 5, Figure 5 shows the following:
Drain diffusion 1i′ present in FIG. 4! l: Offset expansion iW in the opposite direction to channel number 1 of 52 is Tatsumi (
, used as a channel (b thing〃two power)Z)
. In this way, all of the offset gate structure MO8 type transistors are formed facing each other with the drain gold center at the center, so that they are relatively plane*! : (Z) &i small%) i
i, 7'J' Z) can be done. In addition, the sixth part of the drain diffusion layer and the offset region diffusion layer are A7.
The inner pressure is 1.1.
第６図に、本発明特許請求の範囲（３）のＭＯ８型トラ
ンジスタの構造模式図を示す。８Ｐ′６図の破線；７６
内にドレイン引出しアルミ配線等があると、チャネル等
、電流経路内に電界が極部的に資財し、耐圧が以下して
し甘う。そのため、フィールド・プレート等、故意にき
剪った電位を４乏るアルミ等以外は、トランジスタの電
流経路内に大引ることは、耐圧のイバ下につながる。第
６図では、ドレイン電極のアルミによる引出しニア７を
、横方向に行かっている。FIG. 6 shows a schematic structural diagram of an MO8 type transistor according to claim (3) of the present invention. Broken line in figure 8P'6; 76
If there is a drain lead aluminum wiring inside, the electric field will be generated locally in the current path such as the channel, and the withstand voltage will be lowered. Therefore, if a field plate or other material other than aluminum, which has an intentionally shortened potential, is significantly drawn into the current path of the transistor, it will lead to a drop in the withstand voltage. In FIG. 6, the aluminum lead-out hole 7 of the drain electrode is shown in the lateral direction.
本発明は、高耐圧Ｍ ’ＯＳ型トランジスタに於て集積
化に適し、０ＭＯ８構造に出来、倶°耐圧回路部は面積
が増大せず、従来＋７．） ＣＭ ＯＳ製造技術の延長
で製造出来るなどすぐねた効果を有する。The present invention is suitable for integration in high-voltage M'OS type transistors, can be made into a 0MO8 structure, does not increase the area of the voltage-resistant circuit section, and is 7 times larger than conventional transistors. ) It has the immediate effect of being able to be manufactured by extending CMOS manufacturing technology.
賽だ本発明で、低濃変不純物拡散層を素子分能に用いて
いる１４０Ｓ型集積回路では、本発明のオフセット拡散
層として、イバ・＃度不純物拡散ｒ＠を用いることによ
り、同様の効果が得られる。According to the present invention, in the 140S type integrated circuit that uses a low concentration impurity diffusion layer for element performance, the same effect can be achieved by using a high concentration impurity diffusion r@ as the offset diffusion layer of the present invention. is obtained.
１だ本発明で、プラズマディスプレイ、ＫＬ。1. This invention is a plasma display, KL.
螢光表示管等、高蕾圧を必要とする表示装置のコントロ
ーラとＣ％ＡＯＳドライノ（を１チツブイヒすることが
容易となった。It has become easy to integrate a C% AOS Dryno controller with a display device that requires high pressure, such as a fluorescent display tube.
第１ＥＱｉ、ｔ、従来のオフセットゲート構造ＭＯ８型
トランジスタ。第２図は、従来のＡｔ４Ｙ：Ｕ ＳＡ
構造Ｍ ＯＳ型トランジスタ。箆５図は、木登［ｌ１４
のＭＯ８剰トランジスタを用（へ７１−ＣＭＯ８回路の
眉ｑ造模式図。第４図、第５図、第６図は、本発明のＫ
耐ＩＥ Ｍ Ｑ Ｓ型トランジスタの構造模式（ス１
゜１・・・ｎ＋ドレイン拡散層 ２・・・ｎ型ウェル６
・・・ｐ−エピタキシャル層
４・・・ｎ−オフセット拡散ｒ＠
５・・・ｎ＋ソース拡散層 ６・・・ｐ＋基板７・・・
電流経路 １１・・・ｎ＋基板１２・・・ｎ−エピタキ
シャルＩφ
１３・・・ｐ型ウェル １４・・・ｎ＋ソース４広散層
１５・・・電流経路 ５１・・・但・耐圧回路部。
５２・・・高耐圧回路部 ６９・・・ゲート４０・・・
ソース ４１・・・ドレイン５１．６１．７１ ・・・
ソース
５２．６２．７２ ・・・ドレイン
５５、６３．７３ ・・・オフセット拡散層５４、６４
．７４ ・・・素子分離拡散層５５、６５．７５ 、、
、ゲート
以 上
出願人 株式会社 諏訪粁工舎
代理人 弁理士 最上 務
￥１１
％２１１Ｄ
耶ろ（２）
塀
３／ う２
亮４図
１５２
１1st EQi,t, conventional offset gate structure MO8 type transistor; Figure 2 shows the conventional At4Y:USA
Structure MOS type transistor. Figure 5 of the broom is a tree climbing tree [l14
A schematic diagram of the 71-CMO8 circuit using the MO8 surplus transistor of the present invention.
Structural diagram of IE MQ S type transistor (S1
゜1...n+ drain diffusion layer 2...n type well 6
...p- epitaxial layer 4...n-offset diffusion r@5...n+ source diffusion layer 6...p+ substrate 7...
Current path 11...n+ substrate 12...n- epitaxial Iφ 13...p type well 14...n+ source 4 diffusion layer 15...current path 51...However, withstand voltage circuit section. 52... High voltage circuit section 69... Gate 40...
Source 41...Drain 51.61.71...
Source 52.62.72...Drain 55, 63.73...Offset diffusion layer 54, 64
．． 74...Element isolation diffusion layer 55, 65.75,,
, above the gate Applicant Suwa Kumo Kosha Co., Ltd. Agent Patent Attorney Mogami Tsutomu ¥11 %211D Yaro (2) Wall 3/ U2 Ryo 4 Figure 152 1
Claims (1)
セットゲート構造ＭＯ８型トランジスタに於て、ドレイ
ン拡散層を、オフセット領域拡散層でかこむこと′？Ｉ
−特徴とするＭ ＯＳ型トランジスタ。 （２、特許請求の範囲第１項記載のオフセラトゲ−トｍ
造ｙ ｏ ｓ型トランジスタを、ドレインを中心に向か
（八合わせに形威し、かつオフセット領域拡散贋でかこ
むことを特徴とするＭＯ８型トランジスタ。 （３）特許請求の範囲ｌ１ｌｌＬ１項及び第２項記載の
ＭＯ８型トランジスタに於て、チャネル等電流経路にア
ルミ等の配線が横ぎらないことを特徴とするＭＯ８型ト
ランジスタ。[Claims] (1) In an MO8 transistor with an offset gate structure formed on a silicon single crystal semiconductor substrate, the drain diffusion layer is surrounded by an offset region diffusion layer'? I
-Featured MOS transistor. (2. Off-ceratogate m according to claim 1)
An MO8 type transistor characterized in that a manufactured y o S type transistor is formed in an eight-aligned configuration with the drain facing the center, and is surrounded by an offset region diffusion layer. (3) Claims 11ll1L1 and 2 In the MO8 type transistor described in 1., the MO8 type transistor is characterized in that no wiring made of aluminum or the like crosses the current path such as the channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17336683A JPS6064473A (en) | 1983-09-20 | 1983-09-20 | Mos type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17336683A JPS6064473A (en) | 1983-09-20 | 1983-09-20 | Mos type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6064473A true JPS6064473A (en) | 1985-04-13 |
Family
ID=15959061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17336683A Pending JPS6064473A (en) | 1983-09-20 | 1983-09-20 | Mos type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6064473A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01235369A (en) * | 1988-03-16 | 1989-09-20 | Hitachi Ltd | Integrated-circuit semiconductor device |
| US5391904A (en) * | 1988-09-01 | 1995-02-21 | Fujitsu Limited | Semiconductor delay circuit device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS571258A (en) * | 1980-06-02 | 1982-01-06 | Matsushita Electronics Corp | Insulated gate semiconductor device |
| JPS5789257A (en) * | 1980-11-25 | 1982-06-03 | Nec Corp | Manufacture of insulation gate type field effect transistor |
-
1983
- 1983-09-20 JP JP17336683A patent/JPS6064473A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS571258A (en) * | 1980-06-02 | 1982-01-06 | Matsushita Electronics Corp | Insulated gate semiconductor device |
| JPS5789257A (en) * | 1980-11-25 | 1982-06-03 | Nec Corp | Manufacture of insulation gate type field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01235369A (en) * | 1988-03-16 | 1989-09-20 | Hitachi Ltd | Integrated-circuit semiconductor device |
| US5391904A (en) * | 1988-09-01 | 1995-02-21 | Fujitsu Limited | Semiconductor delay circuit device |
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