TWI740719B - High-voltage semiconductor device - Google Patents

Abstract

The present invention provides a high-voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distances between the top surface of an electrode of the first electrode structure and the top surface of the substrate has a first height and a second height which are different from each other.

Description

High-voltage semiconductor device

The present disclosure relates to a semiconductor device, and more particularly to a high-voltage semiconductor device.

With the improvement of semiconductor technology, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and related components on a single chip at the same time to reduce costs and improve operating efficiency. Transistor elements, which are often used to amplify current or voltage signals in circuits, as circuit oscillators, or as switching elements that control circuit switching operations, have been used as high-power elements or high-voltage with the advancement of semiconductor process technology. element. For example, a semiconductor device as a high-voltage component is placed between the internal circuit of the chip and the input/output (I/O) pins to prevent a large amount of charge from entering through the I/O pins in a very short time. Damage to the internal circuit.

In the current semiconductor device as a high-voltage element, in order to improve the breakdown voltage of the semiconductor device, in addition to introducing a drift region in the structure, a field plate can also be formed, such as The end of the gate is further extended above an isolation structure, so that the surface electric field at the end of the gate can be more dispersed. However, the existing high-voltage semiconductor devices are not satisfactory in all aspects and still need to be further improved to meet practical requirements.

One objective of the present disclosure is to provide a high-voltage semiconductor device having a field plate structure of various heights, which can avoid excessively increasing the lateral distance between the gate and the drain. Therefore, the high-voltage semiconductor device can effectively reduce the parasitic capacitance and increase the breakdown voltage, so as to improve the reliability of the high-voltage semiconductor device.

To achieve the above objective, a preferred embodiment of the present disclosure provides a high-voltage semiconductor device, which includes a substrate, a first well region, a second well region, a first insulating layer, a source electrode, a drain electrode, a first electrode structure, and a first electrode structure. Two electrode structure. The first well area is arranged in the substrate, and the first well area has a first conductivity type. The second well area is arranged in the substrate adjacent to the first well area, the second well area has a second conductivity type, and the second conductivity type is complementary to the first conductivity type. The first insulating layer is arranged on the first well area. The source electrode is arranged in the first well area, and the drain electrode is arranged in the second well area. The first electrode structure and the second electrode structure are disposed on the substrate, and the distance between the top surface of the electrode of the first electrode structure and the top surface of the substrate has a first height and a second height that are different from each other, Wherein, at least one of the first electrode structure and the second electrode structure is a gate structure.

The high-voltage semiconductor device of the present disclosure is provided with two or more independently arranged electrode structures. The electrode structure is, for example, a gate structure or a capacitor structure in which polysilicon, an insulating layer, and a conductor layer are sequentially stacked. The electrode structure and the substrate are provided with insulating layers with different thicknesses, different placement positions, or different degrees of coverage of the electrode structures, so that the distance between the top surface of each electrode structure and the top surface of the substrate, or the electrode structure The distance between the top surface of the substrate and the top surface of the substrate through different insulating layers, dielectric layers or combinations of insulating layers and dielectric layers can have a variety of different heights, so that the high-voltage semiconductor device can reach a variety of heights. Plate, and may have a significantly higher breakdown voltage.

In order to enable those who are familiar with the technical field of this disclosure to have a better understanding of this disclosure, the following specifically enumerates several preferred embodiments of this disclosure, together with the accompanying drawings, to describe in detail the content of the disclosure and what it intends to achieve. The effect.

The description of "the first part is formed on or above the second part" in this disclosure can mean "the first part is in direct contact with the second part", or it can mean "between the first part and the second part" There are other parts", so that the first part and the second part are not in direct contact. In addition, various embodiments in the present disclosure may use repeated component symbols and/or text annotations. The use of these repeated component symbols and text notes is to make the description more concise and clear, rather than to indicate the association between different embodiments and/or configurations. In addition, regarding the space-related narrative words mentioned in this disclosure, such as: "below", "above", "low", "high", "below", "above "", "below", "above", "bottom", "top" and similar words, for ease of description, their usage is to describe one component or feature and another (or more) components or The relative relationship of features. In addition to the swing outward shown in the diagram, these spatially related words are also used to describe the possible swing directions of the semiconductor device during the manufacturing process, use, and operation. For example, when the semiconductor device is rotated by 180 degrees, a component that was originally placed "above" other components will become "below" other components. Therefore, as the swing direction of the semiconductor device changes (rotated by 90 degrees or other angles), the space-related narrative used to describe its swing direction should also be interpreted in a corresponding way.

Although this disclosure uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and / Or the block should not be restricted by these words. These terms are only used to distinguish an element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they do not mean or represent the element. Any preceding ordinal number does not represent the order of arrangement of a component and another component, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or block discussed below can also be termed as the second element, component, region, layer, or block Of.

The term "about" or "substantially" mentioned in this disclosure usually means within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, the meaning of "approximate" or "substantial" can still be implied when there is no specific description of "approximate" or "substantial".

Please refer to FIG. 1, which shows a schematic diagram of the high-voltage semiconductor device 100 in the first embodiment of the disclosure. The high-voltage semiconductor device disclosed in the present disclosure refers to a semiconductor device with an operating voltage of approximately 20 to 40 volts (V), which is, for example, a laterally diffused metal oxide semiconductor transistor (LDMOS transistor), which can be a laterally diffused metal oxide semiconductor transistor (LDMOS transistor). N-type MOS transistor or laterally diffused P-type MOS transistor. In this embodiment, the high-voltage semiconductor device 100 is described with a laterally diffused N-type MOS transistor as an implementation mode, but not Limited by this.

First, as shown in FIG. 1, the high-voltage semiconductor device 100 includes a substrate 110, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, etc. , And a buried layer 120, a first well area 160, a second well area 130, etc., arranged in the substrate 110. Specifically, the first well region 160 has the first conductivity type (such as N-type), and a drain 165 is also formed in the first well region 160. The drain electrode 165 is, for example, a doped region also having the first conductivity type (such as N-type), and the doping concentration of the doping region is greater than the doping concentration of the first well region 160. On the other hand, the second well region 130 is arranged adjacent to the first well region 160 and has a second conductivity type (such as P-type), and the second conductivity type (such as P-type) is the same as the first conductivity type (such as N type) complementary. In this embodiment, the depth of the second well region 130 in the base 110 is, for example, slightly greater than the depth of the first well region 160 in the base 110. Thus, in the cross-sectional view shown in FIG. 1, the second well The area 130 may be arranged around the outer side of the first well area 160. In other words, from a top view (not shown), the second well area 130 surrounds the first well area 160 as a whole, but it is not limited to this.

A source 175 is formed in the second well region 130. In one embodiment, a third well region 170 may be further formed in the second well region 130. The third well region 170 also has the second conductivity type (such as P-type), and the third well region 170 is doped with The impurity concentration is preferably greater than the doping concentration of the second well region 130, and the source electrode 175 can be disposed in the third well region 170 and includes a first doping region 175a and a second doping region which are arranged adjacently. District 175b. Wherein, the first doped region 175a and the second doped region 175b respectively include the first conductivity type (such as N-type) and the second conductivity type (such as P-type), and the first doped region 175a and the second doped region 175a The doping concentration of the doped region 175b is preferably greater than the doping concentration of the second well region 130 or the third well region 170. As shown in Figure 1, the buried layer 120 is further disposed under the first well region 160 and the second well region 130 to serve as an isolation structure or anti-pinch- structure of the high-voltage semiconductor device 100. through) to prevent the current from punching through the bottom or inside of the substrate 110 directly from the first well region 160, thereby affecting the device performance of the high-voltage semiconductor device 100. In this embodiment, the buried layer 120 has, for example, the first conductivity type (such as N-type), and its doping concentration is preferably higher than the doping concentration of the first well region 160 or the second well region 130.

A body region 135 is also formed in the second well region 130. The body region 135 has the second conductivity type (such as P-type) and its doping concentration is greater than the doping concentration of the second well region 130. The base region 135 preferably does not directly contact the drain electrode 165 provided in the first well region 160 or does not directly contact the source electrode 175 also provided in the second well region 130. For example, a plurality of insulating structures 200 may be selected on the substrate 110. The insulating structure 200 is, for example, a field oxide (FOX) layer formed by a local oxidation of silicon (LOCOS) method. As shown in the figure), it can also be a shallow trench isolation (STI) formed by a deposition process. Wherein, an insulating structure 205 and an insulating structure 207 are respectively provided on two opposite sides of the base region 135, and the base region 135 and the drain electrode 165, or the base region 135 and the source electrode 175 can be separated by the insulating structure 205, as shown in first As shown in the figure. In this way, the body region 135 and the drain electrode 165 can be electrically isolated from each other, and the body region 135 can also be electrically connected to the first doped region 175a and the second doped region of the source electrode 175 through an external circuit (not shown). 175b, so that the base region 135 and the source electrode 175 can be equipotential with each other, but not limited to this. In other words, the base region 175 and each insulating structure 200 (such as the insulating structure 205 or the insulating structure 207) can present a ring structure, such as a rectangular frame, a circular ring, or a race track, from a top view (not shown). racetrack-shaped) and other suitable shapes, so that the base region 135 can be arranged around the periphery of the drain electrode 165 and the source electrode 175, while the insulating structure 205 and the insulating structure 207 are respectively surrounded inside and outside the base region 135, but their specific configuration This is not limited to this.

In addition, in an embodiment, the substrate 110 of the high-voltage semiconductor device 100 may further include an isolation region, and the isolation region may be externally connected to an isolation voltage (V _iso ) to isolate the high-voltage circuit inside the high-voltage semiconductor device 100. The isolation area includes, for example, a deep well area 150 surrounding the outside of the second well area 130 and an isolation area 155 located in the deep well area 150, as shown in FIG. 1, where the deep well area 150 and the isolation area 155, for example, both have The first conductivity type (such as N-type), and the doping concentration of the isolation region 155 is preferably greater than the doping concentration of the deep well region 150. In another embodiment, the substrate 110 of the high-voltage semiconductor device 100 may further include another base region 145, which is disposed in a fourth well region 140 and surrounds the high-voltage semiconductor device as a whole through the fourth well region 140 Outside of 100, the other base region 145 and the fourth well region 140 also have the second conductivity type (such as P-type), which can further isolate the high-voltage semiconductor device 100 and other active components, such as another high-voltage semiconductor device, etc. . Wherein, an insulating structure 201 and an insulating structure 203 can be further provided on two opposite sides of the other base region 145 to separate the aforementioned isolation region 155 by the insulating structure 201, as shown in FIG.

The high-voltage semiconductor device 100 of this embodiment can choose to provide two independent electrode structures between the source electrode 175 and the drain electrode 165. For example, the electrode structure may be, for example, a first gate structure 180 and a first gate structure 180 and a second gate structure separated from each other. The two-gate structure 190 is shown in Figure 1. In detail, the first gate structure 180 and the second gate structure 190 may respectively include a gate dielectric layer 181, 191, a gate electrode 183, 193 and surrounding the gate which are sequentially stacked on the substrate 110 The dielectric layers 181 and 191 and a side wall 185 and 195 outside the gate electrodes 183 and 193. Wherein, the gate electrodes 183 and 193 of the first gate structure 180 and the second gate structure 190 are separated from each other, and the interval g1 therebetween is, for example, about 0.1 to 0.2 micrometers (micrometer, μm), preferably 0.13 to 0.16 micrometers. , But not limited to this. Preferably, the gap g1 between the gate electrodes 183 and 193 of the first gate structure 180 and the second gate structure 190 is within the range of the first well region 160, and the gap g1 can be reduced as much as possible. As a result, the sidewalls 185 and 195 on one side of the first gate structure 180 and the second gate structure 190 can be directly adjacent to each other, as shown in FIG. 1, or they can be integrated with each other (not shown). With this configuration, the first gate structure 180 and the second gate structure 190 can respectively provide different voltages, thereby improving the device performance of the high-voltage semiconductor device 100.

Those with ordinary knowledge in the art should easily understand that the high-voltage semiconductor device disclosed in the present disclosure may also have other aspects, which are not limited to the foregoing, on the premise of meeting actual product requirements. For example, in the foregoing embodiment, while shortening the distance between the gate structure and the drain 165, as the gate structure is closer to the electric field strength of the drain 165, the breakdown voltage of the high-voltage semiconductor device 100 may be caused. reduce. Therefore, according to another embodiment of the present disclosure, a high-voltage semiconductor device is provided, which can reduce the parasitic capacitance between the gate structure and the drain while simultaneously increasing the breakdown voltage of the high-voltage semiconductor device, thereby improving the integrity The component reliability of the high-voltage semiconductor device is improved. The following will further describe other embodiments or variations of the high-voltage semiconductor device. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and the similarities are not repeated. In addition, the same elements in the embodiments of the present disclosure are labeled with the same reference numerals to facilitate comparison between the embodiments.

Please refer to FIG. 2, which is a schematic cross-sectional view of the high-voltage semiconductor device 300 in the second embodiment of the disclosure. The structure of the high-voltage semiconductor device 300 in this embodiment is substantially the same as that of the high-voltage semiconductor device 100 described in the first embodiment, and it also includes a substrate 110, a first well region 160, a second well region 130, a drain electrode 165, and a source electrode. 175, the base region 135, the insulating structure 200, etc., and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 300 can optionally add an insulating layer 301 to the first well region 160 between the source electrode 175 and the drain electrode 165, so that two independently arranged electrode structures (such as the first The first gate structure 380 and the second gate structure 390 shown in FIG. 2 may be completely or partially straddling the insulating layer 301.

In detail, the first gate structure 380 and the second gate structure 390 can also include a gate dielectric layer 381, 391, a gate electrode 383, 393, and a gate electrode that are sequentially stacked on the substrate 110. The polar dielectric layers 381, 391 and a side wall 385, 395 outside the gate electrodes 383, 393. Wherein, the first gate structure 380 is, for example, disposed at the junction of the first well area 160 and the second well area 130 (or, it can be regarded as the first gate structure 380 straddling the first well area 160 and the second well area. 130), and the second gate structure 390 is completely disposed within the first well region 160, so that the second gate structure 390 does not overlap the second well region 130, and the second gate structure 390 can Adjacent to the first gate structure 380. With this configuration, the gate electrodes 383 and 393 of the first gate structure 380 and the second gate structure 390 can be separated from each other, and the gap g2 between them is, for example, about 0.1 to 0.2 microns, preferably 0.13 to 0.16 microns , But not limited to this. Preferably, the gap g2 between the gate electrodes 383 and 393 of the first gate structure 380 and the second gate structure 390 may be located within the range of the first well region 160 and above the insulating layer 301, As shown in Figure 2. The insulating layer 301 is, for example, a dielectric material layer formed by a deposition process, such as a silicon oxide layer, but it is not limited thereto. The thickness of the insulating layer 301 is preferably greater than the thickness of the gate dielectric layers 381 and 391 of the first gate structure 380 or the second gate structure 390. However, those skilled in the art should understand the specific thickness of the insulating layer 301 Parameters such as oxygen content and density can be adjusted according to actual product requirements.

In this embodiment, the second gate structure 390 is completely straddling the insulating layer 301, so that the distance between the entire gate electrode 393 and the substrate 110 is H31 (that is, the top surface of the gate electrode 393 to the top of the substrate 110). The distance between the surfaces) is a certain value; and the first gate structure 380 is partly arranged on the insulating layer 301, and the other part is directly arranged on the substrate 110, so that the gate electrode 383 of this part (such as the straddle The distance H32 between the part on the insulating layer 301 and the substrate 110 and the distance H33 between the gate electrode 383 of the other part (such as the part directly disposed on the substrate 110) and the substrate 110 can be mutually different. For example, the top surface of the gate electrode 393 of the second gate structure 390 passes through the insulating layer 301 and the distance H31 from the top surface of the substrate 110, and the top surface of the gate electrode 383 of the first gate structure 380 is directly to the substrate 110 The distance H33 from the top surface and the distance H32 from the top surface of the gate electrode 383 of the first gate structure 380 to the top surface of the substrate 110 through the insulating layer 301 can reach field-plates of different heights, thereby reducing the surface The electric field (reduced surface field, RESURF) helps to increase the breakdown voltage of the high-voltage semiconductor device 300.

Furthermore, refer to FIG. 3, which is a schematic cross-sectional view of the high-voltage semiconductor device 400 in the third embodiment of the present disclosure. The structure of the high-voltage semiconductor device 400 in this embodiment is substantially the same as that of the high-voltage semiconductor device 300 described in the foregoing second embodiment, and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 400 selects the first gate structure 480 to be directly disposed on the substrate 110, and the second gate structure 490 is partially disposed on an insulating layer 401. The insulating layer 401 of this embodiment is also a dielectric material layer formed by a deposition process, such as a silicon oxide layer, and various parameters of the insulating layer 401 can also be adjusted correspondingly according to actual product requirements. The thickness of the insulating layer 401 is preferably greater than the thickness of the gate dielectric layers 481 and 491 of the first gate structure 480 or the second gate structure 490, but it is not limited thereto.

In detail, the first gate structure 480 and the second gate structure 490 can also include a gate dielectric layer 481, 491, a gate electrode 483, 493, and a gate electrode 483, 493 that are sequentially stacked on the substrate 110, respectively. The polar dielectric layers 481 and 491 and a side wall 485 and 495 outside the gate electrodes 483 and 493. In this embodiment, the first gate structure 480 is also arranged at the junction of the first well area 160 and the second well area 130, and the second gate structure 490 is completely arranged in the first well area 160. And it is adjacent to the first gate structure 480. In this setting, the gate electrodes 483 and 493 of the first gate structure 480 and the second gate structure 490 are also separated from each other, and the gap g3 therebetween is, for example, about 0.1 to 0.2 microns, preferably 0.13 to 0.16 Micron, but not limited to this. It should be noted that in this embodiment, due to the small gap g3, the sidewalls 485 and 495 on the side of the first gate structure 480 and the second gate structure 490 can be integrated with each other. At the same time, the first gate The gate dielectric layers 481 and 491 of the pole structure 480 and the second gate structure 490 can also be connected to each other to present an integrally formed state, as shown in FIG. 3. In this way, the gap g3 between the gate electrodes 483 and 493 of the first gate structure 480 and the second gate structure 490 can be located on the gate dielectric layers 481 and 491 and still be located in the first well region 160 Within the range, as shown in Figure 3.

In addition, a part of the second gate structure 490 is arranged across the insulating layer 401, and the other part is directly arranged on the substrate 110, so that the gate electrode 493 of this part (such as the part arranged across the insulating layer 401) The distance H41 to the substrate 110 and the distance H42 from the other part of the gate electrode 493 (such as the part directly disposed on the substrate 110) to the substrate 110 may be different from each other. For example, the distance H42 from the top surface of the gate electrode 483 of the first gate structure 480 to the top surface of the substrate 110, the distance H42 from the top surface of the gate electrode 493 of the second gate structure 490 to the top surface of the substrate 110, and The distance H41 from the top surface of the gate electrode 493 of the second gate structure 490 to the top surface of the substrate 110 through the insulating layer 401 can reach two different heights of field plates, which also helps to increase the breakdown voltage of the high-voltage semiconductor device 400 .

Next, please refer to FIG. 4, which is a schematic cross-sectional view of the high-voltage semiconductor device 500 in the fourth embodiment of the present disclosure. The structure of the high-voltage semiconductor device 500 in this embodiment is substantially the same as the high-voltage semiconductor device 300 described in the second embodiment or the high-voltage semiconductor device 400 described in the third embodiment, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 500 chooses to add an insulating layer 501 between the source electrode 175 and the drain electrode 165. The insulating layer 501 is, for example, a field oxidation formed by the local silicon oxidation method. The manufacturing process can optionally be performed together with the manufacturing process of the insulating structure 200 described above. Thus, the insulating layer 501 can be partially disposed in the substrate 110 and partially protruding from the top surface of the substrate 110, and two independently disposed electrode structures (such as the first gate structure 580 and the second gate structure shown in FIG. 4 590) The insulating layer 501 can be completely or partially straddled in the subsequent manufacturing process.

In detail, the first gate structure 580 and the second gate structure 590 can also include a gate dielectric layer 581, 591, a gate electrode 583, 593, and a gate electrode 583, 593 that are sequentially stacked on the substrate 110. The polar dielectric layers 581, 591 and a side wall 585, 595 outside the gate electrodes 583, 593. Wherein, the first gate structure 580 is also arranged at the junction of the first well area 160 and the second well area 130, while the second gate structure 590 is completely arranged in the first well area 160 and is adjacent to the first well area. A gate structure 580. With this arrangement, the gate electrodes 583 and 593 of the first gate structure 580 and the second gate structure 590 can be separated from each other, and the gap g4 therebetween is, for example, about 0.1 to 0.2 microns, preferably 0.13 to 0.16 microns. But not limited to this. Preferably, the gap g4 between the gate electrodes 583 and 593 of the first gate structure 580 and the second gate structure 590 is also located within the range of the first well region 160 and is located on the insulating layer 501 , As shown in Figure 4.

It should be noted that, in this embodiment, the second gate structure 590 is completely straddling the insulating layer 501, so that the overall distance between the gate electrode 593 and the substrate 110 is H51 (that is, the gate electrode 593 The distance between the top surface and the top surface of the substrate 110) is a certain value; and the first gate structure 580 is partly arranged on the insulating layer 501, and the other part is directly arranged on the substrate 110, so that the gate of this part The distance H51 between the electrode 583 (e.g., the part that straddles the insulating layer 501) and the substrate 110 and the other part of the gate electrode 583 (e.g., the part directly provided on the substrate 110) to the substrate 110 The distance H52 between them may be different from each other. For example, the top surface of the gate electrode 583 of the first gate structure 580 passes through the insulating layer 501 and the distance H51 to the top surface of the substrate 110, and the top surface of the gate electrode 583 of the first gate structure 580 is directly to the top surface of the substrate 110 The distance H52 of the second gate structure 590 and the distance H52 of the second gate structure 590 to the top surface of the substrate 110 through the insulating layer 501 can reach two different heights of field plates, which can also enable the high voltage semiconductor device 500 to have a higher breakdown voltage.

Furthermore, refer to FIG. 5, which shows a cross-sectional schematic diagram of the high-voltage semiconductor device 600 in the fifth embodiment of the present disclosure. The structure of the high-voltage semiconductor device 600 in this embodiment is substantially the same as that of the high-voltage semiconductor device 500 described in the foregoing fourth embodiment, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 600 selects the first gate structure 680 to be directly disposed on the substrate 110, so that the second gate structure 690 is partially disposed on an insulating layer 601. The insulating layer 601 of this embodiment is also a field oxide layer formed by the partial silicon oxidation method, and the manufacturing process can be optionally performed together with the manufacturing process of the insulating structure 200 described above.

The first gate structure 680 and the second gate structure 690 can also include a gate dielectric layer 681, 691, a gate electrode 683, 693 and a surrounding gate dielectric layer sequentially stacked on the substrate 110, respectively 681, 691 and a side wall 685, 695 outside the gate electrodes 683, 693. In this embodiment, the first gate structure 680 is also arranged at the junction of the first well area 160 and the second well area 130, and the second gate structure 690 is completely arranged in the first well area 160. And it is adjacent to the first gate structure 680. With this configuration, the gate electrodes 683 and 693 of the first gate structure 680 and the second gate structure 690 can also be separated from each other, and the gap g5 therebetween is, for example, about 0.1 to 0.2 microns, preferably 0.13 to 0.16 microns , But not limited to this. It should be noted that in this embodiment, due to the small gap g5, the sidewalls 685 and 695 on the side of the first gate structure 680 and the second gate structure 690 can be integrated with each other to fill the gap g5. At the same time, the gate dielectric layers 681 and 691 of the first gate structure 680 and the second gate structure 690 can also be connected to each other to present an integrally formed state, as shown in FIG. 5. In this way, the gap g5 between the gate electrodes 683 and 693 of the first gate structure 680 and the second gate structure 690 can be located on the gate dielectric layers 681 and 691 and still be located in the first well region 160 Within the range, as shown in Figure 5.

In addition, a part of the second gate structure 690 is arranged across the insulating layer 601, and the other part is directly arranged on the substrate 110, so that the part of the gate electrode 693 (such as the part arranged across the insulating layer 601) The distance H61 to the substrate 110 and the distance H62 from the other part of the gate electrode 693 (for example, the part directly disposed on the substrate 110) to the substrate 110 may be different from each other. For example, the distance between the top surface of the gate electrode 683 of the first gate structure 680 and the top surface of the substrate 110 is H62, and the distance between the top surface of the gate electrode 693 of the second gate structure 690 and the top surface of the substrate 110 is H62, And the distance H61 from the second gate structure 690 to the top surface of the substrate 110 through the insulating layer 601 can reach two different heights of field plates, which also helps to increase the breakdown voltage of the high-voltage semiconductor device 600.

Then, please refer to FIG. 6, which is a schematic cross-sectional view of the high-voltage semiconductor device 700 in the sixth embodiment of the disclosure. The structure of the high-voltage semiconductor device 700 in this embodiment is substantially the same as that of the high-voltage semiconductor device 400 described in the foregoing third embodiment, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 700 chooses to add an insulating layer 701 between the source electrode 175 and the drain electrode 165, so that the second gate structure 790 can partially straddle an insulating layer 701. Above. Wherein, the insulating layer 701 is also a dielectric material layer formed by the deposition process, such as a silicon oxide layer, etc., and various parameters of the insulating layer 701 can also be adjusted correspondingly according to actual product requirements. Moreover, the high-voltage semiconductor device 700 of this embodiment may additionally include another electrode structure, such as a capacitor structure 770, which is disposed on the insulating layer 701 and the second gate structure 790.

In detail, the first gate structure 780 and the second gate structure 790 may also include a gate dielectric layer 781, 791, a gate electrode 783, 793, and a gate electrode 783, 793 that are sequentially stacked on the substrate 110, respectively. The polar dielectric layers 781 and 791 and a side wall 785 and 795 outside the gate electrodes 783 and 793. The first gate structure 780 is also arranged at the junction of the first well area 160 and the second well area 130, while the second gate structure 790 is completely arranged in the first well area 160 and is adjacent to the first gate. Structure 780. Under this arrangement, the gate electrodes 783 and 793 of the first gate structure 780 and the second gate structure 790 are also separated from each other, and the interval g6 between them is, for example, located within the range of the first well region 160, as in the first gate structure. As shown in Figure 6, it is generally about 0.1 to 0.2 microns, preferably 0.13 to 0.16 microns, but not limited to this.

In this embodiment, an insulating layer 703 is further formed above the second gate structure 790, and a part of the insulating layer 703 covers the first well region 160, the insulating layer 701, and the second gate structure 790 below, such as Shown in Figure 6. The insulating layer 703 is, for example, a dielectric material layer formed by another deposition process, such as a silicon oxide layer, but not limited to this. Preferably, the manufacturing process of the insulating layer 703 can be performed together with the general manufacturing process of the high-voltage semiconductor device 700, for example, a protective layer (not shown) that partially shields the substrate 110 to avoid the formation of metal silicide can be formed together. However, it can also be formed through other processes. Then, a dielectric layer (MIP insulator) 771 and a conductive layer 773 are sequentially formed on the insulating layer 703, partially overlapping the second gate structure 790 below. In one embodiment, the conductive layer 773 can provide different voltages to achieve different functions. For example, when the conductive layer 773 is electrically connected to the source electrode 175 through an external circuit (not shown), the conductive layer 773, the dielectric layer 771, and the gate electrode 793 of the second gate structure 790 can be formed together The capacitor structure 770 is, for example, a capacitor structure (metal-insulator-polysilicon, MIP) formed by stacking polysilicon, an insulating layer, and a conductive layer. _{With this configuration, the breakdown voltage can be increased, and the parasitic capacitance (C gd} ) between the gate structure of the high-voltage semiconductor device 700 and the drain 165 can be reduced. On the other hand, when the conductive layer 773 is connected to the first gate electrode 780 through another external circuit (not shown), the on-resistance of the semiconductor device 700 can be reduced.

Thereby, the second gate structure 790 partially straddling the insulating layer 701 can also achieve two heights of field plate effect. For example, it can include the top surface of the gate electrode 793 of the second gate structure 790 directly to the substrate 110. The distance H71 from the top surface and the different field plates reached by the distance H72 from the top surface of the gate electrode 793 of the second gate structure 790 through the insulating layer 701 to the top surface of the substrate 110. In addition, the conductive layer 773 of the capacitor structure 770 passes through the dielectric layer 771 and the distance H73 from the insulating layer 703 to the top surface of the substrate 110, or the conductive layer 773 of the capacitor structure 770 passes through the dielectric layer 771, the insulating layer 703, and the insulating layer 701. The distance H74 from the surface of the first well region 160 can achieve field plate effects of different heights, so that the breakdown voltage of the high-voltage semiconductor device 700 of this embodiment can be further increased.

Please refer to FIG. 7 again, which is a schematic cross-sectional view of the high-voltage semiconductor device 800 in the seventh embodiment of the disclosure. The structure of the high-voltage semiconductor device 800 in this embodiment is substantially the same as that of the high-voltage semiconductor device 300 described in the aforementioned second embodiment, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 800 chooses to add an insulating layer 801 between the source electrode 175 and the drain electrode 165, and the insulating layer 801 may further include two parts 801a, 801b separated from each other. , So that two independently arranged electrode structures (such as the gate structure 880 and the capacitor structure 870 shown in FIG. 7) can be separately arranged across the insulating layer 801, thereby achieving more field plate effects of different heights. Wherein, the insulating layer 801 is also a dielectric material layer formed by the deposition process, such as a silicon oxide layer, etc., and then two parts 801a and 801b are formed by a patterning process.

In detail, the gate structure 880 is disposed on the junction of the first well region 160 and the second well region 130, and partially straddles the second portion 801b of the insulating layer 801. As shown in FIG. 7, the gate structure 880 includes a gate dielectric layer 881, a gate electrode 883, and a gate dielectric layer 881 and a gate electrode 883 that are sequentially stacked on the substrate 110.温子885。 Side wall 885. On the other hand, the capacitor structure 870 is composed of, for example, a conductive layer 773, a dielectric layer 771, and an electrode structure 883. The electrode structure 870 is completely disposed in the first well region 160 and partially overlaps the gate structure 880 and the insulating layer below. The second part 801b of the layer 801. In addition, in this embodiment, an insulating layer 803 is further formed between the capacitor structure 870 and the insulating layer 801 to partially cover the first well 160 and the first portion 801a of the insulating layer 801 below. The insulating layer 803 is also a dielectric material layer formed by another deposition process, such as a silicon oxide layer, and can optionally partially shield the substrate 110 to avoid forming a protective layer (not shown) of metal silicide. And formed, or formed separately.

In this embodiment, the distance H81 from the top surface of the gate electrode 883 of the gate structure 880 directly to the top surface of the substrate 110, and the top surface of the gate electrode 883 of the gate structure 880 passes through the second portion 801b of the insulating layer 801 to reach The distance H82 between the top surface of the substrate 110 can reach the field plate effect of two heights (ie, H81, H82). In addition, the top surface of the conductive layer 873 of the capacitor structure 870 passes through the dielectric layer 871 and the second part 801b of the insulating layer 801 to the distance H83 from the top surface of the substrate 110. The conductive layer 873 of the capacitor structure 870 is arranged across the gate structure 880. The top surface of the upper part passes through the dielectric layer 871 and the second part 801b of the insulating layer 801 and the distance H84 from the surface of the substrate 110. The conductor layer 873 of the capacitor structure 870 passes through the dielectric layer 871, the insulating layer 803 and the insulating layer 801. The distance H85 from the first part 801a to the surface of the substrate 110 can provide at least five field plates of different heights (namely H81, H82, H83, H84, and H85), effectively reducing the surface electric field (RESURF), making the embodiment of The breakdown voltage of the high-voltage semiconductor device 800 can be further increased.

Please refer to FIG. 8, which is a schematic cross-sectional view of the high-voltage semiconductor device 900 in the eighth embodiment of the disclosure. The structure of the high-voltage semiconductor device 900 in this embodiment is substantially the same as that of the high-voltage semiconductor device 700 described in the aforementioned sixth embodiment, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 900 chooses to provide an insulating layer 901 between the source electrode 175 and the drain electrode 165. The insulating layer 901 may include two parts 901a, 901b separated from each other, so that three independent The provided electrode structures (such as the first gate structure 980, the second electrode structure 990, and the capacitor structure 970 shown in FIG. 8) can be respectively arranged across the two parts 901a, 901b of the insulating layer 901 to provide a conductive layer 973 It can have a gradual height to reach more field plates of different heights to reduce the surface electric field.

In detail, the first gate structure 980 and the second gate structure 990 may also include a gate dielectric layer 981, 991, a gate electrode 983, 993 and a gate electrode 983 and 993 stacked on the substrate 110 in sequence. The polar dielectric layers 981, 991 and a side wall 985, 995 outside the gate electrodes 983, 993. The first gate structure 980 is also arranged at the junction of the first well area 160 and the second well area 130, while the second gate structure 990 is completely arranged in the first well area 160, and partly on the insulating layer. The second part 901b of 901 is on and adjacent to the first gate structure 980, as shown in FIG. 8. Under this arrangement, the gate electrodes 983 and 993 of the first gate structure 980 and the second gate structure 990 are also separated from each other, and the gap g7 therebetween is, for example, located within the range of the first well region 160, and generally The upper limit is about 0.1 to 0.2 microns, preferably 0.13 to 0.16 microns, but it is not limited thereto.

In addition, in this embodiment, an insulating layer 903 is further formed to partially cover the first well region 160 below and the first portion 901a of the insulating layer 901. The insulating layer 903 is also a dielectric material layer formed by another deposition process, such as a silicon oxide layer, and can optionally partially shield the substrate 110 to avoid forming a protective layer (not shown) of metal silicide. And formed, or formed separately. After that, a capacitor structure 970 is formed on the insulating layer 903, for example, a conductive layer 973, a dielectric layer 971 and an electrode structure 993 are jointly formed. The capacitor structure 970 is completely disposed within the range of the first well region 160, so that it can completely overlap the insulating layer 903 and the first part 901a of the insulating layer 901 disposed below, and partially overlap the second part 901b of the insulating layer 901 And the second gate structure 990, as shown in FIG. 8.

In this embodiment, the distance H91 from the top surface of the gate electrode 993 of the gate structure 990 directly to the top surface of the substrate 110, and the top surface of the gate electrode 993 of the gate structure 990 passes through the second portion 901b of the insulating layer 901 to reach The distance H92 from the top surface of the substrate 110 can also achieve field plate effects of two heights (ie, H91 and H92). In addition, the conductive layer 973 of the capacitor structure 970 passes through the dielectric layer 971 and the second portion 901b of the insulating layer 901 and then the distance H93 to the top surface of the substrate 110, and the conductive layer 973 of the capacitor structure 970 passes through the dielectric layer 971 and the insulating layer 903 to The distance from the top surface of the substrate 110 is H94. The top surface of the portion where the conductor layer 973 of the capacitor structure 970 straddles the gate structure 990 passes through the dielectric layer 971 and the second part 901b of the insulating layer 901 to the top surface of the substrate 110. The distance H95, the conductor layer 973 of the capacitor structure 970 through the dielectric layer 971, the insulating layer 903 and the first part 901a of the insulating layer 901 and the distance H96 from the surface of the substrate 110 can provide at least six different heights (ie H91, H92, The field plates of H93, H94, H95, and H96) effectively reduce the surface electric field, so that the breakdown voltage of the high-voltage semiconductor device 900 of this embodiment can be further increased.

Generally speaking, the high-voltage semiconductor device of the present disclosure is provided with two or more independently arranged electrode structures, such as a gate structure or a capacitor structure in which polysilicon, an insulating layer, and a conductor layer are sequentially stacked. The electrode structure and the substrate are provided with insulating layers with different thicknesses, different placement positions, or different degrees of coverage of the electrode structures, so that the distance between the top surface of each electrode structure and the top surface of the substrate, or the electrode structure The distance between the top surface of the substrate and the top surface of the substrate through different insulating layers, dielectric layers or combinations of insulating layers and dielectric layers can have a variety of different heights, so that the high-voltage semiconductor device can reach a variety of heights. Plate effect, and has a significantly higher breakdown voltage. Under the configuration of the present disclosure, the current gain can be effectively increased without increasing the lateral length of the field plate structure, so that the high-voltage semiconductor device can obtain a higher breakdown voltage. In addition, the present disclosure can also alleviate the problem of excessively high parasitic capacitance between the gate and the drain, and improve the component reliability and device performance of the high-voltage semiconductor device. Therefore, the configuration of the present disclosure can be applied to various high-voltage semiconductor devices. Although the laterally diffused N-type metal oxide semiconductor transistor is used as an implementation mode for description in the foregoing embodiment, it should be easily understood by those skilled in the art. In other embodiments, it can also be applied to other different types of high-voltage semiconductor devices. The foregoing descriptions are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present disclosure should fall within the scope of the present disclosure.

100, 300, 400, 500, 600, 700, 800, 900: high-voltage semiconductor devices 110: Base 120: Buried layer 130: The second well area 135: matrix area 140: The fourth well area 145: matrix area 150: Deep Well District 155: Quarantine 160: The first well area 165: Drain 170: The third well area 175: Source 175a: the first doped region 175b: second doped region 180, 380, 480, 580, 680, 780, 880, 980: first gate structure 181, 381, 481, 581, 681, 781, 881, 981: gate dielectric layer 183, 383, 483, 583, 683, 783, 883, 983: gate electrode 185, 385, 485, 585, 685, 785, 885, 985: side wall 190, 390, 490, 590, 690, 790, 990: second gate structure 191, 391, 491, 591, 691, 791, 991: gate dielectric layer 193, 393, 493, 593, 693, 793, 993: gate electrode 195, 395, 495, 595, 695, 795, 995: side wall 200, 201, 203, 205, 207: insulation structure 301: Insulation layer 401: Insulation layer 501: Insulation layer 601: Insulation layer 701: insulating layer 703: Insulation layer 770: Capacitor structure 771: Dielectric layer 773: A capacitor structure in which polysilicon, an insulating layer, and a conductor layer are sequentially stacked 801: Insulation layer 801a: Part One 801b: Part Two 803: Insulation layer 870: Electrode structure 871: Dielectric layer 873: A capacitor structure in which polysilicon, an insulating layer, and a conductor layer are sequentially stacked 901: Insulation layer 901a: Part One 901b: Part Two 903: Insulation layer 970: Electrode structure 971: Dielectric layer 973: Capacitor structure in which polysilicon, insulating layer and conductor layer are sequentially stacked g1, g2, g3, g4, g5, g6, g7: distance H31, H32, H33: distance H41, H42: distance H51, H52: distance H61, H62: distance H71, H72, H73, H74: distance H81, H82, H83, H84, H85: distance H91, H92, H93, H94, H95, H96: distance

FIG. 1 is a schematic cross-sectional view of the high-voltage semiconductor device in the first embodiment of the disclosure. FIG. 2 is a schematic cross-sectional view of the high-voltage semiconductor device in the second embodiment of the disclosure. FIG. 3 is a schematic cross-sectional view of the high-voltage semiconductor device in the third embodiment of the disclosure. FIG. 4 is a schematic cross-sectional view of the high-voltage semiconductor device in the fourth embodiment of the disclosure. FIG. 5 is a schematic cross-sectional view of the high-voltage semiconductor device in the fifth embodiment of the disclosure. FIG. 6 is a schematic cross-sectional view of the high-voltage semiconductor device in the sixth embodiment of the disclosure. FIG. 7 is a schematic cross-sectional view of the high-voltage semiconductor device in the seventh embodiment of the disclosure. FIG. 8 is a schematic cross-sectional view of the high-voltage semiconductor device in the eighth embodiment of the disclosure.

110: Base

120: Buried layer

130: The second well area

135: matrix area

140: The fourth well area

145: matrix area

150: Deep Well District

155: Quarantine

160: The first well area

165: Drain

170: The third well area

175: Source

175a: the first doped region

175b: second doped region

200, 201, 203, 205, 207: insulation structure

300: High-voltage semiconductor device

301: Insulation layer

380: The first gate structure

381: gate dielectric layer

383: gate electrode

385: side wall

390: second gate structure

391: gate dielectric layer

393: gate electrode

395: side wall

g2: distance

H31, H32, H33: distance

Claims (12)

A high-voltage semiconductor device, including: A base A first well area arranged in the substrate, the first well area having a first conductivity type; A second well region arranged in the substrate adjacent to the first well region, the second well region having a second conductivity type, the second conductivity type being complementary to the first conductivity type; A first insulating layer arranged on the first well area; A source electrode is arranged in the second well area; A drain pole is set in the first well area; and A first electrode structure and a second electrode structure are disposed on the substrate, and the distance between the top surface of the electrode of the first electrode structure and the top surface of the substrate has a first height and a second height that are different, Wherein, at least one of the first electrode structure and the second electrode structure is a gate structure. The high-voltage semiconductor device described in item 1 of the scope of patent application, wherein the first electrode structure covers a part of the first insulating layer and is located on the boundary between the first well region and the second well region, and the first electrode structure The two electrode structure is located on the first well area. According to the high-voltage semiconductor device described in claim 1, wherein the first electrode structure is located on the first well region and covers a part of the first insulating layer. According to the high-voltage semiconductor device described in item 2 or item 3 of the scope of patent application, the electrodes of the first electrode structure and the second electrode structure are separated from each other. According to the high-voltage semiconductor device described in item 2 or item 3 of the scope of patent application, the second electrode structure partially overlaps the first electrode structure. According to the high-voltage semiconductor device described in claim 5, the second electrode structure includes a capacitor structure, and the capacitor structure includes a gate electrode, a dielectric layer, and a conductor layer stacked in sequence. According to the high-voltage semiconductor device described in claim 6, wherein the first electrode structure and the second electrode structure share the gate electrode. The high-voltage semiconductor device described in claim 6, wherein the distance between the top surface of the electrode of the second electrode structure and the top surface of the substrate includes a third height, a fourth height, and a fifth height. Height, wherein the first height, the second height, the third height, the fourth height, and the fifth height are not equal. The high-voltage semiconductor device described in item 3 of the scope of patent application, wherein the second electrode structure is disposed on the boundary between the first well region and the second well region. The high-voltage semiconductor device described in claim 1, wherein the first insulating layer includes a first part and a second part that are separated from each other. The high-voltage semiconductor device described in item 1 of the scope of patent application, which also includes: A second insulating layer is arranged on the first insulating layer, and the second electrode structure is partially arranged on the second insulating layer. The high-voltage semiconductor device described in item 11 of the scope of patent application, which also includes: A third electrode structure is arranged separately from the first electrode structure, wherein the second electrode structure and the third electrode structure respectively include a gate structure and a capacitor structure.

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