TWI740531B - High-voltage semiconductor device - Google Patents
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Description
本發明是關於一種半導體裝置,且特別是關於一種高壓半導體裝置。 The present invention relates to a semiconductor device, and more particularly to a high-voltage semiconductor device.
隨著半導體技術的提昇,業界已能將控制電路、記憶體、低壓操作電路、以及高壓操作電路及相關元件同時整合製作於單一晶片上,以降低成本並提高操作效能。而常用於放大電路中電流或電壓訊號、作為電路震盪器(oscillator)、或作為控制電路開關動作之開關元件的電晶體元件,更隨著半導體製程技術的進步而被應用作為高功率元件或高壓元件。舉例來說,作為高壓元件的電晶體元件係設置於晶片內部電路(internal circuit)與輸入/輸出(I/O)接腳之間,以避免大量電荷在極短時間內經由I/O接腳進入內部電路而造成破壞。 With the improvement of semiconductor technology, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and related components on a single chip at the same time to reduce costs and improve operating efficiency. Transistor elements, which are commonly used to amplify current or voltage signals in circuits, as circuit oscillators, or as switching elements that control circuit switching operations, have been applied as high-power elements or high-voltage with the advancement of semiconductor process technology. element. For example, a transistor component as a high-voltage component is placed between the internal circuit of the chip and the input/output (I/O) pins to prevent a large amount of charge from passing through the I/O pins in a very short time. Enter the internal circuit and cause damage.
在目前作為高壓元件的電晶體元件中,主要係以降低側向電場的方式來達到提升崩潰電壓(breakdown voltage)的效果,而在結構上大致包括有雙擴散汲極金氧半導體(double diffused drain MOS,DDDMOS)、橫向擴散汲極金氧半導體(laterally diffused MOS,LDMOS)等元件。然而,如何進一步地提升高壓半導體裝置的崩潰電 壓以符合實務上的需求為目前業界所面臨的課題。 In the current transistor components as high-voltage components, the effect of increasing the breakdown voltage is mainly achieved by reducing the lateral electric field, and the structure roughly includes double diffused drain metal oxide semiconductor (double diffused drain metal oxide semiconductor). MOS, DDDMOS), laterally diffused MOS (LDMOS) and other components. However, how to further increase the breakdown voltage of high-voltage semiconductor devices? Complying with practical requirements is a topic facing the industry at present.
本發明之一目的在於提供一種高壓半導體裝置,其係在汲極區域下方的絕緣埋層內局部性地增設至少一濃度調變區,該至少一濃度調變區具有與該絕緣埋層相同的導電型態、相同的摻質以及較低的摻雜濃度,因而可降低該汲極區域下方的電場強度,進而提升該高壓半導體裝置的崩潰電壓。 An object of the present invention is to provide a high-voltage semiconductor device, which is locally added at least one concentration-modulated region in the buried insulating layer below the drain region, the at least one concentration-modulated region having the same thickness as the buried insulating layer The conductivity type, the same dopant, and a lower doping concentration can reduce the electric field intensity under the drain region, thereby increasing the breakdown voltage of the high-voltage semiconductor device.
為達上述目的,本發明之一較佳實施例提供一種高壓半導體裝置,其包括一基底、一埋層、一汲極區域、一源極區域、一閘極以及至少一濃度調變區。該基底具有一第一導電類型,該埋層設置於該基底內,並且具有一第二導電類型,該第二導電類型與該第一導電類型互補。該汲極區域設置於該基底內並位在該埋層上方,該汲極區域具有該第一導電類型。該源極區域設置於該基底內並位在該埋層上方,該源極區域具有該第一導電類型。該閘極設置在該基底上,位在該源極區域與該汲極區域之間。該至少一濃度調變區設置在局部的埋層內。該至少一濃度調變區位在該汲極區域下方並具有該第二導電類型,且該些濃度調變區的摻雜濃度小於該埋層的摻雜濃度。 To achieve the above objective, a preferred embodiment of the present invention provides a high-voltage semiconductor device, which includes a substrate, a buried layer, a drain region, a source region, a gate, and at least one concentration modulation region. The substrate has a first conductivity type, and the buried layer is disposed in the substrate and has a second conductivity type that is complementary to the first conductivity type. The drain region is disposed in the substrate and above the buried layer, and the drain region has the first conductivity type. The source region is disposed in the substrate and above the buried layer, and the source region has the first conductivity type. The gate is arranged on the substrate and is located between the source region and the drain region. The at least one concentration modulation area is arranged in a local buried layer. The at least one concentration-modulated region is located under the drain region and has the second conductivity type, and the doping concentration of the concentration-modulated regions is less than the doping concentration of the buried layer.
100、300、400、500、600:高壓半導體裝置 100, 300, 400, 500, 600: high-voltage semiconductor devices
110:基底 110: Base
120、320、420、520、620:埋層 120, 320, 420, 520, 620: buried layer
121:濃度調變區 121: Concentration modulation area
130:第一井區 130: The first well area
140:第二井區 140: The second well area
150:汲極區域 150: Drain area
160:源極區域 160: source region
170:基體區域 170: matrix area
190、191、193、195:絕緣結構 190, 191, 193, 195: insulation structure
210:閘極 210: Gate
211:閘極介電層 211: gate dielectric layer
213:閘極電極層 213: gate electrode layer
321:濃度調變區 321: Concentration Modulation Area
323:方型摻雜區 323: Square doped area
421:濃度調變區 421: Concentration Modulation Area
521、523:濃度調變區 521, 523: Concentration modulation area
621、623:濃度調變區 621, 623: Concentration modulation area
D1:第一方向 D1: First direction
D2:第二方向 D2: second direction
E1、E2:曲線 E1, E2: Curve
第1圖繪示本發明第一實施例中高壓半導體裝置的俯視示意圖。 FIG. 1 is a schematic top view of the high-voltage semiconductor device in the first embodiment of the present invention.
第2圖為第1圖沿著切線A-A’的剖面示意圖。 Figure 2 is a schematic cross-sectional view taken along the line A-A' in Figure 1.
第3圖繪示本發明第一實施例中高壓半導體裝置的模擬示意圖。 FIG. 3 is a schematic diagram of a simulation of the high-voltage semiconductor device in the first embodiment of the present invention.
第4圖繪示繪示本發明第二實施例中高壓半導體裝置的示意圖。 FIG. 4 shows a schematic diagram of a high-voltage semiconductor device in the second embodiment of the present invention.
第5圖繪示繪示本發明第三實施例中高壓半導體裝置的示意圖。 FIG. 5 shows a schematic diagram of a high-voltage semiconductor device in the third embodiment of the present invention.
第6圖繪示繪示本發明第四實施例中高壓半導體裝置的示意圖。 FIG. 6 shows a schematic diagram of a high-voltage semiconductor device in the fourth embodiment of the present invention.
第7圖繪示繪示本發明第五實施例中高壓半導體裝置的示意圖。 FIG. 7 shows a schematic diagram of a high-voltage semiconductor device in the fifth embodiment of the present invention.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明,下文特列舉本發明之數個較佳實施例,並配合所附圖式,詳細說明本發明的構成內容及所欲達成之功效。並且,熟習本發明所屬技術領域之一般技藝者亦能在不脫離本發明的精神下,參考以下所舉實施例,而將數個不同實施例中的特徵進行替換、重組、混合以完成其他實施例。 In order to enable those who are familiar with the technical field of the present invention to have a better understanding of the present invention, a few preferred embodiments of the present invention are listed below, together with the accompanying drawings, to explain in detail the content of the present invention and what it intends to achieve. The effect. Moreover, those who are familiar with the technical field of the present invention can also refer to the following embodiments without departing from the spirit of the present invention, and replace, reorganize, and mix the features in several different embodiments to complete other implementations. example.
本發明中針對「第一部件形成在第二部件上或上方」的敘述,其可以是指「第一部件與第二部件直接接觸」,也可以是指「第一部件與第二部件之間另存在有其他部件」,致使第一部件與第二部件並不直接接觸。此外,本發明中的各種實施例可能使用重複的元件符號和/或文字註記。使用這些重複的元件符號與文字註記是為了使敘述更簡潔和明確,而非用以指示不同的實施例及/或配置之間的關聯性。另外,針對本發明中所提及的空間相關的敘述詞彙,例如:「在...之下」、「在...之上」、「低」、「高」、「下方」、「上方」、「之下」、「之上」、「底」、「頂」和類似詞彙時,為便於敘述,其用法均在於描述圖式中一個部件或特徵與另一個(或多個)部件或特徵的相對關係。除了圖式中所 顯示的擺向外,這些空間相關詞彙也用來描述半導體裝置在製作過程中、使用中以及操作時的可能擺向。舉例而言,當半導體裝置被旋轉180度時,原先設置於其他部件「上方」的某部件便會變成設置於其他部件「下方」。因此,隨著半導體裝置的擺向的改變(旋轉90度或其它角度),用以描述其擺向的空間相關敘述亦應透過對應的方式予以解釋。 In the present invention, the description of "the first part is formed on or above the second part" can mean "the first part is in direct contact with the second part", or it can mean "between the first part and the second part" There are other parts", so that the first part and the second part are not in direct contact. In addition, various embodiments of the present invention may use repeated component symbols and/or text annotations. The use of these repeated component symbols and text notes is to make the description more concise and clear, rather than to indicate the association between different embodiments and/or configurations. In addition, for the space-related narrative vocabulary mentioned in the present invention, for example: "below", "above", "low", "high", "below", "above" "", "below", "above", "bottom", "top" and similar words, for ease of description, their usage is to describe one component or feature and another (or more) component or The relative relationship of features. Except in the scheme The displayed swing outwards, and these space-related words are also used to describe the possible swing directions of the semiconductor device during the manufacturing process, in use, and operation. For example, when the semiconductor device is rotated by 180 degrees, a component that was originally placed "above" other components will become "below" other components. Therefore, as the swing direction of the semiconductor device is changed (rotated by 90 degrees or other angles), the space-related narrative used to describe its swing direction should also be interpreted in a corresponding manner.
雖然本發明使用第一、第二、第三等用詞,以敘述種種元件、部件、區域、層、及/或區塊(section),但應了解此等元件、部件、區域、層、及/或區塊不應被此等用詞所限制。此等用詞僅是用以區分某一元件、部件、區域、層、及/或區塊與另一個元件、部件、區域、層、及/或區塊,其本身並不意含及代表該元件有任何之前的序數,也不代表某一元件與另一元件的排列順序、或是製造方法上的順序。因此,在不背離本發明之具體實施例之範疇下,下列所討論之第一元件、部件、區域、層、或區塊亦可以第二元件、部件、區域、層、或區塊等詞稱之。 Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and / Or the block should not be restricted by these words. These terms are only used to distinguish an element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they do not mean or represent the element. Any preceding ordinal number does not represent the order of arrangement of a component and another component, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below may also be termed as the second element, component, region, layer, or block Of.
本發明中所提及的「約」或「實質上」之用語通常表示在一給定值或範圍的20%之內,較佳是10%之內,且更佳是5%之內,或3%之內,或2%之內,或1%之內,或0.5%之內。應注意的是,說明書中所提供的數量為大約的數量,亦即在沒有特定說明「約」或「實質上」的情況下,仍可隱含「約」或「實質上」之含義。 The term "about" or "substantially" mentioned in the present invention usually means within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, the meaning of "approximate" or "substantial" can still be implied when there is no specific description of "approximate" or "substantial".
請參照第1圖及第2圖所示,其繪示本發明第一實施例中高壓
半導體裝置100的示意圖,其中,第1圖為高壓半導體裝置100的一俯視示意圖,第2圖則為高壓半導體裝置100的一剖面示意圖。本發明的高壓半導體裝置係指操作電壓約高於90伏特(V)的半導體裝置,其例如是一橫向擴散金氧半導體電晶體(laterally diffused metal oxide semiconductor transistor,LDMOS transistor),可為橫向擴散N型金氧半導體電晶體或是橫向擴散P型金氧半導體電晶體,在本實施例中,高壓半導體裝置100是以橫向擴散P型金氧半導體電晶體為實施樣態進行說明,但並不以此為限。
Please refer to Figures 1 and 2, which illustrate the high voltage in the first embodiment of the present invention
A schematic diagram of the
首先,如第1圖及第2圖所示,高壓半導體裝置100包括一基底110,例如是矽基底、磊晶矽基底、矽鍺基底、碳化矽基底或矽覆絕緣(silicon-on-insulator,SOI)基底等,以及設置在基底110上的至少一絕緣結構190。在本實施例中,絕緣結構190例如是透過局部矽氧化(local oxidation of silicon,LOCOS)方法而形成的一場氧化層(field oxide,FOX),如第2圖所示,但不以此為限。在另一實施例中,該絕緣結構亦可以是透過一沉積製程而形成的淺溝渠隔離(shallow trench isolation,STI)或是透過其他適合製程而製得的絕緣單元等。需注意的是,為了清楚表現高壓半導體裝置100中某些特定摻雜區域的相對關係,第1圖中係將絕緣結構190省略,但熟習該項技藝之人士應可根據第2圖輕易瞭解絕緣結構190的設置位置。此外,關於本發明絕緣結構190的具體設置位置與數量等特徵將會在後續段落中描述。
First, as shown in FIGS. 1 and 2, the high-
基底110具有一第一導電類型(例如是P型),其內分別設置有一第一井區130以及一第二井區140。具體來說,第一井區130具有該
第一導電類型(如P型),並且,第一井區130內還形成有一汲極(drain)區域150。汲極區域150同樣具有該第一導電類型(如P型),其摻雜濃度較佳係大於第一井區130的摻雜濃度。第二井區140係環設在第一井區130外側並且具有一第二導電類型(例如是N型),該第二導電類型(如N型)係與該第一導電類型(如P型)互補。在本實施例中,第二井區140在基底110內的深度例如是大於第一井區130,如第2圖所示,但不以此為限。第二井區140內形成有一源極(source)區域160,源極區域160具有該第一導電類型(如P型)。
The
此外,第二井區140內還形成有一基體(body)區域170,基體區域170具有該第二導電類型(如N型)且其摻雜濃度較佳為大於第二井區140的摻雜濃度。在一實施例中,基體區域170較佳係不直接接觸設置在第一井區130內的汲極區域150。舉例來說,基體區域170的兩相對側可分別設置絕緣結構191和絕緣結構193,而汲極區域150的兩相對側則分別設置絕緣結構193和絕緣結構195,如此,絕緣結構193即可夾設在汲極區域150和基體區域170之間,使得汲極區域150和基體區域170彼此電性隔離,如第2圖所示。並且,在一實施例中,基體區域170可以呈現環狀,例如是如第1圖所示的矩框狀,而可環繞於汲極區域150以及源極區域160的外圍。然而本領域者應可理解,在另一實施例中,該基體區域亦可能具有其他形狀,例如方形、圓環狀、賽道形(racetrack-shaped)或其他適合的形狀等,而不以第1圖所示者為限。另外,基底110上還設置一閘極210,閘極210可包括依序堆疊於基底110上的一閘極介電層211以及一閘極電極層213,其中,閘極電極層213例如為一多晶矽閘極層或金屬閘極層,但不以此為限。閘極210係位在
源極區域160和汲極區域150之間。在本實施例中,閘極210的一側係部分覆蓋基底110內的第二井區140,並且鄰接源極區域160,而閘極210的另一側則部分覆蓋在第一井區130以及絕緣結構195上,而不直接接觸汲極區域150。
In addition, a
另一方面,基底110內還設有一埋層(buried layer)120,係位在第一井區130以及第二井區140下方。埋層120可具有該第二導電類型(如N型)且其摻雜濃度係高於第一井區130以及第二井區140的摻雜濃度。在本實施例中,基底110內的埋層120以及第二井區140係共同作為高壓半導體裝置100的一絕緣(isolation)層,以避免電流直接自第一井區130貫穿(punch through)基底110的底部或內部,而影響高壓半導體裝置100的元件效能。需注意的是,本實施例的高壓半導體裝置100還包含局部開設於埋層120內的至少一濃度調變區(concentration modulated region)121。其中,濃度調變區121的數量可以是單一個,也可以是複數個,本實施例的高壓半導體裝置100是選擇在局部的埋層120內設置相互分隔的兩個濃度調變區121作為實施樣態進行說明,但不以此為限。本領域者應可輕易理解,該濃度調變區的數量還可依據實際元件需求而進一步調整,例如是僅在局部的埋層120內設置單一個該濃度調變區或是設置兩個以上的該濃度調變區。
On the other hand, a buried
需注意的是,濃度調變區121較佳是設置在高壓半導體裝置100中電場較強的部位,如設置在鄰近於第一井區130和第二井區140PN接面(PN junction)或是第一井區130和埋層120之間的PN接面處,但不以此為限。舉例來說,濃度調變區121可設置在汲極區域150以及
第一井區130下方的埋層120內,並延伸於埋層120的頂面與底面之間,而直接接觸第一井區130,如第2圖所示。其中,各濃度調變區121在如第1圖所示的一俯視圖上例如是一條狀摻雜區,並且,濃度調變區121整體的涵蓋面積較佳係小於第一井區130的涵蓋面積,如第1圖及第2圖所示。於一較佳實施例中,濃度調變區121在垂直於基底110的一方向(未繪示)上的投影範圍並未超出第一井區130在該垂直方向上的投影範圍。在一實施例中,濃度調變區121的製作例如是在進行埋層120的離子佈植製程時額外設置一遮罩(未繪示),並透過該遮罩阻擋基底110的局部區域,使得該局部區域無法在該離子佈植製程中被植入摻質,而僅能在後續的熱驅入(drive-in)製程中獲得自埋層120所擴散出的少量摻質。因此,濃度調變區121可具有與埋層120相同的導電類型(如N型)、相同的摻質以及相對較低的摻雜濃度。舉例來說,濃度調變區121的摻雜濃度相較於埋層120的摻雜濃度例如是約減少10%至20%左右,較佳係約減少15%,但不以此為限。在另一實施例中,濃度調變區121的製作還可選擇在形成埋層120之前或之後進行,例如可先透過另一離子佈植製程在局部的基底110內直接形成摻雜濃度相對較低的一摻雜區作為該濃度調變區,再形成埋層120,或者是,在基底110內形成埋層120時先局部預留空間,之後再透過另一離子佈植製程於該預留空間內直接形成摻雜濃度相對較低的一摻雜區作為該濃度調變區,但不以此為限。
It should be noted that the concentration-modulating
換言之,濃度調變區121即是局部設置(汲極區域150以及第一井區130下方的部位)在埋層120內的至少一開口(slot),而後透過熱驅入製程獲得自埋層120所擴散出的少量摻質,而可具有相對較低的
摻雜濃度。因此,濃度調變區121可降低該部位的電場強度,進而改善高壓半導體裝置100在電場強度較強的部位(即靠近PN接面的部位或汲極區域150附近)崩潰電壓較低的問題。在此設置下,高壓半導體裝置100的崩潰電壓例如約可提升5伏特左右,但不以此為限。請參照第3圖所示,本實施例的高壓半導體裝置100(如曲線E1所示)在模擬測試下,確實可降低局部的電場強度,而可相較於習用高壓半導體裝置(如曲線E2所示)獲得較高的崩潰電壓,但不以此為限。由此,本實施例的高壓半導體裝置100即可獲得較佳的元件效能。
In other words, the
本領域具有通常知識者應可輕易了解,為能滿足實際產品需求的前提下,本發明的高壓半導體裝置亦可能有其它態樣,而不限於前述。舉例來說,在前述實施例中,雖是以橫向擴散P型金氧半導體電晶體為實施樣態進行說明,而使該第一導電類型為P型、該第二導電類型為N型,但並不以此為限。在另一實施例中,亦可選擇使該第一導電類型為N型,該第二導電類型為P型而形成不同型態的高壓半導體裝置。下文將進一步針對高壓半導體裝置的其他實施例或變化型進行說明。且為簡化說明,以下說明主要針對各實施例不同之處進行詳述,而不再對相同之處作重覆贅述。此外,本發明之各實施例中相同之元件係以相同之標號進行標示,以利於各實施例間互相對照。 Those with ordinary knowledge in the art should easily understand that the high-voltage semiconductor device of the present invention may also have other aspects, which are not limited to the foregoing, on the premise of meeting actual product requirements. For example, in the foregoing embodiment, although the laterally diffused P-type metal oxide semiconductor transistor is used as an implementation mode for description, the first conductivity type is P-type and the second conductivity type is N-type. Not limited to this. In another embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type to form different types of high-voltage semiconductor devices. The following will further describe other embodiments or variations of the high-voltage semiconductor device. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and the similarities are not repeated. In addition, the same elements in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.
根據本發明的另一實施例,係提供一種高壓半導體裝置,其可在局部調整該埋層的摻雜濃度以降低局部的電場強度時,同時避免該部位的摻雜濃度過低而影響該埋層作為絕緣層的效果。請參照第4圖所示,其繪示本發明第二實施例中高壓半導體裝置300的俯視示意
圖。本實施例中的高壓半導體裝置300的結構大體上與前述第一實施例所述高壓半導體裝置100相同,同樣包括基底110、第一井區130、第二井區140、汲極區域150、源極區域160、基體區域170以及絕緣結構190等,相同之處容不再贅述。本實施例與前述實施例的主要差異在於濃度調變區321於埋層320內的具體設置條件,如設置區域、圖案設計、數量以及大小等。
According to another embodiment of the present invention, a high-voltage semiconductor device is provided, which can locally adjust the doping concentration of the buried layer to reduce the local electric field strength while avoiding the excessively low doping concentration of the part that affects the buried layer. The effect of the layer as an insulating layer. Please refer to FIG. 4, which shows a schematic plan view of the high-
詳細來說,本實施例的埋層320內係局部設置複數個濃度調變區321,濃度調變區321係位在汲極區域150以及第一井區130的下方。並且,濃度調變區321可具有與埋層320相同的導電類型(如N型)、相同的摻質以及較低的摻雜濃度。需注意的是,本實施例的濃度調變區321例如是一方型摻雜區,且各該方型摻雜區在如第4圖所示的一俯視圖上係相互間隔且錯位排列,而可整體呈現一棋盤狀(checkerboard arrangement),但不以此為限。換言之,本實施例的局部埋層320(即埋層320位在第一井區130下方的部分)亦可形成複數個方型摻雜區323,並且,各方型摻雜區323係與濃度調變區321相互間隔且錯位排列,如第4圖所示。
In detail, in the buried
由此,本實施例的濃度調變區321可更為均勻地分布在高壓半導體裝置300中電場較強的部位,使得該部位下方的埋層320的摻雜濃度可更為均勻地降低,例如相較於其他部位的埋層320的摻雜濃度約減少10%至20%左右,較佳係約減少15%,但不以此為限。在此設置下,本實施例的高壓半導體裝置300同樣可改善元件在電場強度較強的部位(即靠近PN接面的部分或汲極區域150附近)的崩潰電壓較低的問
題,並有效提升該部位的崩潰電壓,例如約可提升5伏特左右,而獲得較佳的元件效能。
Therefore, the
此外,本領域具有通常知識者應可輕易理解,前述實施例中各濃度調變區321、121的設置數量、圖案(如方形或長條狀)以及大小僅為例示,並不以此為限。在其他實施例中,該濃度調變區亦可依據實際元件需求而可具有其他的設置態樣,以便能更為均勻地局部降低該埋層的摻雜濃度,來達到降低電場強度的效果。並且,該濃度調變區在該埋層內所佔的整體面積亦可依據實際元件需求調整,較佳係在不影響該埋層作為絕緣層效果的前提下,盡可能地提高元件的崩潰電壓。
In addition, those with ordinary knowledge in the art should easily understand that the number, pattern (such as square or strip), and size of the
請參照第5圖至第7圖所示,其分別繪示本發明第三實施例、第四實施例以及第五實施例中高壓半導體裝置400/500/600的俯視示意圖,其中,高壓半導體裝置400/500/600的結構大體上與前述第二實施例所述高壓半導體裝置300相同,容不再贅述。該些實施例與前述第二實施例的主要差異在於該些濃度調變區可具有多種不同的設置態樣。
Please refer to FIG. 5 to FIG. 7, which illustrate the top view schematic diagrams of the high-
詳細來說,在第三實施例中,高壓半導體裝置400包含複數個濃度調變區421,並且,各濃度調變區421同樣為一方型摻雜區(摻雜濃度較低),且各該方型摻雜區在如第5圖所示的一俯視圖上係相互間隔地順列(in-line arrangement)排列於第一井區130或汲極區域150下方的埋層420中。而在第四實施例中,高壓半導體裝置500則可同時包含濃度調變區521以及濃度調變區523。濃度調變區521以及濃度調變
區523在如第6圖所示的一俯視圖上可分別為一矩框狀摻雜區(摻雜濃度較低),其中,濃度調變區523與濃度調變區521係相互分離地位在第一井區130或汲極區域150下方的埋層520中,並且,濃度調變區523係環繞在濃度調變區521之外。此外,濃度調變區523和濃度調變區521的幾何中心(geometric center)彼此可以互相重疊,但不限定於此。而在第五實施例中,高壓半導體裝置600則可同時包含複數個濃度調變區621以及複數個濃度調變區623。濃度調變區621例如是相互平行且沿著一第一方向D1延伸的條狀摻雜區(摻雜濃度較低),濃度調變區623則例如是相互平行且沿著一第二方向D2延伸的條狀摻雜區(摻雜濃度較低),第二方向D2不同於第一方向D1。由此,各濃度調變區623在如第7圖所示的一俯視圖上可橫跨濃度調變區621,而在第一井區130或汲極區域150下方的埋層620中呈現一網格狀(grid-shaped)結構,但不以此為限。在該第五實施例中,第一方向D1例如是垂直於第二方向D2,如第7圖所示,但不以此為限,在另一實施例中,該第一方向以及該第二方向還可選擇為彼此相交但相互不垂直,仍可形成整體呈現一網格狀結構的濃度調變區。
In detail, in the third embodiment, the high-
在前述的各種設置態樣下,該些濃度調變區(包含第5圖所示的濃度調變區421;第6圖所示的濃度調變區521、523;以及第7圖所示的濃度調變區621、623)同樣可更為均勻地分布在高壓半導體裝置400/500/600中電場較強的部位,使得該部位下方的該埋層(包含第5圖所示的埋層420;第6圖所示的埋層520;以及第7圖所示的埋層620)的摻雜濃度可更為均勻地降低,例如相較於其他部位的該埋層的摻雜濃度約減少10%至20%左右,較佳係約減少15%,但不以此為限。在前
述各種設置態樣下,高壓半導體裝置400/500/600同樣可改善元件在電場強度較強的部位(即靠近PN接面的部分或汲極區域150附近)的崩潰電壓較低的問題,提升該部位的崩潰電壓,例如約可提升5伏特左右,而獲得較佳的元件效能。
In the aforementioned various settings, the density adjustment areas (including the
此外,另需注意的是,在本發明前述的各實施例中,雖皆是將各種態樣的該些濃度調變區設置在一埋層進行說明,但本領域具有通常知識者應可輕易理解,本發明前述的該些濃度調變區亦可選擇設置在一高壓半導體裝置的其他電絕緣層中,例如是形成在一深井區(deep well)或是一高壓井區(HV well)內等。藉此,同樣可透過該些濃度調變區設置達到局部降低該電絕緣層的摻雜濃度的效果,進而局部性地降低該高壓半導體裝置的電場強度。 In addition, it should also be noted that in the foregoing embodiments of the present invention, although the concentration modulation regions in various forms are provided in a buried layer for description, those with ordinary knowledge in the field should be able to easily It is understood that the aforementioned concentration modulation regions of the present invention can also be optionally provided in other electrical insulating layers of a high-voltage semiconductor device, for example, formed in a deep well region or a high-voltage well region (HV well). Wait. Thereby, it is also possible to achieve the effect of locally reducing the doping concentration of the electrically insulating layer through the arrangement of the concentration-modulating regions, thereby locally reducing the electric field intensity of the high-voltage semiconductor device.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:高壓半導體裝置 100: High-voltage semiconductor device
120:埋層 120: Buried layer
121:濃度調變區 121: Concentration modulation area
130:第一井區 130: The first well area
140:第二井區 140: The second well area
150:汲極區域 150: Drain area
160:源極區域 160: source region
170:基體區域 170: matrix area
210:閘極 210: Gate
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