201251007 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種橫向擴散金氧半導體元件及其製造方 法，尤指一種具有低的導通電阻(On-state resistance，Rem)/ 崩潰電壓（Breakdown Voltage，VB)值的橫向擴散金氧半導 體元件及其製造方法。 【先前技術】 隨著半導體積體電路製造技術的發展，對於形成於單一 晶片上的控制電路、記憶體、低壓操作電路以及高壓操作電 路等元件的需求也隨之增加，其中習知技術更常利用絕緣閘 極雙載子電晶體（insulated gate bipolar transistor，IGBT)與雙 擴散金氧半導體（double-diffused metal oxide semiconductor，DM0S)元件作為單一晶片内的高壓元件。 雙擴散金氧半導體元件可概分為橫向擴散金氧半導體元 件（lateral DMOS，以下簡稱為LDMOS)與垂直擴散金氧半導 體元件(vertical DMOS ’ VDMOS)，其中LDMOS因與標準互 補型金氧半導體(CMOS)元件製程具有較佳的整合性，且具 有較佳的切換效率（power switching efficiency)，又更常為業 界所採用。 5 201251007 第1圖為習知橫向擴散金氧半導體元件的剖面示意圖 。如第1 圖所示’橫向擴散金氧半導體元件i⑻包含有一 p型的基底110、 一 N型井120設置於基底11〇巾、一場氧化層13〇設置於基底11〇 上開極140 5又置於部分場氧化層130上’一侧壁子15〇設置於 甲1極140的兩側P型摻雜區160位於N型井12〇令，而源極170 則位於側子丨5〇 一側邊的p型摻雜區_中沒極謂設置於側 壁子150另一側邊的n型井12〇中。 當施加於橫向擴散金氧半導體元件1〇〇之閘極⑽的電壓大 於閾值電_hreshold voltage)時，橫向擴散金氧半導體元件謂 即被開啟。此時，自汲極180輸入之高壓訊號會經由N型井 =〇傳向源極！ 7 〇。N型井！ 2 G係用以作為—電阻使得流 井12G之高壓訊號產生壓降成為低壓訊號，以利内部 吏用。然而，由於P型摻雜型井12〇之介 半^的：雜電性差異’故造成局部電場集中’導致橫向擴散金氧 導體轉⑽的崩潰電壓降低以及導通電阻增高。是以， :向擴體元件之⑽(導通電阻/崩潰電壓)值居高二。 【發明内容】 ^發明提出―種橫向擴散金氧半導體元 具有相較於習知較低的R/B值。 ^方法 201251007 本毛月提供一種橫向擴散金氧半導體元件，包含有一基 底 第味井區、至少一場氧化層、一閘極、一第二深井 區 第摻雜區、一汲極以及一共用源極。基底具有第一 導電型之第一深井區。至少一場氧化層位於基底上。閘極設 置於基底上且覆蓋部分場氧化層。第二深井區具有—第二導 電型，設置於基底中且緊鄰第—深井區。第—摻雜區且有一 =導！型、:設置於第二深井區中’且第-摻雜區的換雜濃 又同於第-冰井區的摻雜濃度。没極設置於閘極外側的第一 深井區中。共用源極設置於閘極内側的第一摻雜區中。 包含有一基 場氧化層、 彡及極以及一共用 源極。蟲晶層位於基底上，具有第一導電型之第一 井區 埋入層位於基底與磊晶層之間。至少一場氧化層位於蠢 本發明提供一種橫向擴散金氧半導體元件， 底、一磊晶層、第一深井區、一埋入層、至少 一閘極、一第二深井區、一第一摻雜區、 晶 層 上。閘極設置於磊晶層上且覆蓋部分場氧化層。第二深井區 具有一第二導電型’設置於蠢晶層中且緊鄰第一深井區。第 —摻雜區具有一第二導電蜇，設置於第一深井區中，且第一 摻雜區的摻雜濃度高於第二深井區的掺雜濃度。汲極設置於 閘極外側的第一深井區中。共用源極設置於閘極内側的第一 摻雜區中。 201251007 本發明提供-種橫向擴散金氧半導體元件 包含有下列步驟。首先，提供-基底。接著’方法’ 井區於基底中，第-深井區具有—第1電型^ :第:深 一第二深井區於基底中且緊鄰第—深井區，第二产^形成 -第二導電型。續之，形成一汲極於第—深井區；。2有 形成至少一場氧化層，於基底上。接續，形成一第妓， 於第二深井區中，第-穆雜區具有—第二 第—摻雜區 雜區的摻雜濃度高於第 且第一摻 閘極，於第-摻雜區摻Γ度。再者，形成— 化層。最後，形成-共用源極於;一;=且中覆蓋、 製造:二一種橫向擴散金氧半導體元件及其 第一摻雜區相同，但第二二二此第二深井區的電性與 的摻雜濃度，故本發明<橫：:Μ度小於第—摻雜區 :式的摻雜濃度梯度結構，、因而可〜有-漸 氧半導體元件具有較低的R(導通電阻）/Β(Λ擴散金 此外’本發明之橫向擴散金氧半導體元件更:有二電壓)值。 用以作為絕緣層，而能進—步防止位於埋人;上—=入層， -深井區的電流流向下而漏電的情形。 寺別是第 【實施方式】 第2圖為依據本發明第—較佳實施例之橫向 擴散金氧半導 體 201251007 元件的上視及剖面示意圖。如第2圖所示（，其中（2a)為上視圖， (2b)為剖面圖），一種橫向擴散金氧半導體元件200，包含 有一基底210、一第一深井區220、至少一場氧化層230、一 閘極240、一第二深井區250、一第一摻雜區260、一汲極 270以及一共用源極280。基底210具有第一深井區220，其 中基底210包含一矽基底、一含矽基底、一矽覆絕緣基底或 其他半導體基底。場乳化層230位於基底210上，包含二氧 化矽層，但亦可為其他淺溝隔離(STI)等絕緣結構，本發明不 以此為限。閘極240設置於基底210上且覆蓋部分場氧化層 230，其中閘極240可包含一閘極介電層242、一閘極電極 244以及一側壁子246 ’當然亦可包含一蓋層（未繪示），而 閘極240的材質為本領域所熟知，故不在此資述。 第一深井區220具有一第一導電型，第二深井區25〇具 有一第二導電型，緊鄰第一深井區22〇且設置於基底21〇 中，而基底210較佳具有第二導電型。再者，在本實施例中， 第一深井區220係位於第二深井區25〇外圍，且第一深井區 220與第二深井區250不重疊，但此設置僅為本發明之一實 施態樣，本發明不以此為限。在本實施例中，第一導電型為 N型，第二導電型為P型，但熟習該項技藝之人士應知，隨 著欲形成的電晶體導電類型不同，第一導電型亦可為p型， 而第二導電型可為N型。第一摻雜區26〇亦具有一第二導電 型，設置於第二深井區250中’且第一摻雜區的摻雜濃 201251007 度高於第二深井區250的摻雜濃度，因而形成一具有漸變濃 度梯度的結構。共用源極280設置於閘極240内側的第一摻 雜區260中’汲極270設置於閘極240外側的第一深井區中。 如此，汲極270緊鄰場氧化層230設置，是以當橫向擴散金 氧半導體元件200導通，高電壓電流由汲極270流入時，可 防止電流穿過閘極介電層242流至閘極電極244而導致橫向 擴散金氧半導體元件200失效。另外，將汲極270設置於閘 極240的周圍，而採用共用源極28〇的設置，可獲得一較為 均勻的電場，進而提升崩潰電壓。 必須強調的是，本發明較佳實施例之閘極240具有一操場 跑道(racetrack)佈局形狀（如第2a圖），其中閘極240係由 一對互相平行的直線部分與一對分別設置於閘極240直線部 分兩端的曲線端部分所構成。但在其他實施例中，閘極240 亦可具有一矩形且為中空的佈局圖案，本發明不以此為限。 此外’在一較佳實施例中，更包含一對具有第二導電型的摻 雜區290 ’位於共用源極280兩端的基底210中，設置範圍 係對應且部分重疊於閘極240的曲線端部分與共用源極 280。摻雜區290的設置係可避免曲線端部分產生通道，進 而避免電場的產生。第二深井區250與第一深井區220之交 界面S1可包含一操場跑道佈局曲面，其類似閘極24〇的操 場跑道(racetrack)佈局形狀的曲面。在一較佳實施例中，第 二深井區250與第一深井區220之交界面S1係位於閘極240 201251007 的正下方，易言之，第二深井區250與第一深井區22〇之交 界面S1係位於汲極270與共用源極280之間。再者，第〆 摻雜區260與第二深井區250之交界面S2亦包含一操場跑 道佈局曲面，且在一較佳實施例中，第二深井區25〇與第〆 摻雜區260之交界面S2亦位於閘極240的正下方，易言之， 第二深井區250與第一摻雜區260之交界面幻亦位於浪極 27〇與共用源極280之間，且交界面S1環繞交界面s2。如 此，可藉由調整第一摻雜區260、第二深井區25〇以及第〆 深井區220的濃度來有效控制橫向擴散金氧半導體元件2〇〇 導通時，其内部電壓分佈，以進一步提高橫向擴散金氧半導 體元件200的崩潰電壓以及減少其電阻值。舉例而言，本發 月係使第一摻雜區260的摻雜濃度大於第二深井區250的摻 雜'農度’俾使第一摻雜區260與第二深井區250的摻雜濃度 具有一緩和的摻雜濃度梯度。因此，當電流流經時，便不具 右 、—極端的摻雜濃度差異，而能改善電場分佈集中的問題， 進而提升橫向擴散金氧半導體元件200的崩潰電壓以及減少 其導通電阻。因此，本發明可有效減少R/B (導通電阻/崩潰 電壓）值’而能有效改善橫向擴散金氧半導體元件200的電 性品質。 在一較佳的實施例中，第一深井區220與第一摻雜區260 之間只設置有第二深井區250，換言之，不再另外設置其他 凡件於第一深井區220與第一摻雜區260之間，以進一步避 201251007 電 場集〜區域一潰 非Λ進言，波極27G設置於閘極施外側的第一深 以門極場跑道佈局曲面。共用源極280則設 係由閘極240所句t “ m L 亦可為具有1場圍％繞，而制源極280 極280更可^ 曲面的船形結構。再者，共用源 極280更了包含—第二摻雜 284,且第二摻_…淑“ 4數個島狀第二摻雜區 第-導電型與島第三摻雜區284分別具有一 、一導電型。在一較佳實施例中，第 區250、篦一换他r- 矛一冰开 〃'區260與島狀第三摻雜區284的摻雜濃产 :高=低依序為島狀第三摻雜區284、第一摻雜區26〇以： 、-冰井區25。。如此’以提供—漸變式濃度梯度的結構， :改善橫向擴散金氧半導體元件2〇〇的電性分佈進而降低 橫向擴散金氧半導體元件2⑼的R (導通電阻）/B (崩潰電 壓）值。另外’島狀第三摻雜區284上可再設置有複數個基 體接觸插塞284a;第二摻雜區282上亦可再設置有複數個源 極接觸插塞282a，以電連接其他電子元件。 第3圖為依據本發明第二較佳實施例之橫向擴散金氧半導體 元件的剖面示意圖。如第3圖所示，本實施例與（上述）第一 實施例的差異在於，本實施例的橫向擴散金氧半導體元件3〇〇 12 201251007 更包含一遙晶層310位於基底2i〇上，而第一導電型之第— 深井區220則位於磊晶層31〇中。再者，橫向擴散金氧半導 體兀件300又包含一埋入層32〇位於基底21〇與磊晶層31〇 之間，用以電性隔絕埋入層32〇上之第二深井區25〇等，以 防止電流向下造成漏電。埋入層32〇可例如為一重摻雜區、 N+埋入層或一氧化層等絕緣層，本發明不以此為限。在 其他實施例中，橫向擴散金氧半導體元件3〇〇可只包含一埋 入層320位於基底21〇中，而沒有磊晶層31〇的設置。 第4圖至第1〇圖例示本發明一較佳實施例之橫向擴散金氧 半導體το件的製作方法。下文與齡中僅以單—橫向擴散金氧半導 體元件為舰向概錄半導體元件的製作方法，但本發明之 魏應用上並靴於製作單—橫向擴散金氧半導體元件且本發明 之檢向擴散金氧半導體元件亦可與其他低壓電晶體等元件一起製 ^，本發明不以此為限。另外，為方便說明，以下㈣型為例 第一導電型，而P型視為第二導電型，但熟知本領域者可知著 欲形成的電晶料電類财同㈣亦可簡 N型視為第二導電型。 子电圭而 如一第4圖所示，首先提供—基底21()，其中此基底例如為—佩 =二切基底或1覆絕緣等半導體基底。本實施例财 基底為例，而在基底加中選擇性地形成—埋入層咖 = 層32〇可例如以N+重離子佈植製程等形成之N+重離子推雜 13 201251007 區，亦可例如以熱氧化製程形成一氧化絕緣層，本發明不以 此為限。接著，在形成埋入層320之後，可再形成一磊晶層 310於基底210上，此磊晶層31〇例如以磊晶方法形成。然 而，在其他實施例中，亦可能以矽覆絕緣基底組成一矽_氧化層 -矽的結構。此時，氧化層即可做為本實施例中之埋入層32〇，而 上層的矽即可對應為磊晶層31〇。當然，本發明亦可直接應 用在一矽基底210中，而不再另外形成一埋入層32〇或磊晶 層310，如第一實施例所述結構。 如第5圖所示，形成一第一深井區22〇於磊晶層31〇中而 第深井區220為一 N型深井區，其例如可利用離子佈植製 程先將N型摻懸人蟲晶層31G中，再熱處理製無人(drive_in) 摻質而形成。 如第6圖所示，形成一第二深井區25〇於磊晶層釘❹中且 緊鄰第一深井區220。第二深井區250例如為一 p型深井區， 而第二深井區250可例如利用離子佈植製程先將p型摻質植入第 /木井區220中’再利用熱處理製程驅入(办^也)掺質而形成。 如第7圖所示，形成一圖案化氮化石夕層（未繪示）於基底2⑴ 上’此圖案化氮化補例如以磁彳微影方法形成，用以定義場氧化 層230的位置。之後’先例如以微影以及離子佈植製程ρι形成一 n 型的沒極270’。織’再侧贿化氮切層為料，進行氧化製 201251007 程形成場氧化層23〇。氧化層23()是作為隔離結構，但隔離結構並 不限定為魏化層23G，而柯城雜_t^(shaibwtreneh ls〇iatl〇n，STI)等之絕緣物件。在本實施例中，場氧化層23〇係形成 於第-深井區22G中並突出基底則的表面。接著，進行例如一微 影以及離子佈植製程P2，以形成—p型的第—摻雜區於第二 深井區250中，其中第一摻雜區施的摻雜濃度高於第二深 井區25G的摻雜濃度’以此形成—漸變式的摻雜濃度的p型推雜 如第8圖所示，形成一閘極介電層242以及一問極電極— 於第一摻雜區260以及没極27〇’之間的基底21()上再加以 :案:使其覆蓋部分的場氧化層23〇,且具有一操場跑道佈 局形狀。閘極介電層242以及閘極電極24 領域所熟知，故不在此料。 成方法為本 一如第9圖所示，利用例如微影及離子佈植製程1>3於場氧化居23〇 3=Γ深井區220中形成一具有N型輕推雜的及_，，曰，並 同時於场減層230另-侧之第一摻雜區26〇中形成— 摻雜的共職極蕭。糾，同_職影及離子佈植製程p 成同時未進行微影及離子佈植製程p4的部分共用源極蕭 即形成一輕摻雜的N型第二摻雜區282,。 15 201251007 如第10圖所示，例如以蝕刻微影製程於閘極電極2 成-側壁子246。接著，再利用例如微影及離子佈 44周圍形 化層230 一側的第一深井區220中形成-具有重換:5於場氧 270,並同時於場氧化層，另一側之第一推雜區_中=賴 重摻雜的N型共用源極（未緣示）。另外，再利 4一具有 製㈣於共騎射形成複數個重摻雜的p型島狀ζ及離子佈植 284，同時未進行姓刻微影及離子佈植製程Ρ6的部八^推雜區 形成-重摻雜_型第二推雜區282，因 /刀、用源極即 及島狀第三摻雜區284形成—共用源極28〇了 =區加以 發明之橫向擴散金氧半導體元件200的製作。b，完成本 總上所述，本發明提出一種 其製造方法，其具有一第一、月金氧半導體元件及 與第一摻雜區相同，且第二深弟一冰井區的電性 區，故本發明之橫向擴散金氧半導體^件第-摻雜 雜濃度梯度結構。如此一來， “有漸變式的掺 元件可解決習知第—摻雜區橫向擴散金氧半導體 以及摻雜濃度差異太大所造成之電：集；：摻雜電性不同 佳的問題，因而可降低橫向擴散金氧半'^生分佈不 電阻）/B (崩潰電壓）值，^改4 的Μ導通 發明之橫向擴散金氧半導體元件更。質。此外，本 絕緣層，而能進一步防止位於埋入声上入層，用以作為 的電流流向下而漏電的情形。特別疋第二深井區 16 201251007 所做 圍 【圖式簡單說明】 第1圖為習知橫向擴散金氧半導體元件的剖面示意圖。 第2圖為依據本發明第—較佳實施例之橫向擴散金氧半 的上視及剖面示意圖。 第3圖為依據本發明第二較佳實施例之橫向擴散金氧半 的剖面示意圖。 導體元件 導體元件 苐4圖至第1 〇圖例示本發明一 體元件的製作方法。 較佳實施例之橫向擴散金氧半導 【主要元件符號說明】 100、200、300 :橫向擴散金氧半導體元件 110、210 :基底 120 : N型井 130、230 :場氧化層 140、240 :閘極 150、246 I側壁子 160 : P型摻雜區 170 :源極 180、270、270’、270” ：；：及極 17 201251007 220 ： 第一深井區 242 ： 閘極介電層 244 ： 閘極電極 250 ： 第二深井區 260 ： 第一摻雜區 280、 280’ ：共用源極 282、282’ ：第二摻雜區 282a :源極接觸插塞 284、284’ ：島狀第三摻雜區 284a :基體接觸插塞 290 :摻雜區 310 :磊晶層 320 :埋入層 SI、S2 :交界面 PI、P2、P3、P4、P5 :微影以及離子佈植製程 18201251007 VI. Description of the Invention: [Technical Field] The present invention relates to a laterally diffused MOS device and a method of fabricating the same, and more particularly to a low on-state resistance (Rem) / breakdown voltage (Breakdown) A laterally diffused MOS device having a voltage, VB) value and a method of manufacturing the same. [Prior Art] With the development of semiconductor integrated circuit manufacturing technology, there is an increasing demand for components such as control circuits, memory, low voltage operation circuits, and high voltage operation circuits formed on a single wafer, among which conventional techniques are more common. An insulated gate bipolar transistor (IGBT) and a double-diffused metal oxide semiconductor (DMOS) device are used as high voltage components in a single wafer. Double-diffused MOS devices can be broadly classified into laterally diffused MOS devices (lateral DMOS, hereinafter referred to as LDMOS) and vertically diffused MOS devices (vertical DMOS 'VDMOS), where LDMOS is compatible with standard complementary MOS devices ( The CMOS) component process has better integration, has better switching efficiency, and is more commonly used in the industry. 5 201251007 Figure 1 is a schematic cross-sectional view of a conventional laterally diffused MOS device. As shown in Fig. 1, the laterally diffused MOS device i (8) comprises a p-type substrate 110, an N-type well 120 is disposed on the substrate 11 and a field oxide layer 13 is disposed on the substrate 11 and the open electrode 140 5 Placed on the partial field oxide layer 130, a side wall 15 is disposed on both sides of the pole 1 and the P-doped region 160 is located in the N-well 12, and the source 170 is located in the side gate. The p-doped region _ on the side is not included in the n-well 12 另一 on the other side of the sidewall sub-150. When the voltage applied to the gate (10) of the laterally diffused MOS device 1 is larger than the threshold voltage, the laterally diffused MOS device is turned on. At this time, the high voltage signal input from the bungee pole 180 will be transmitted to the source via the N-type well = !! 7 〇. N-type well! The 2 G system is used as a resistor to cause the voltage drop of the high voltage signal of the flow well 12G to become a low voltage signal for internal use. However, the partial electric field concentration caused by the P-type doping well 12's: the difference in the electric charge' causes the breakdown voltage of the laterally diffused gold-oxide conductor (10) to decrease and the on-resistance to increase. Therefore, the value of (10) (on-resistance/crash voltage) to the expanded component is two. SUMMARY OF THE INVENTION The invention proposes that a laterally diffused MOS element has a lower R/B value than conventionally known. ^方法201251007 The present invention provides a laterally diffused MOS device comprising a substrate first taste well region, at least one oxide layer, one gate, a second deep well region doped region, a drain and a common source. . The substrate has a first deep well region of a first conductivity type. At least one oxide layer is on the substrate. The gate is placed on the substrate and covers a portion of the field oxide layer. The second deep well zone has a second conductivity type disposed in the base and adjacent to the first deep well zone. The first doping zone has a = lead! Type: set in the second deep well zone' and the doping concentration of the first doping zone is the same as the doping concentration of the first-ice zone. The pole is placed in the first deep well area outside the gate. The common source is disposed in the first doped region inside the gate. It includes a field oxide layer, a ruthenium and a pole, and a common source. The worm layer is located on the substrate, and the first well region having the first conductivity type is buried between the substrate and the epitaxial layer. At least one oxide layer is located in a stray. The invention provides a laterally diffused MOS device, a bottom, an epitaxial layer, a first deep well region, a buried layer, at least one gate, a second deep well region, and a first doping layer. Area, on the crystal layer. The gate is disposed on the epitaxial layer and covers a portion of the field oxide layer. The second deep well region has a second conductivity type disposed in the stray layer and adjacent to the first deep well region. The first doped region has a second conductive germanium disposed in the first deep well region, and the doping concentration of the first doped region is higher than the doping concentration of the second deep well region. The drain is placed in the first deep well area outside the gate. The common source is disposed in the first doped region inside the gate. 201251007 The present invention provides a laterally diffused MOS device comprising the following steps. First, a substrate is provided. Then the 'method' is in the basement, the first deep well zone has the first electric type ^: the deeper second deep well zone is in the basement and adjacent to the first deep well zone, and the second generation is formed - the second conductivity type . Continued, forming a smashing in the first - deep well area; 2 There is at least one oxide layer formed on the substrate. In the second deep well region, the doping region of the first-doped region has a higher doping concentration than the first and first doping gates in the first doping region. Doping degree. Furthermore, a layer is formed. Finally, the formation-shared source is the same; the first and the second doped regions are the same, but the second and second second deep well regions are electrically The doping concentration, the present invention <horizontal:: the twist is smaller than the first doping region: the doping concentration gradient structure, and thus the ~-ovaporative semiconductor device has a lower R (on-resistance) / Β (Λ diffusion gold in addition to the lateral diffusion MOS device of the present invention: two voltages) value. Used as an insulating layer, it can prevent the situation from being buried; the upper-=into-layer, the current flowing in the deep well area and leaking. The second embodiment is a top view and a cross-sectional view of a laterally diffused gold-oxygen semiconductor 201251007 element according to a first preferred embodiment of the present invention. As shown in FIG. 2 (where (2a) is a top view, (2b) is a cross-sectional view), a laterally diffused MOS device 200 includes a substrate 210, a first deep well region 220, and at least one oxide layer 230. a gate 240, a second deep well region 250, a first doped region 260, a drain 270, and a common source 280. The substrate 210 has a first deep well region 220, wherein the substrate 210 comprises a germanium substrate, a germanium containing substrate, a germanium insulating substrate or other semiconductor substrate. The field embedding layer 230 is disposed on the substrate 210 and includes a ruthenium dioxide layer, but may be other insulating structures such as shallow trench isolation (STI), and the invention is not limited thereto. The gate 240 is disposed on the substrate 210 and covers a portion of the field oxide layer 230. The gate 240 may include a gate dielectric layer 242, a gate electrode 244, and a sidewall 246'. The material of the gate 240 is well known in the art and is therefore not described herein. The first deep well region 220 has a first conductivity type, and the second deep well region 25 has a second conductivity type, adjacent to the first deep well region 22〇 and disposed in the substrate 21〇, and the substrate 210 preferably has a second conductivity type. . Furthermore, in the present embodiment, the first deep well region 220 is located at the periphery of the second deep well region 25, and the first deep well region 220 and the second deep well region 250 do not overlap, but this arrangement is only one embodiment of the present invention. As such, the invention is not limited thereto. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type, but those skilled in the art should know that the first conductivity type may also be different depending on the conductivity type of the transistor to be formed. The p type, and the second conductivity type may be an N type. The first doping region 26A also has a second conductivity type disposed in the second deep well region 250' and the doping concentration of the first doping region is 201251007 degrees higher than that of the second deep well region 250, thereby forming A structure with a gradient concentration gradient. The common source 280 is disposed in the first doping region 260 inside the gate 240. The drain 270 is disposed in the first deep well region outside the gate 240. Thus, the drain 270 is disposed adjacent to the field oxide layer 230 so that when the laterally diffused MOS device 200 is turned on and the high voltage current flows from the drain 270, current can be prevented from flowing through the gate dielectric layer 242 to the gate electrode. 244 causes lateral diffusion of the MOS device 200 to fail. In addition, the drain 270 is disposed around the gate 240, and the arrangement of the common source 28 is used to obtain a relatively uniform electric field, thereby increasing the breakdown voltage. It must be emphasized that the gate 240 of the preferred embodiment of the present invention has a racetrack layout shape (e.g., Figure 2a), wherein the gate 240 is disposed by a pair of mutually parallel straight portions and a pair respectively. The curved end portion of the straight portion of the gate 240 is formed by a curved end portion. In other embodiments, the gate 240 may have a rectangular and hollow layout pattern, and the invention is not limited thereto. In addition, in a preferred embodiment, a pair of doped regions 290' having a second conductivity type are further disposed in the substrate 210 at both ends of the common source 280, and the setting range corresponds to and partially overlaps the curved end of the gate 240. Part and share source 280. The doping region 290 is arranged to avoid the creation of a channel at the end portion of the curve, thereby avoiding the generation of an electric field. The interface S1 between the second deep well region 250 and the first deep well region 220 may include a playground runway layout curved surface that resembles the surface of the gate track layout shape of the gate 24 turns. In a preferred embodiment, the interface S1 between the second deep well region 250 and the first deep well region 220 is located directly below the gate 240 201251007. In other words, the second deep well region 250 and the first deep well region 22 The interface S1 is located between the drain 270 and the common source 280. Furthermore, the interface S2 between the second doped region 260 and the second deep well region 250 also includes a playground runway layout curved surface, and in a preferred embodiment, the second deep well region 25A and the second doped region 260 The interface S2 is also located directly below the gate 240. In other words, the interface between the second deep well region 250 and the first doping region 260 is also located between the wave pole 27〇 and the common source 280, and the interface S1 Surround the interface s2. In this way, by adjusting the concentrations of the first doping region 260, the second deep well region 25〇, and the second deep well region 220, the internal voltage distribution of the laterally diffused MOS device 2 can be effectively controlled to further improve the internal voltage distribution. The breakdown voltage of the MOS element 200 is laterally diffused and its resistance value is reduced. For example, the present invention causes the doping concentration of the first doping region 260 to be greater than the doping 'agricultural degree' of the second deep well region 250 such that the doping concentration of the first doping region 260 and the second deep well region 250 is Has a moderate doping concentration gradient. Therefore, when the current flows, there is no right-to-extreme doping concentration difference, which can improve the problem of concentration of the electric field distribution, thereby increasing the breakdown voltage of the laterally diffused MOS device 200 and reducing its on-resistance. Therefore, the present invention can effectively reduce the R/B (on-resistance/crash voltage) value and can effectively improve the electrical quality of the laterally diffused MOS device 200. In a preferred embodiment, only the second deep well region 250 is disposed between the first deep well region 220 and the first doping region 260. In other words, no other components are disposed in the first deep well region 220 and the first Between the doped regions 260, in order to further avoid the 201251007 electric field set ~ region, the wave pole 27G is disposed on the first deep side of the gate pole to the gate field runway layout surface. The common source 280 is set by the gate 240. t "m L can also be a ship-shaped structure with a field circumference of about 5% and a source of 280 poles of 280, and a curved surface. Further, the common source 280 is more The second doping 284 is included, and the second doped region has a plurality of island-shaped second doped region first-conducting type and island third doped region 284 respectively having one conductivity type. In a preferred embodiment, the first region 250, the first one is replaced by the r-spear-ice opening 260 and the island-shaped third doped region 284 is doped rich: high = low is island-shaped The three doped regions 284 and the first doped regions 26 are: -, an ice well region 25. . Thus, the structure of the gradient concentration gradient is provided to improve the electrical distribution of the laterally diffused MOS device 2 and further reduce the R (on-resistance) / B (crash voltage) value of the laterally diffused MOS device 2 (9). In addition, the island-shaped third doping region 284 may be further provided with a plurality of base contact plugs 284a; the second doping region 282 may be further provided with a plurality of source contact plugs 282a for electrically connecting other electronic components. . Figure 3 is a cross-sectional view showing a laterally diffused MOS device in accordance with a second preferred embodiment of the present invention. As shown in FIG. 3, the difference between the present embodiment and the first embodiment is that the laterally diffused MOS device 3〇〇12 201251007 of the present embodiment further includes a remote crystal layer 310 on the substrate 2i〇. The first conductivity type - the deep well region 220 is located in the epitaxial layer 31 。. Furthermore, the laterally diffused MOS device 300 further includes a buried layer 32 between the substrate 21 and the epitaxial layer 31, for electrically isolating the second deep well region of the buried layer 32. Wait to prevent the current from causing leakage. The buried layer 32 can be, for example, a heavily doped region, an N+ buried layer, or an oxide layer. The invention is not limited thereto. In other embodiments, the laterally diffused MOS device 3 may include only one buried layer 320 in the substrate 21A without the arrangement of the epitaxial layer 31A. 4 to 1 are views showing a method of fabricating a laterally diffused MOS device according to a preferred embodiment of the present invention. In the following, a single-transverse-diffused MOS device is used as a method for fabricating a semiconductor component, but the invention is applied to fabricate a single-laterally diffused MOS device and the direction of the invention. The diffusion MOS device can also be fabricated together with other low voltage transistors and the like, and the invention is not limited thereto. In addition, for convenience of description, the following (4) type is taken as the first conductivity type, and the P type is regarded as the second conductivity type, but it is well known in the art that the crystal material to be formed is the same as the fourth type. It is a second conductivity type. As shown in Fig. 4, first, a substrate 21 () is provided, wherein the substrate is, for example, a semiconductor substrate such as a dicing substrate or a dielectric barrier. In this embodiment, the financial substrate is taken as an example, and the substrate layer is selectively formed - the buried layer = the layer 32 can be formed, for example, by the N+ heavy ion implantation process, etc., 20125007. The oxidized insulating layer is formed by a thermal oxidation process, and the invention is not limited thereto. Next, after the buried layer 320 is formed, an epitaxial layer 310 may be further formed on the substrate 210, and the epitaxial layer 31 is formed, for example, by an epitaxial method. However, in other embodiments, it is also possible to form a structure of a 矽-oxide layer-矽 with a blanket insulating substrate. At this time, the oxide layer can be used as the buried layer 32〇 in the present embodiment, and the upper layer of tantalum can correspond to the epitaxial layer 31〇. Of course, the present invention can also be applied directly to a substrate 210 without additionally forming a buried layer 32 or an epitaxial layer 310, as in the first embodiment. As shown in FIG. 5, a first deep well region 22 is formed in the epitaxial layer 31A and the deep well region 220 is an N-type deep well region. For example, the N-type doped insect can be firstly used in the ion implantation process. In the crystal layer 31G, a heat-driven (drive_in) dopant is formed by heat treatment. As shown in Fig. 6, a second deep well region 25 is formed in the epitaxial layer pin and adjacent to the first deep well region 220. The second deep well region 250 is, for example, a p-type deep well region, and the second deep well region 250 can be used to implant the p-type dopant into the first/wood well region 220 by using an ion implantation process, for example, to re-use the heat treatment process. ^ Also) formed by doping. As shown in Fig. 7, a patterned nitride layer (not shown) is formed on the substrate 2(1). This patterned nitride fill is formed, for example, by a magnetic lithography method to define the position of the field oxide layer 230. Thereafter, an n-type stepless 270' is formed, for example, by lithography and ion implantation process. Weaving 're-side bribery nitrogen cut layer as material, and oxidation system 201251007 process to form field oxide layer 23〇. The oxide layer 23() is used as an isolation structure, but the isolation structure is not limited to the Weihua layer 23G, and the insulation member such as Kecheng _t^(shaibwtreneh ls〇iatl〇n, STI). In the present embodiment, the field oxide layer 23 is formed in the first deep well region 22G and protrudes from the surface of the substrate. Then, for example, a lithography and ion implantation process P2 is performed to form a -p-type doped region in the second deep well region 250, wherein the doping concentration of the first doping region is higher than that of the second deep well region The doping concentration of 25G is formed by a gradient-type doping concentration p-type dopant as shown in FIG. 8, forming a gate dielectric layer 242 and a gate electrode - in the first doping region 260 and Substrate 21 () between the immersions of 27 〇' is further added: the case: it covers a portion of the field oxide layer 23 〇 and has a playground runway layout shape. The gate dielectric layer 242 and the gate electrode 24 are well known in the art and are therefore not contemplated. The method of forming is as shown in FIG. 9, using, for example, lithography and ion implantation process 1>3, forming a N-type nudge and _ in the field oxide 23〇3=Γ deep well area 220,曰, and simultaneously formed in the first doping region 26〇 of the other side of the field subtraction layer 230—the doping of the common job is extremely low. Correction, the same as the _ occupational shadow and ion implantation process p into the lithography and ion implantation process p4 part of the shared source is Xiao, that is, a lightly doped N-type second doped region 282 is formed. 15 201251007 As shown in FIG. 10, for example, an etch lithography process is applied to the gate electrode 2 to form a sidewall 246. Then, for example, the first deep well region 220 on the side of the morphing layer 230 around the lithography and ion cloth 44 is formed with a double exchange: 5 field oxide 270, and simultaneously on the field oxide layer, the first side on the other side. The dummy region _ medium = the heavily doped N-type common source (not shown). In addition, the re-profit 4 has a system (4) to form a plurality of heavily doped p-type islands and ion implants 284, and does not carry out the partial lithography and ion implantation process Ρ6 Forming a heavily doped _ type second doping region 282 formed by a / knife, a source, and an island-shaped third doped region 284 - a common source 28 〇 = region to be invented by the laterally diffused MOS device 200 production. b. Completion of the present invention, the present invention provides a manufacturing method thereof, which has a first, monthly gold-oxygen semiconductor device and an electrical region identical to the first doped region, and the second deep brother-I1 Therefore, the laterally diffused MOS device of the present invention has a first-doped impurity concentration gradient structure. In this way, “the gradual addition of components can solve the problem of the conventionally-doped-region laterally diffused MOS and the difference in doping concentration is too large; the problem of different doping properties is It can reduce the lateral diffusion of gold oxides, the distribution of non-resistance / B (crash voltage) value, and the change of 4 Μ 通 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明It is located in the buried sound upper layer, which is used as a current flow down and leakage. Especially in the second deep well area 16 201251007 [Picture of simple description] Figure 1 is a conventional lateral diffusion MOS device 2 is a top view and a cross-sectional view of a laterally diffused gold-oxygen half according to a first preferred embodiment of the present invention. FIG. 3 is a cross-sectional view of a laterally diffused gold-oxygen half according to a second preferred embodiment of the present invention. Fig. Conductor element conductor element 苐4 to Fig. 1 illustrates a method of fabricating the integrated element of the present invention. Lateral diffusion oxynitride of the preferred embodiment [Key element symbol description] 100, 200, 300: Laterally diffused MOS devices 110, 210: substrate 120: N-wells 130, 230: field oxide layers 140, 240: gates 150, 246 I sidewalls 160: P-doped regions 170: sources 180, 270, 270', 270"::: and pole 17 201251007 220: first deep well area 242: gate dielectric layer 244: gate electrode 250: second deep well region 260: first doped region 280, 280': common source Pole 282, 282': second doped region 282a: source contact plug 284, 284': island-shaped third doped region 284a: substrate contact plug 290: doped region 310: epitaxial layer 320: buried Layer SI, S2: interface PI, P2, P3, P4, P5: lithography and ion implantation process 18