JPS571258A - Insulated gate semiconductor device - Google Patents

Insulated gate semiconductor device

Info

Publication number
JPS571258A
JPS571258A JP7482380A JP7482380A JPS571258A JP S571258 A JPS571258 A JP S571258A JP 7482380 A JP7482380 A JP 7482380A JP 7482380 A JP7482380 A JP 7482380A JP S571258 A JPS571258 A JP S571258A
Authority
JP
Japan
Prior art keywords
layer
drain
concentration
substrate
neighborhood
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7482380A
Other languages
Japanese (ja)
Other versions
JPS6331944B2 (en
Inventor
Shuji Kubo
Tadashi Uno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP7482380A priority Critical patent/JPS571258A/en
Publication of JPS571258A publication Critical patent/JPS571258A/en
Publication of JPS6331944B2 publication Critical patent/JPS6331944B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To contrive to enhance withstand voltage of the drain of an insulated gate semiconductor device without difficulty by a method wherein between the drain and a layer for prevention of reversion is separated, and a layer having lower concentration of impurity and being shallower than the drain is provided between them on the surface of the substrate. CONSTITUTION:An SiO2 layer 20 is formed sufficiently thick, the high concentration layer 8 being the same conductive type with the substrate 1 is formed in the lower layer, and moreover on the surface of the substrate 1 separating between the drain 5 and the layer 8, the layer 11 being the same conductive type with the substrate and having lower concentration than the substrate is formed as shallower than the drain 5. Accordingly withstand voltage of the drain is decided in accordance with the condition in the neighborhood of an interface between the same low concentration layer 10 and a gate oxide film 30 and the condition in the neighborhood of a contact face between the high concentration layer 8 and the low concentration layer 11. Because concentration and depth of the layers 10, 11 are as mentioned above, concentration of electric field in the neighborhood of the interface between the layer 10 and the oxide film 30 is mitigated, and on the contact face side of the layers 11, 8, by separating the drain 5 to the grade as depletion layer does not reach the layer 8 when the drain is reversely biased, concentration of electric field in the neighborhood of the contact face of the layers 11, 8 is also mitigated, and the MOS device having high withstand voltage can be obtained.
JP7482380A 1980-06-02 1980-06-02 Insulated gate semiconductor device Granted JPS571258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7482380A JPS571258A (en) 1980-06-02 1980-06-02 Insulated gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7482380A JPS571258A (en) 1980-06-02 1980-06-02 Insulated gate semiconductor device

Publications (2)

Publication Number Publication Date
JPS571258A true JPS571258A (en) 1982-01-06
JPS6331944B2 JPS6331944B2 (en) 1988-06-27

Family

ID=13558411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7482380A Granted JPS571258A (en) 1980-06-02 1980-06-02 Insulated gate semiconductor device

Country Status (1)

Country Link
JP (1) JPS571258A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5964032A (en) * 1982-09-08 1984-04-11 クレア−・バ−ナデツト・モデル Method and apparatus for sampling membrane of uterus
JPS6064473A (en) * 1983-09-20 1985-04-13 Seiko Epson Corp Mos type transistor
US4665418A (en) * 1983-01-10 1987-05-12 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63173655A (en) * 1987-01-13 1988-07-18 Canon Inc Thermal recorder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS564280A (en) * 1979-06-25 1981-01-17 Toshiba Corp Insulated gate type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS564280A (en) * 1979-06-25 1981-01-17 Toshiba Corp Insulated gate type field effect transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5964032A (en) * 1982-09-08 1984-04-11 クレア−・バ−ナデツト・モデル Method and apparatus for sampling membrane of uterus
JPH0340613B2 (en) * 1982-09-08 1991-06-19
US4665418A (en) * 1983-01-10 1987-05-12 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
JPS6064473A (en) * 1983-09-20 1985-04-13 Seiko Epson Corp Mos type transistor

Also Published As

Publication number Publication date
JPS6331944B2 (en) 1988-06-27

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