JP3264110B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage and low breakdown voltage MO.
The present invention relates to a method for manufacturing an S transistor integrated type semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in a high-voltage and low-voltage integrated CMOSIC having different gate oxide film thicknesses, at the time of manufacture, ion implantation of LDD (Lightly doped drain) (so-called low-concentration ion implantation) and sidewalls are performed. Steps such as part formation and source / drain ion implantation (so-called high-concentration ion implantation) are separately provided for the high breakdown voltage part and the low breakdown voltage part. For example, in the LDD ion implantation, the energy and the dose are different between the high breakdown voltage portion and the low breakdown voltage portion, or a step of additionally etching a thick gate oxide film in the high breakdown voltage portion after forming the sidewall is required.

However, in these cases, the number of steps, that is, the manufacturing cost increases, and the additional etching after the formation of the side wall portion causes an etching rate due to the instability of the process itself (remaining film, surface roughness) and the area ratio of resist / SiO _2. There is a problem that it changes drastically and it is necessary to determine etching conditions for each device.

FIG. 15 shows a high breakdown voltage and low breakdown voltage integrated CMO.
1 shows a configuration of an SIC. This high and low withstand voltage integrated CMOSI
C forms a first n-type well region 2 and a second n-type well region 3 in a p-type silicon semiconductor substrate 1 to form a first n-type well region 3.
Forming a first p-type well region 4 in the type well region 2;
A low breakdown voltage CMOS transistor, that is, a p-channel MOS transistor Qp ₁ and an n-channel MOS transistor Q are provided in the n-type well region 2 and the p-type well region 4 which are separated from each other by a selective oxide layer (a so-called LOCOS oxide layer) 5.
n ₁ is formed, and a high-voltage CMOS transistor, that is, a p-channel MOS transistor Qp ₂ and an n-channel MOS transistor Qn ₂ are formed in the second n-type well region 3 and the p-type substrate region 1A.

The low-breakdown-voltage p-channel MOS transistor Qp ₁ has a gate electrode 7 made of polycrystalline silicon formed via a thin gate oxide film 6, a p-type source region 9 and a drain region having an LDD structure. And 10.

An n-channel MOS transistor Qn ₁ of a low breakdown voltage system has a gate electrode 7 formed via a thin gate oxide film 6 and an n-type source region 11 and a drain region 12 similarly having an LDD structure. It is configured to have.

The high breakdown voltage p-channel MOS transistor Qp ₂ has a gate electrode 7 formed through a thick gate oxide film 13 and a p-type source region 14 and a drain region 15 similarly having an LDD structure. It is configured to have.

The high-breakdown-voltage n-channel MOS transistor Qn ₂ has a gate electrode 7 formed through a thick gate oxide film 13 and an n-type source region 16 and a drain region 17 similarly having an LDD structure. It is configured to have.

Reference numeral 8 denotes a side wall portion made of, for example, SiO ₂ formed on the side surface of each gate electrode 7.
In addition, under the LOCOS oxide layer 5 for each element isolation, a contact region 19 for applying a predetermined potential to the corresponding channel stop region 18 and each well region and substrate region in advance (only a part thereof is shown in the drawing). Is formed).

FIGS. 16 to 20 show another example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC. In FIG.
5 of the low voltage p-channel MOS transistor (gate oxide film thickness 20 nm) Qp ₁ shows a high-voltage p-channel MOS transistor (gate oxide film thickness 110 nm) Qp ₂ as a representative, but will be described also with reference to FIG. 15.

First, as shown in FIG. 16A, after forming the well regions 2, 3 and 4, the LOCOS oxide layer 5 and the like, the element forming region 2 including the low breakdown voltage portion 21 and the high breakdown voltage portion 22 is formed.
A gate oxide film (SiO ₂ ) 25 having a thickness of, for example, 95 nm is formed on the entire surfaces of the gate electrodes 3 and 24 by thermal oxidation.

Next, as shown in FIG.
The gate oxide film 25 on the second side is covered with a resist layer 26, and the gate oxide film 25 on the low breakdown voltage portion 21 side is selectively removed by wet etching.

Next, as shown in FIG. 17C, the resist layer 2
After removing 6, the surfaces of the element forming regions 23 and 24 on the high withstand voltage portion 22 and the low withstand voltage portion 21 side are respectively thermally oxidized to form the gate oxide film 6 with a thickness of 20 nm on the low withstand voltage portion 21 side. On the high withstand voltage portion 22 side, thermal oxidation is added to form the gate oxide film 13 having a thickness of 110 nm.

Next, for example, a polycrystalline silicon film, which is a gate electrode material, is deposited and patterned, and FIG.
As shown in (1), the gate electrode 7 is formed on the gate oxide film 6 having a small thickness on the side of the low breakdown voltage portion 21, and the gate electrode 7 is formed on the gate oxide film 13 having a large thickness on the side of the high breakdown voltage portion 22. On the low breakdown voltage portion 21 side, a part of the gate insulating film 6 is also etched during the patterning of the gate electrode 7, and the gate insulating film 6 has a thickness of about 10 nm in portions other than the gate portion.

Next, as shown in FIG.
While the second side is covered with the resist layer 27, the self-aligned LDD is applied to the low withstand voltage portion 21 side using the gate electrode 7 as a mask.
P-type impurities 28 are ion-implanted, for example, at a dose of 3.5 × 10 ¹³ cm ⁻² and low impurity concentration regions 9a and 10a.
To form

Next, as shown in FIG.
While the one side is covered with the resist layer 29, the LDD p-type impurity 30 is ion-implanted, for example, at a dose of 6 × 10 ¹² c.
The m ^-2 impurity concentration regions 14a and 15a are formed.

Next, a SiO ₂ film is formed on the entire surface and etched back to form sidewall portions 8 of SiO ₂ on the side surfaces of each gate electrode 7 as shown in FIG. 19G.

Next, as shown in FIG. 19H, with the resist layer 31 covering the low breakdown voltage portion 21, a thick gate oxide on the active region (that is, the region corresponding to the source and drain) on the high breakdown voltage portion side 22 is formed. The film 13 is etched away (so-called additional etching is performed). In this etching, since the area of the region to be etched on the high withstand voltage portion 22 side is usually smaller than the area on the low withstand voltage portion 21 side, the remaining film, Surface roughness occurs, and the etching rate changes depending on the resist / SiO ₂ area ratio, so that the etching conditions differ for each device. Further, the width of the side wall portion 8 is also changed due to the influence of the etching.

Next, as shown in FIG. 20, in this example, a high impurity concentration region 9b, 10b, 14b, and 15b are formed, and each LD is formed.
D-structure source regions 9, 14 and drain regions 10, 1
5 is formed. The n-channel MOS transistor Q
Except for selectively performing LDD ion implantation and source / drain ion implantation for n ₁ and Qn ₂ , the same steps as in the above example are performed. In this way, a high and low withstand voltage integrated CMOS IC is manufactured.

On the other hand, there is a method in which additional etching is not performed after the formation of the sidewall portion. However, since all the processes are separately performed in the high breakdown voltage portion and the low breakdown voltage portion, the number of processes, that is, the manufacturing cost is further increased. High and low withstand pressure integrated C
Low cost, which is one of the advantages of the MOSIC, is lost.

[0021]

SUMMARY OF THE INVENTION As described above,
In a low-withstand-voltage integrated CMOS IC, it is required to achieve a reduction in the number of steps and a stabilization of the process itself by using a common high- and low-withstand-voltage process without impairing the conventional characteristics.

The present invention provides a method of manufacturing a semiconductor device which solves the above-mentioned problems.

[0023]

The method of manufacturing a semiconductor device according to the present invention SUMMARY OF THE INVENTION are respectively different gate insulating film thickness t _2, t ₁ high voltage MOS transistor Qp ₂ composed of, Qn ₂ and the low-voltage MOS transistor Qp ₁ and Qn _{1 In} the manufacturing method of the integrated semiconductor device, after forming the gate electrodes 66G to 69G of the high breakdown voltage portion and the low breakdown voltage portion, selective etching is performed while leaving the resist layer 64 for processing the gate electrode. The gate insulating films 62 and 61 having different thicknesses t ₂ and t ₁ on the active region in the portion and the low breakdown voltage portion are all removed, and thereafter, processes such as ion implantation and sidewall formation are performed in the high breakdown voltage portion and the low breakdown voltage portion. Make it common among departments.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device as described above, wherein the high withstand voltage MOS transistors Qp ₂ , Qn
₂ is formed in an offset gate structure in which a selective oxide layer 45a is formed on the drain side between the source and the drain, and gate electrodes 68G and 69G are formed between the selective oxide layer 45a and the source.

[0025]

In the method of manufacturing a semiconductor device according to the present invention, after forming the gate electrodes 62, 61 of the high breakdown voltage portion and the low breakdown voltage portion, selective etching is performed while leaving the gate electrode processing resist layer 76. Gate insulating films 6 having different thicknesses on the active regions in the high breakdown voltage portion and the low breakdown voltage portion, respectively.
By removing all of the oxide films 2 and 61, the oxide film 71 on the high breakdown voltage portion and the low breakdown voltage portion can be made to have the same film thickness in the subsequent oxidation treatment. Enable commonality. Therefore, the number of steps can be reduced without deteriorating characteristics.

In this manufacturing method, the high voltage MOS transistors Qp ₂ and Qn ₂ are provided with a selective oxide layer 45 a on the drain side between the source and the drain, and the selective oxide layer 4.
When the gate electrodes 68G and 69G are formed between the 5a and the source by the offset gate structure, the LDD ion implantation of the high breakdown voltage portion and the low breakdown voltage portion can be performed simultaneously under the same condition, that is, the optimum condition in the low breakdown voltage portion. . Therefore, the number of steps can be further reduced.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 5 show an embodiment of a high-voltage and low-voltage integrated CMOS IC according to the present invention, and are sectional views shown in the order of manufacturing steps.

In this embodiment, a low voltage MOS transistor is replaced by an LD.
And D structure, a high voltage MOS transistor, the LOCOS oxide layer is formed on the drain side between the source and drain, the offset gate structure where a gate electrode formed between the LOCOS oxide layer and the source [hereinafter, LOD (L LOCOS
O Ffset a case of the D rain) that the structure].

First, as shown in FIG. 1, a silicon semiconductor substrate 41 of a first conductivity type, for example, p-type, is provided with a second conductivity type, that is, n-type.
A first well region 42 and a second well region 43 are formed, and the first n-type well region 42 has a first conductivity type, that is, p type.
A mold well region 44 is formed.

Reference numeral 45 denotes a selective oxide layer (SiO ₂ ) (so-called LOCOS oxide layer), which is used for element isolation.
In each of the well regions 42, 43, and 44 under the OS oxide layer 45 and the substrate region, a channel stop region 46 of a corresponding conductivity type is provided in advance, and a contact region 48 for applying a predetermined potential to the well region and the substrate region (see FIG. Are shown only by ion implantation.

Further, the LOCOS oxide layer 45a for the offset drain formed in the element forming region 43a of the second n-type well region 43 and the element forming region 41a of the substrate 41 on the high breakdown voltage portion 40 side is formed later. region 51 ^- p is a low impurity concentration region which connects with that drain region
And n ⁻ region 52 are formed.

Then, on the element forming region 43a of the second n-type well region 43 and the element forming region 41a of the substrate 41 on the side of the high breakdown voltage portion 40, for example, a SiO ₂ film having a thick film thickness t ₂ is formed.
_{2 and the} like, and an element formation region 42a of the first n-type well region 42 on the low breakdown voltage portion 39 side is formed.
And the gate insulating film 6 by p-type well region 44 by the element formation regions 44a on a thin film thickness t _1, for example SiO ₂ or the like
Form one.

The gate insulating films 61 and 6 having different thicknesses
2 can be formed by, for example, the same method as that described above with reference to FIGS. 16A to 17C, and a detailed description thereof will be omitted.

An electrode material serving as a gate electrode, in this example, a polycrystalline silicon film 63 is deposited on the entire surface including the gate insulating films 61 and 62.

Next, as shown in FIG. 2, anisotropic etching, for example, RI
The polycrystalline silicon film 63 is patterned by E (reactive ion etching) to form a gate electrode 66G on the element formation region 42a of the first n-type well region 42 and a gate electrode 66G on the element formation region 44a of the p-type well region 44. Electrode 67G
A gate electrode 68G on the element formation region 43a of the second n-type well region 43 and the element formation region 41a of the substrate 41.
A gate electrode 69G is formed thereon. The gate electrodes 68G and 69G on the high withstand voltage portion 40 side are respectively formed in the element forming region 4
3a and the LOCOS oxide layer 45 in the element formation region 41a.
a is formed so as to extend over the LOCOS oxide layer 45a from one of the regions divided by a.

Next, as shown in FIG.
Resist layer 6 for processing 6G, 67G, 68G, 69G
4 while the etcher is replaced, the element formation regions 42a, 42a,
The gate insulating films 61 and 62 having different thicknesses t ₁ and t ₂ on the respective active regions 44a, 43a and 41a, that is, portions where the source region and the drain region are to be formed, are all etched off at the same time.

[0038] Upon this etching, the gate insulating film thickness t _2, t ₁ at a low-voltage unit 39 and the high-voltage section 40 are different, but the low-voltage portion 39 side is Re懼to be over-etched, SiO ₂ / Si There is no problem if you use an etcher with a high selectivity.

The subsequent steps are common to the low breakdown voltage section 39 and the high breakdown voltage section 40.

That is, as shown in FIG. 4, the surface of each of the gate electrodes 66G to 69G and each active region is oxidized by a normal oxidation process to form an oxide film 71. Thereby, the end of the gate electrode is also oxidized at the same time, thereby preventing the gate breakdown voltage from lowering.

Next, LDD ion implantation is performed. On this occasion,
If the high breakdown voltage portion has the LOD structure, the LDD ion implantation can be shared. That is, in the high breakdown voltage portion 40, the LOCOS oxide layer 45a of the offset portion is formed in a portion corresponding to the portion between the gate and the drain.
Since the ion implantation is not performed immediately below 5a, the L
It can be adjusted to the optimum concentration of DD (low impurity concentration region).

In this embodiment, LDD ions are selectively implanted by self-alignment using the LOCOS oxide layers 45 and 45a and the gate electrodes 66G to 69G as masks, for example, the element formation region 44a of the low breakdown voltage portion 39 and the high breakdown voltage portion 40. An n ⁻ region 73a is simultaneously formed in the element formation region 41a. Next, LDD ion implantation for the p-channel MOS transistor can be performed. In this example, a low impurity concentration region is formed by lateral diffusion after source / drain ion implantation described later.

Next, an SiO ₂ layer, for example, is deposited on the entire surface by a CVD method, and the low withstand voltage portion 39 and the high withstand voltage portion 40 are formed from the end of the gate insulating film to the side surface of the gate electrode by, for example, etch back by RIE. ₂ are simultaneously formed.

Next, source / drain ion implantation is performed selectively using a self-line using the gate electrodes 66G to 69G having the LOCOS oxide layer 45 and the side wall portions 76 as a mask. In this source / drain ion implantation, one is masked with a resist layer, and n-type impurities and p-type impurities are selectively ion-implanted as usual, though not shown. As a result, the low breakdown voltage portion 39 and the high breakdown voltage portion 40
The n ⁺ region 73b of the high impurity concentration region and the p ⁺ region 74b of the high impurity concentration region are formed in the corresponding portions. When boron is used as the p-type impurity, the diffusion speed of boron is higher than that of phosphorus, so that boron is diffused laterally from p ⁺ region 74b in the subsequent thermal process to form p ⁻ region 74a.
Is formed. Therefore, n ⁻ region 73a and n ⁺ region 73
b, the source regions 67S, 69S and the drain region 67
D, 69D are formed, and p ⁻ region 74a and p ⁺ region 74 are formed.
b, the source regions 66S, 68S and the drain region 66
D, 68D are formed. Thereafter, electrodes (not shown) connected to the corresponding source and drain regions are formed.

Thus, as shown in FIGS. 5 and 6 (an enlarged view of the low breakdown voltage portion) and FIG. 7 (an enlarged view of the high breakdown voltage portion), the low breakdown voltage p-channel MOS transistor Qp ₁ and the n-channel MOS transistor An integrated CMOS IC 75 comprising a CMOS comprising Qn ₁ and a CMOS comprising a p-channel MOS transistor Qp ₂ and an n-channel MOS transistor Qn ₂ having a high withstand voltage, that is, an integrated CMOS IC 75 having a high and low withstand voltage is obtained.

In the low breakdown voltage section, the MOS transistor having the LDD structure is used.
The transistors Qp ₁ and Qn ₁ are configured, and the MOS transistors Qp ₂ and Qn ₂ having the LOD structure are configured in the high breakdown voltage section. Any of the MOS transistors Qp ₁ , Qn ₁ ,
Qp ₂ and Qn ₂ have a configuration in which the gate insulating film terminates at the end of the gate electrode, and a sidewall portion is formed from the terminal of the gate insulating film to the side surface of the gate electrode.

According to the above-described embodiment, the gate electrode 66G
After forming ~ 69G, the gate insulating films 61 and 62 on the active regions of the low breakdown voltage portion 39 and the high breakdown voltage portion 40, that is, the source / drain formation regions are left by RIE while leaving the resist layer 64 for processing the gate electrode. By selectively removing all of them, in the next oxidation treatment, the low breakdown voltage portion 39 and the high breakdown voltage portion 4 are formed.
The thickness of the oxide film 71 formed on the active region 0 can be made substantially equal.

For this reason, the subsequent steps such as LDD ion implantation, side wall formation, source / drain ion implantation, etc. can be shared without providing separate high and low breakdown voltage parts, thereby reducing the number of steps. The manufacturing can be facilitated, and the manufacturing cost can be reduced.

In FIG. 3, when selectively removing the gate insulating film (61, 62) on the active region by RIE, the resist layer 64 on the substrate is removed because both the low breakdown voltage portion 39 and the high breakdown voltage portion 40 are removed by etching at a time. And etched SiO
Area ratio with the _two films (61, 62), ie, resist / SiO
_{2. The} area ratio is reduced, and the RIE process can be stabilized. At the same time, the decrease in the resist / SiO ₂ area ratio eliminates the dependency on the resist pattern, and the etching rate is not affected, so that it is not necessary to determine the etching conditions for each device.

Since the sidewall portions 76 in the low breakdown voltage portion 39 and the high breakdown voltage portion 40 are formed at the same time, and there is no etching step thereafter, the width of the sidewall portion 76 is stabilized in both the low breakdown voltage portion 39 and the high breakdown voltage portion 40. can do.

Further, the thickness of the oxide film 71 on the active region of the high breakdown voltage portion 40 and the low breakdown voltage portion 39 is made common and the MOS transistor of the high breakdown voltage portion 40 has the LOD structure. Can be commonly used for high and low breakdown voltage parts. That is, the dose can be adjusted to the optimum value of the low breakdown voltage portion, and the process can be simplified.

At the same time, in the high breakdown voltage portion 40, during the LDD ion implantation, the ion implantation is not performed by the LOCOS oxide layer 45a of the offset portion on the drain regions 68D and 69D side, but only on the source regions 68S and 69S side. However, the dose amount is higher than the concentration required for the original high withstand voltage, so that the resistance value of the source region decreases and a large current is obtained. As a result, low power consumption can be achieved while maintaining the withstand voltage.

Further, in this embodiment, the gate insulating film 6
1 and 62 terminate at the gate electrode end, and the gate insulating film 6
Since the sidewall portion 76 is formed from the terminal ends of the gate electrodes 1 and 62 to the side surface of the gate electrode, for example, when the size is further reduced and the source and drain regions having a shallower junction are required, the sidewall portion 76 is formed. The low impurity concentration region of the LDD can be formed by forming an impurity from an impurity-containing insulating material, for example, PSG or the like, and diffusing the impurity from the sidewall portion.

As described above, in this embodiment, the number of steps is increased due to the provision of separate steps in the conventional high and low withstand voltage portions, thus increasing the manufacturing cost, and the high withstand voltage after forming the side wall portion. Problems such as the instability of the process itself during the additional etching of the gate oxide film in the portion and the strong dependence of the etching rate on the resist / SiO ₂ area ratio, and the gate of the high breakdown voltage portion after the formation of the sidewall portion in order to solve the problems. It is possible to solve the problem of a further increase in the number of steps when the additional etching of the oxide film is stopped and the high and low withstand voltage portions are completely formed separately, and hence the manufacturing cost.

FIGS. 8 to 12 show an embodiment in which both the high breakdown voltage portion 40 and the low breakdown voltage portion 39 are applied to a high and low breakdown voltage integrated CMOS IC having an LDD structure.

In this example, as shown in FIG.
A second conductivity type, ie, an n-type first well region 42 and a second well region 43 are formed on a conductivity type, eg, a p-type silicon semiconductor substrate 41, and the first conductivity type, ie, p type, is formed in the first well region 42. A mold well region 44 is formed.

After a required conductivity type channel stop region 46 and a contact region 48 (only some of which are shown in the figure) are formed at corresponding positions by ion implantation, a LOCOS oxide layer 45 for element isolation is formed. I do.

Next, the element forming region 4 on the low breakdown voltage portion 39 side
A thin gate insulating film 61 with a thickness t ₁ is formed on 2a and 44a, and a thick gate insulating film 62 with a thick thickness t ₂ is formed on the element forming regions 43a and 41a on the high breakdown voltage portion 40 side. Thereafter, an electrode material, for example, a polycrystalline silicon film is deposited on the entire surface, and then, for example, R
Selective etching is performed by the IE to form each element forming region 42a,
The gate electrodes 66G, 6G are respectively formed on 44a, 43a, 41a.
Form 7G, 68G and 69G.

Next, as shown in FIG.
The etcher is switched while the resist layer 64 on 6G, 67G, 68G, 69G is left, and the film thickness on the active region of each element formation region 42a, 44a, 43a, 41a, that is, the source / drain formation region is changed by RIE. The gate insulating films 61 and 62 are all selectively etched away at the same time.

Next, as shown in FIG. 10, an oxidation process is performed to form an oxide film 71 on the surface of each of the gate electrodes 66G to 69G, and to form each of the element forming regions 42a, 44a, 43.
An oxide film 71 having the same thickness is formed on the active regions a and 41a. Then, LDD ions of n-type impurities are selectively implanted into the element formation region 44a of the low withstand voltage portion 39 and the element formation region 41a of the high withstand voltage portion 40 in separate steps.
^- forming a region 76a ^- region 73a and n.

Next, as shown in FIG.
Element forming region 42a and the element forming region 4 of the high breakdown voltage portion 40
3a is selectively LDD of p-type impurities in separate processes.
Ion implantation is performed to form a p ^- region 77a and a p ^- region 7 respectively.
8a is formed.

Next, for example, an SiO ₂ layer is deposited on the entire surface by CVD, and the gate electrodes 66G to 69G of the high breakdown voltage portion 40 and the low breakdown voltage portion 39 are etched back by RIE, for example.
Forming the sidewall portion 76 by SiO ₂ to the side of. Next, common source / drain ion implantation is performed on the low breakdown voltage portion 39 and the high breakdown voltage portion 40. That is, an n-type impurity is ion-implanted at a high concentration into the element formation region 44a and the element formation region 41a to simultaneously form the n ⁺ region 73b, and the p-type impurity is increased into the element formation region 42a and the element formation region 43a in another step. P ⁺ regions 74b are simultaneously formed by ion implantation at a concentration.

Thereafter, although not shown, each corresponding source region 66S, 67S, 68S, 69S and drain region 66S
The electrodes connected to D, 67D, 68D, and 69D are formed.

In this manner, as shown in FIGS. 12 and 13 (enlarged view of the low breakdown voltage portion) and FIG. 14 (enlarged view of the high breakdown voltage portion), both the low breakdown voltage portion 39 and the high breakdown voltage portion 40 have the LDD structure. CMOS IC integrally including MOS transistors Qp ₁ , Qn ₁ , Qp ₂ , Qn ₂ , ie, a high and low withstand voltage integrated CM
OSIC 80 is obtained.

The high and low withstand voltage integrated CMOS IC 80
Also, after the gate electrodes 66G to 69G are formed, the element formation region 42 in the low breakdown voltage portion 39 and the high breakdown voltage portion 40 while the gate electrode processing resist layer 64 is left.
By removing all of the gate insulating films 61 and 62 on the active regions a, 44a, 43a and 41a, an oxide film 71 of the same thickness is formed on the active regions of the high and low breakdown voltage parts by the next oxidation treatment. You.

Accordingly, the subsequent steps such as formation of the sidewall portion 76 and source / drain ion implantation can be made common to the high and low breakdown voltage portions, and the number of steps can be reduced.

In addition, RIE of the gate insulating films 61 and 62
/ SiO ₂ on substrate during selective etching
The selective etching process is stabilized by reducing the area ratio. There is no dependency on the resist pattern, and it is not necessary to determine the etching conditions for each device. The width of the sidewall portion can be stabilized.

Further, by forming the sidewall portion with an impurity-containing insulating material, for example, PSG or the like, a low-concentration region of the LDD can be formed by further impurity diffusion, and the source of the LDD structure having a shallower junction can be formed. , A drain region can be formed, and a MOS transistor operating at a higher speed can be obtained.

[0069]

According to the method of manufacturing a semiconductor device according to the present invention, in a high and low withstand voltage integrated type semiconductor device, processes such as ion implantation after a gate electrode and formation of a side wall portion are performed for both high and low withstand voltage portions. The number of steps can be reduced, the number of steps can be reduced, the manufacturing can be simplified, and the manufacturing cost can be reduced. In addition, when the gate insulating film is selectively etched, since the resist / insulating film area ratio on the substrate is small, the selective etching is stabilized, and it becomes unnecessary to determine the etching conditions for each device. The width of the sidewall portion can be stabilized by simultaneously forming the sidewall portions of the high and low breakdown voltage portions.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram (part 1) illustrating an example of a high and low withstand voltage integrated CMOS IC according to the present invention.

FIG. 2 is a manufacturing process diagram (part 2) illustrating an example of a high and low withstand voltage integrated CMOS IC according to the present invention.

FIG. 3 is a manufacturing process diagram (part 3) illustrating an example of a high and low withstand voltage integrated CMOS IC according to the present invention;

FIG. 4 is a manufacturing process diagram (part 4) illustrating an example of a high and low withstand voltage integrated CMOS IC according to the present invention.

FIG. 5 is a manufacturing process diagram (part 5) illustrating an example of a high-voltage and low-voltage integrated CMOS IC according to the present invention;

FIG. 6 is an enlarged view of a low withstand voltage section of FIG. 5;

FIG. 7 is an enlarged view of a high withstand voltage section of FIG. 5;

FIG. 8 is a manufacturing process diagram (part 1) showing another example of a high and low withstand voltage integrated CMOS IC according to the present invention.

FIG. 9 is a manufacturing process diagram (part 2) illustrating another example of the high-voltage and low-voltage integrated CMOS IC according to the present invention.

FIG. 10 shows a high-voltage and low-voltage integrated CMOSIC according to the present invention.
It is a manufacturing process figure (the 3) which shows other examples.

FIG. 11 is a high-voltage and low-voltage integrated CMOSIC according to the present invention;
It is a manufacturing process figure (the 4) which shows other examples.

FIG. 12 is a high-voltage and low-voltage integrated CMOSIC according to the present invention;
It is a manufacturing process figure (the 5) which shows the other example.

FIG. 13 is an enlarged view of the low breakdown voltage portion of FIG.

FIG. 14 is an enlarged view of the high breakdown voltage section of FIG.

FIG. 15 is a configuration diagram of a conventional high and low withstand voltage integrated CMOS IC.

16A is a manufacturing process diagram of a main part showing an example of a conventional method for manufacturing a high-voltage, low-voltage integrated CMOS IC. FIG. B is a manufacturing process diagram of a main part showing an example of a conventional method for manufacturing a high-voltage, low-voltage integrated CMOS IC.

FIG. 17C is a manufacturing process diagram of a main part showing an example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC. D is a process drawing of an essential part showing an example of a conventional method of manufacturing a high-voltage, low-voltage integrated CMOS IC.

FIG. 18E is a manufacturing process diagram of an essential part showing an example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC. F is a manufacturing process diagram of a main portion showing an example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC.

FIG. 19 is a manufacturing process diagram of main parts showing an example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC. H is a manufacturing process diagram of an essential part showing an example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC.

FIG. 20 is a manufacturing process diagram of main parts showing an example of a conventional method for manufacturing a high-voltage and low-voltage integrated CMOS IC.

[Explanation of symbols]

39 low breakdown voltage part 40 high breakdown voltage part 41 p-type silicon semiconductor substrate 42, 43 n-type well region 44 p-type well region 41a, 42a, 43a, 44a element formation region 45, 45a LOCOS oxide layer 46 channel stop region 47 contact region 51 , 52 Low concentration region 61, 62 Gate insulating film 64 Resist layer 66G, 67G, 68G, 69G Gate electrode 66S, 67S, 68S, 69S Source region 66D, 67D, 68D, 69D Drain region 76 Side wall portion Qp ₁ , Qp ₂ p-channel MOS transistor Qn ₁ , Qn ₂ n-channel MOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8234-21/8238 H01L 27/08 H01L 27/088-27/092

Claims (2)

(57) [Claims] In a method of manufacturing a high-voltage MOS transistor and a low-voltage MOS transistor integrated semiconductor device each having a different gate insulating film thickness, after forming a gate electrode of a high-voltage portion and a low-voltage portion, a gate is formed. Perform selective etching while leaving the resist layer for electrode processing,
The gate insulating films having different thicknesses on the active regions in the high breakdown voltage portion and the low breakdown voltage portion are all removed, and thereafter, processes such as ion implantation and formation of a sidewall portion are commonly performed in the high breakdown voltage portion and the low breakdown voltage portion. A method of manufacturing a semiconductor device. 2. The high breakdown voltage MOS transistor has an offset gate structure in which a selective oxidation layer is formed on a drain side between a source and a drain, and a gate electrode is formed between the selective oxidation layer and the source. The method for manufacturing a semiconductor device according to claim 1, wherein: