JP4560809B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor integrated circuit device.SetRegarding manufacturing technology, in particular, the gate structure of fine MISFET (Metal Insulator Semiconductor Field Effect Transistor).MadeThe present invention relates to a technology effective when applied to manufacturing.
[0002]
[Prior art]
In order to reduce the resistance of the gate electrode of the MISFET, a so-called polymetal gate in which a refractory metal such as tungsten is stacked on a polycrystalline silicon film is employed.
[0003]
On the other hand, when the gate electrode is etched, the gate insulating film below the gate electrode is also etched, and the breakdown voltage of the gate insulating film is lowered. Therefore, the gate electrode sidewall and the silicon substrate surface in the vicinity of the gate electrode are thermally oxidized and heated. A so-called light oxidation process for forming an oxide film is performed.
[0004]
For example, Japanese Patent Application Laid-Open No. 10-335652 discloses a technique related to a light oxidation treatment of a polymetal gate.
[0005]
[Problems to be solved by the invention]
In this light oxidation treatment of the polymetal gate, the refractory metal constituting the polymetal gate is very easily oxidized, and the resistance value increases due to the oxidation of the refractory metal film. A process of oxidizing only the underlying polycrystalline silicon film and the substrate surface while preventing the above has been studied.
[0006]
For example, when light oxidation (wet hydrogen oxidation) is performed in a steam / hydrogen mixed gas, only silicon (polycrystalline silicon, silicon substrate) is selectively oxidized without oxidizing the metal film. Can be oxidized.
[0007]
However, regarding the semiconductor integrated circuit device subjected to the wet hydrogen oxidation process, the present inventors have recognized the following problems.
[0008]
That is, the refresh characteristics of DRAM (Dynamic Random Access Memory) memory cells are poor, and problems such as a kink phenomenon are observed in the p-channel MISFET of the peripheral circuit. Further, the threshold V of the n-channel MISFET constituting the memory cell_thIs high and the subthreshold coefficient is large. In addition, problems such as a large cell leakage current were observed.
[0009]
As a result of diligent examination of the problem, the present inventors have found that the cause of the problem is that the thickness of the light oxide film of the semiconductor integrated circuit device subjected to the wet hydrogen oxidation process is as thin as 5 nm or less. The analysis was as follows. The light oxide film has a thickness of 5 nm or less because, depending on the oxidation conditions of the wet hydrogen oxidation (water vapor / hydrogen mixture ratio, processing time, etc.), abnormal oxidation occurs in the refractory metal film such as a tungsten film, This is because it causes a short circuit between the gate electrodes and the like, and only a film thickness of 5 nm or less can be secured under the condition for preventing this abnormal oxidation.
[0010]
That is, as will be described in detail later, a sidewall spacer film made of a silicon nitride film is laminated on the light oxide film, and a negative charge is formed at the interface between the silicon nitride film and the light oxide film. In the n-channel MISFET constituting the memory cell, the negative charge causes n^-The surface of the mold diffusion layer is depleted, and the junction leakage current increases due to the interface state between the light oxide film and the substrate. N^-When the surface of the type diffusion layer is depleted, the effective gate insulating film thickness is increased at the end portion of the gate electrode, so that the subthreshold coefficient is increased. And n^-The threshold potential V of the MISFET for the type diffusion layer to effectively approach the offset structure_thBecomes higher.
[0011]
In addition, the junction electric field of the cell transistor of the memory cell is increased under the influence of the negative charge at the end of the gate electrode, and the refresh characteristic is deteriorated.
[0012]
Furthermore, if negative charges are present at the end of the gate electrode, the n-type substrate (well) is depleted in the p-channel MISFET of the peripheral circuit._thIn particular, when a trench-type element isolation structure is adopted, a recess phenomenon occurs in which the isolation oxide film in the trench recedes (FIG. 22), and a kink phenomenon (the gate insulating film is locally formed at the end of the gate electrode). The electric field due to the gate voltage is concentrated on this portion, and the drain current (A) flows even at a low gate voltage (V) (the phenomenon shown in FIG. 21).
[0013]
An object of the present invention is to form a thick light oxide film by thermally oxidizing the silicon substrate surface on the side of the gate electrode after forming a sidewall film made of a thin silicon nitride film on the side wall of the gate electrode. It is to improve refresh characteristics. Another object of the present invention is to provide a threshold value V of the n-channel MISFET constituting the memory cell._thIn other words, the increase in the subthreshold coefficient is suppressed, and further, the cell leakage current is reduced.
[0014]
Another object of the present invention is to reduce the occurrence of a kink phenomenon in a p-channel MISFET in a peripheral circuit.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0025]
  (1) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming a gate insulating film on a semiconductor substrate; and (b) a polycrystalline silicon film, a refractory metal film and a nitriding film on the gate insulating film. By sequentially forming and patterning silicon filmsIncluding the polycrystalline silicon film and the refractory metal filmForming a gate electrode; and (c)Performing wet hydrogen oxidation to form a first light oxide film on the side surface of the polycrystalline silicon film and the surface of the semiconductor substrate;(d) The gate electrodeofOn the side wallUsing silicon nitride filmForming a sidewall film; (e) In an oxidizing atmosphereHeat treatmentAndThe gate electrodeAnd a second surface of the semiconductor substrate not covered with the sidewall film.A step of forming a light oxide film;f)The semiconductor substrateImpurities are injected intodo itForming a low concentration diffusion layer; andTheHave.
  (2) In another embodiment of the present invention, a method of manufacturing a semiconductor integrated circuit device includes an n-channel MISFET for information transfer formed in a memory cell formation region of a semiconductor substrate, a memory cell including a capacitive element, and a peripheral circuit. A method of manufacturing a semiconductor integrated circuit device having an n-channel MISFET and a p-channel MISFET for CMIS configuration formed in a formation region, comprising: (a) forming a gate insulating film on a semiconductor substrate; (B) A polycrystalline silicon film, a refractory metal film and a silicon nitride film are sequentially formed on the gate insulating film and patterned to form the polycrystalline silicon film and the high-concentration film in the memory cell region and the peripheral circuit region. Forming a gate electrode including a melting point metal film; and (c) performing wet hydrogen oxidation to form the memory cell. Forming a first light oxide film on a side surface of the polycrystalline silicon film of the gate electrode formed in the region and the peripheral circuit region, and on a surface of the semiconductor substrate in the memory cell region and the peripheral circuit region When,
(D) forming a silicon nitride film that covers the semiconductor substrate in the memory cell region and the peripheral circuit region; and (e) performing anisotropic etching on the semiconductor substrate in the memory cell region. By removing the silicon nitride film, a sidewall film made of the silicon nitride film is formed on the side surface of the gate electrode formed in the memory cell region and formed on the semiconductor substrate in the peripheral circuit region Leaving the silicon nitride film left, (f) performing a heat treatment in an oxidizing atmosphere to form a second light oxide film on the surface of the semiconductor substrate in the memory cell region, and (g) And implanting impurities into the semiconductor substrate in the memory cell region to form a low concentration diffusion layer.
  (3) In still another embodiment of the present invention, a method of manufacturing a semiconductor integrated circuit device includes an information transfer n-channel MISFET formed in a memory cell formation region of a semiconductor substrate, a memory cell including a capacitive element, and a peripheral device. A method of manufacturing a semiconductor integrated circuit device having a CMIS configuration n-channel MISFET and a p-channel MISFET formed in a circuit formation region, comprising: (a) forming a gate insulating film on a semiconductor substrate; (B) A polycrystalline silicon film, a refractory metal film and a silicon nitride film are sequentially formed on the gate insulating film and patterned to form the polycrystalline silicon film and the peripheral circuit region in the memory cell region and the peripheral circuit region. A step of forming a gate electrode including a refractory metal film, and (c) wet hydrogen oxidation, Forming a first light oxide film on a side surface of the polycrystalline silicon film of the gate electrode formed in the recell region and the peripheral circuit region, and on a surface of the semiconductor substrate in the memory cell region and the peripheral circuit region; (D) forming a silicon nitride film covering the semiconductor substrate in the memory cell region and the peripheral circuit region; and (e) performing anisotropic etching to form the semiconductor substrate in the memory cell region. By removing the silicon nitride film formed on the semiconductor substrate in the region for forming the p-channel type MISFET in the silicon nitride film and the peripheral circuit region formed thereon, the memory cell region is formed. The silicon nitride film is formed on the side wall of the formed gate electrode and the side wall of the gate electrode of the p-channel type MISFET. Forming a side wall film, and leaving the silicon nitride film formed on the semiconductor substrate in a region of the peripheral circuit region where the n channel MISFET for CMIS configuration is formed; ) Heat treatment is performed in an oxidizing atmosphere, and a second write is applied to the surface of the semiconductor substrate in the memory cell region and the surface of the semiconductor substrate in the region in which the p-channel MISFET is formed in the peripheral circuit region. Forming an oxide film; and (g) forming a low-concentration diffusion layer by implanting impurities into the semiconductor substrate in the memory cell region.
[0026]
  According to the present invention, after forming the sidewall film on the side wall of the gate electrode,SecondSince the light oxide film is formed, the light oxide film can be thickened while preventing oxidation of the tungsten film in the gate electrode. When applied to an information transfer n-channel MISFET, the refresh characteristic of the memory cell is improved. The junction leakage current of the n-channel type MISFET constituting the memory cell can be reduced. Further, the subthreshold coefficient can be reduced, and an increase in the threshold potential Vth can be suppressed. Further, when applied to a p-channel type MISFET for CMIS configuration, it is possible to reduce the occurrence of the kink phenomenon of the p-channel type MISFET.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0028]
(Embodiment 1)
A method for manufacturing a DRAM according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS. The left part of each drawing showing the cross section of the substrate shows a region (memory cell array portion) where DRAM memory cells are formed, and the right part shows a peripheral circuit formation region.
[0029]
First, as shown in FIG. 1, an element isolation trench 2 having a depth of about 350 nm is formed by etching a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example.
[0030]
Thereafter, the semiconductor substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the groove. This silicon oxide film recovers damage caused by dry etching that has occurred on the inner wall of the groove, and also relieves stress generated at the interface between the silicon oxide film 5 embedded in the groove and the semiconductor substrate 1 in the next step. Form.
[0031]
Next, a silicon oxide film 5 having a thickness of about 450 to 500 nm is deposited on the semiconductor substrate 1 including the inside of the groove by a CVD (Chemical Vapor deposition) method, and the groove is formed by a chemical mechanical polishing (CMP) method. The upper silicon oxide film 5 is polished to flatten the surface.
[0032]
Next, after p-type impurities (boron) and n-type impurities (for example, phosphorus) are ion-implanted into the semiconductor substrate 1, the impurities are diffused by a heat treatment at about 1000 ° C., so that the semiconductor substrate 1 in the memory cell array portion is p-type. A type well 3 is formed, and a p-type well 3 and an n-type well 4 are formed in the semiconductor substrate 1 in the peripheral circuit formation region. Here, the impurity concentration of the p-type well 3 and the n-type well 4 is determined by the desired threshold value V of the MISFET formed on these wells._thHas been adjusted to obtain.
[0033]
Next, as shown in FIG. 2, the surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) is wet-cleaned using a hydrofluoric acid-based cleaning solution, and then the p-type well is thermally oxidized at about 800 ° C. A clean gate oxide film 8 having a thickness of about 6 nm is formed on the surface of each of the 3 and n-type wells 4.
[0034]
Next, phosphorus (P) is 4 × 10 4 on the gate oxide film 8.²⁰/ Cm^ThreeA low-resistance polycrystalline silicon film 9a having a thickness of about 100 nm doped at a concentration of 1 nm is deposited by a CVD method. Subsequently, a WN film (not shown) with a film thickness of about 10 nm and a W film 9b made of a refractory metal such as tungsten with a film thickness of about 50 nm are deposited on the upper part by sputtering, and further on the upper part by CVD method. A silicon nitride film 10 having a thickness of about 200 nm is deposited. Next, for the purpose of stress relaxation of the W film 9b and densification (densification) of the WN film, heat treatment is performed at about 800 ° C. in an inert gas atmosphere such as nitrogen.
[0035]
Next, the silicon nitride film 10 is dry-etched using a photoresist film (not shown) as a mask to leave the silicon nitride film 10 in the region where the gate electrode is to be formed.
[0036]
Next, by using the silicon nitride film 10 as a mask, the W film 9b, the WN film (not shown) and the polycrystalline silicon film 9a are dry-etched, so that the polycrystalline silicon film 9a, N composed of WN film and W film 9b⁺A gate electrode 9 (gate length: 0.15 μm) is formed. Note that the gate electrode 9 formed in the memory cell array portion functions as the word line WL. Further, the gate oxide film 8 between the gate electrodes 9 may be left during the etching.
[0037]
Next, as shown in FIG. 3, a thin oxide film (hereinafter referred to as a light oxide film) 11a of about 4 nm is formed on the side wall of the polycrystalline silicon film 9a by wet hydrogen oxidation. As described above, according to wet hydrogen oxidation, only silicon (polycrystalline silicon, silicon substrate) can be selectively oxidized without oxidizing the tungsten film. By this oxidation, the surface of the semiconductor substrate 1 (p-type well 3, n-type well 4) is also slightly oxidized. Further, when the gate oxide film 8 is left as described above, this wet hydrogen oxidation can be omitted. 4A is an enlarged view of the gate electrode portion of the memory cell array portion (the memory cell selection MISFET Qs of the DRAM) of FIG. 3, and FIG. 4B is a peripheral circuit formation region (n-channel type MISFET Qn and p-channel type). It is an enlarged view of the gate electrode part of MISFETQp).
[0038]
Next, as shown in FIG. 5, a silicon nitride film having a thickness of about 10 nm is deposited on the semiconductor substrate 1 by the CVD method and anisotropically etched to form a sidewall film 12 on the side wall of the gate electrode 9. To do. 6A is an enlarged view of the gate electrode portion of the memory cell array portion (the DRAM memory cell selection MISFET Qs) in FIG. 5, and FIG. 5B is a peripheral circuit formation region (n-channel type MISFET Qn and p-channel type). It is an enlarged view of the gate electrode part of MISFETQp).
[0039]
Next, as shown in FIG. 7, light oxidation is performed in an oxidizing atmosphere to oxidize the surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) on both sides of the gate electrode, thereby producing a light oxide film 11b (claimed). A light oxide film as described in the above section. Here, the sum of the thicknesses of the light oxide film 11b and the light oxide film 11a (including the thickness of the gate oxide film 8 if it remains) is about 8 nm. 8A is an enlarged view of the gate electrode portion of the memory cell array portion (the memory cell selection MISFET Qs of the DRAM) of FIG. 7, and FIG. 8B is a peripheral circuit formation region (n-channel type MISFET Qn and p-channel type). It is an enlarged view of the gate electrode part of MISFETQp). The light oxide films 11a and 11b and the gate oxide film 8 in the actual gate electrode portion have a structure as shown in FIG. 9 due to the volume expansion due to oxidation and the occurrence of bird's beaks. In order to clarify the oxidation site in FIG. 8, the following cross-sectional views are also expressed in the same manner as FIG. 8.
[0040]
Next, as shown in FIG. 10, n-type impurities (phosphorus) are implanted into the p-type well 3 in the memory cell array portion on both sides of the gate electrode 9 (20 keV, 2 × 10¹³/ Cm²N)^-Type semiconductor region 13 is formed, and n-type impurity (arsenic) is implanted into p-type well 3 in the peripheral circuit formation region (20 keV, 2 × 10¹⁴/ Cm²N)^-P-type impurity (boron) is implanted into the n-type well 4 in the type semiconductor region 14 (5 keV, 2 × 10¹⁴/ Cm²) By p^-A type semiconductor region 15 is formed. In order to suppress the short channel effect, n of the p-type well 3 in the peripheral circuit formation region^-Type semiconductor region 14 and p of n-type well 4^-When forming the type semiconductor region 15, boron is 25 keV and 1 × 10 5 respectively.¹³/ Cm²Also, phosphorus is 50 keV, 2 × 10¹³/ Cm²By ion implantation at the n-type of the p-type well 3 in the peripheral circuit formation region.^-Type semiconductor region 14 and p of n-type well 4^-A reverse conductivity type semiconductor region (not shown) may be formed around the type semiconductor region 15.
[0041]
Next, after depositing a silicon nitride film having a thickness of about 40 nm on the semiconductor substrate 1 by CVD, anisotropic etching is performed to form sidewall spacers 16 on the sidewalls of the sidewall films 12.
[0042]
Next, an n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 3 in the peripheral circuit formation region to form n⁺Type semiconductor region 17 (source, drain) is formed, and p-type impurity (boron) is ion-implanted into n-type well 4 to form p⁺A type semiconductor region 18 (source, drain) is formed. 11A is an enlarged view of the gate electrode portion of the memory cell array portion (DRAM memory cell selection MISFETQs) of FIG. 10, and FIG. 11B is the gate electrode of the peripheral circuit formation region (p-channel type MISFETQp). It is an enlarged view of a part.
[0043]
Through the steps so far, the n-channel MISFET Qn and the p-channel MISFET Qp having the LDD (Lightly Doped Drain) structure source and drain are formed in the peripheral circuit formation region. These MISFETs constitute a complementary MISFET.
[0044]
Subsequently, as shown in FIG. 12, after a silicon oxide film 19 having a thickness of about 700 nm to 800 nm is deposited on the upper portion of the semiconductor substrate 1 by the CVD method, the silicon oxide film 19 is polished by the CMP method to flatten the surface. Turn into.
[0045]
Next, n in the memory cell array portion^-Contact holes 20 and 21 are formed on the upper surface of the semiconductor region 13 and the semiconductor substrate 1 (n^-The surface of the mold semiconductor region 13) is exposed.
[0046]
Next, the p-type well 3 (n^-N-type impurity (phosphorus or arsenic) is ion-implanted into the n-type semiconductor region 13)⁺A type semiconductor region 17 (source, drain) is formed. Through the steps so far, the memory cell selection MISFET Qs constituted of the n-channel type is formed in the memory cell array portion.
[0047]
Next, plugs 22 are formed inside the contact holes 20 and 21. In the plug 22, 4 × 10 4 of n-type impurities such as phosphorus (P) is formed on the silicon oxide film 19 including the insides of the contact holes 20 and 21.²⁰/ Cm^ThreeA low-resistance polycrystalline silicon film doped to some extent is deposited by CVD, followed by etching back (or polishing by CMP) to leave only in the contact holes 20 and 21.
[0048]
Next, as shown in FIG. 13, a silicon oxide film 23 having a film thickness of about 20 nm is deposited on the silicon oxide film 19 by the CVD method, and then the periphery is formed by dry etching using a photoresist film (not shown) as a mask. By dry-etching the silicon oxide film 23 in the circuit formation region and the silicon oxide film 19 below it, the source and drain of the n-channel MISFET Qn (n⁺The contact hole 24 is formed in the upper part of the p-type semiconductor region 17), and the source and drain (p⁺A contact hole 25 is formed in the upper part of the type semiconductor region 18). At the same time, a contact hole is formed above the gate electrodes of the p-channel MISFET and n-channel MISFET in a peripheral circuit formation region (not shown). Further, a through hole is formed above the plug 22 in the memory cell array portion.
[0049]
Next, a W film having a thickness of about 300 nm is deposited by CVD on the contact holes 24, 25, the contact hole on the gate electrode of the MISFET (not shown), and the inside of the through hole, and then silicon oxide is deposited. The plug 26 is formed by polishing the W film above the film 23 by the CMP method and leaving these films only in the contact holes 24, 25 and the through holes. Note that a thin WN film may be formed under the W film by a CVD method, and the plug 26 may be configured by two layers of the WN film and the W film.
[0050]
Next, the bit lines BL are formed above the plugs 26 in the memory cell array portion, and the first-layer wirings 30 to 33 are formed above the plugs 26 in the peripheral circuit formation region. For example, the bit line BL and the first-level wirings 30 to 33 are formed by depositing a W film of about 100 nm in thickness on the silicon oxide film 23 including the plug 26 by sputtering, and then using the photoresist film as a mask. The W film is formed by dry etching. Alternatively, a thin WN film may be formed under the W film by a CVD method, and the bit line BL and the first layer wiring may be configured by two layers of the WN film and the W film.
[0051]
Next, a silicon oxide film 34 having a film thickness of about 300 nm is deposited on the bit line BL and the first layer wirings 30 to 33 by a CVD method.
[0052]
Next, the silicon oxide film 34 in the memory cell array portion, the silicon oxide film 23 under the silicon oxide film 23 and the like are dry-etched to form a through hole 38.
[0053]
Next, a silicon nitride film 40 having a thickness of about 100 nm is deposited on the silicon oxide film 34 by the CVD method, and then a silicon oxide film 41 is deposited on the silicon nitride film 40 by the CVD method. The silicon oxide film 41 and the silicon nitride film 40 are dry-etched to form a groove 42 above the through hole 38.
[0054]
Next, a low-resistance polycrystalline silicon film having a thickness of about 50 nm doped with an n-type impurity such as phosphorus (P) is deposited on the silicon oxide film 41 including the inside of the groove 42 by the CVD method. Then, a photoresist film or the like is buried inside and the polycrystalline silicon film above the silicon oxide film 41 is etched back to leave only the inner wall of the groove 42. As a result, the lower electrode 43 of the information storage capacitive element C is formed along the inner wall of the groove 42.
[0055]
Next, a capacitive insulating film 44 made of a tantalum oxide film and an upper electrode 45 made of a TiN film are formed on the lower electrode 43. Through the steps up to here, a DRAM memory cell composed of the memory cell selection MISFET Qs and the information storage capacitive element C connected in series is completed.
[0056]
Next, a silicon oxide film 50 having a film thickness of about 100 nm is deposited on the semiconductor substrate 1 by the CVD method, and silicon oxide films 50 and 41 and silicon nitride films 40 on the first layer wirings 30 and 33 in the peripheral circuit formation region. Then, the through hole 51 is formed by dry etching the silicon oxide film 34. Thereafter, after the plug 52 is formed in the through hole 51, second-layer wirings 53, 54, 55 are formed on the plug 52 and the silicon oxide film 50. Next, a silicon oxide film or the like (not shown) is formed on the second layer wirings 53, 54, 55, whereby the DRAM of the present embodiment is substantially completed.
[0057]
Thus, in the present embodiment, since the light oxide films 11a and 11b are thickened, the amount of negative charge formed at the interface between the light oxide films 11a and 11b and the upper layer films 12 and 16 can be reduced. it can. As a result, the n-channel MISFET for information transfer n^-Depletion of the surface of the type semiconductor region 13 can be suppressed, and an increase in junction leakage current can be prevented. Further, since the leakage current due to the level of the surface of the depletion layer is reduced, it is possible to prevent the refresh characteristics of the DRAM from being deteriorated. Further, an increase in the junction electric field due to negative charges can be prevented, and deterioration of the refresh characteristics of the DRAM due to leakage due to the electric field can be prevented.
[0058]
FIG. 14 is a graph comparing the refresh time of the semiconductor integrated circuit device of the present invention with the case where the light oxide film 11a is formed only by wet hydrogen oxidation (FIG. 20). (A) shows the case where the light oxide film 11a is formed only by wet hydrogen oxidation and the light oxide film 11b is not formed (FIG. 20), and (b) shows the refresh time of the DRAM shown in the first embodiment. Show. As apparent from FIG. 14, in the case (a), the worst bit refresh is 10 ms, whereas in the case of the present embodiment shown in (b), the worst bit refresh is 100 ms. Here, the refresh time indicates a time (holding time) during which charges stored in the information storage capacitive element C connected to the memory cell selection MISFET Qs can be read, and indicates the worst holding time of 64 Mbits.
[0059]
Further, if the amount of negative charge formed at the interface between the light oxide films 11a and 11b and the sidewall films 12 and the sidewall spacers 16 which are upper layers thereof is large, the gate sidewall channel is depleted due to the influence of the negative charges. Threshold voltage V for easy_thHowever, if the light oxide films 11a and 11b are thick as in the present embodiment, the amount of negative charge can be reduced, and the kink of the p-channel type MISFET Qp can be prevented. Further, the subthreshold current (off current) can be reduced. Also, if the light oxide film is thin, charges formed when a high voltage stress is applied are easily trapped at the interface, and the threshold voltage V_thHowever, if the light oxide films 11a and 11b are thick as in the present embodiment, the charge generation rate decreases and the threshold V_thThus, it is possible to suppress the characteristic variation of the MISFET, and to improve the reliability of the MISFET.
[0060]
(Embodiment 2)
In the first embodiment, the memory cell selection MISFETQs in the memory cell array portion, the write oxide films 11a and 11b of the n-channel MISFETQn and p-channel MISFETQp in the peripheral circuit formation region are formed thick. Only the light oxide films 11a and 11b of the selection MISFET Qs may be formed thick. 15 to 17 are cross-sectional views showing the method of manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention in the order of steps. The steps up to the formation of the gate electrode 9 (9a, 9b) described with reference to FIGS. 1 and 2 are the same as those in the first embodiment, and thus the description thereof is omitted.
[0061]
The semiconductor substrate 1 shown in FIG. 2 is prepared, and as shown in FIG. 15, a light oxide film 11a of about 4 nm is formed on the sidewall of the polycrystalline silicon film 9a by wet hydrogen oxidation. Next, as shown in FIG. 16, a silicon nitride film 12a having a thickness of about 10 nm is deposited on the semiconductor substrate 1 by the CVD method, and the peripheral circuit formation region is covered with the resist film 2R, and then anisotropically etched. As a result, the sidewall film 12 is formed on the sidewall of the gate electrode 9 in the memory cell array portion. Next, after removing the resist film 2R, as shown in FIG. 17, light oxidation is performed in an oxidizing atmosphere to oxidize the surface of the semiconductor substrate 1 between the gate electrodes of the memory cell array portion, and the light oxide film 11b is formed. Form. Here, the sum of the thicknesses of the light oxide film 11b and the light oxide film 11a (including the thickness of the gate oxide film 8 if it remains) is about 8 nm. Since the peripheral circuit formation region is covered with the silicon nitride film 12a, no light oxide film is formed.
[0062]
Accordingly, the write oxide films 11a and 11b of the memory cell selection MISFET Qs are thicker than the write oxide films 11a of the n-channel MISFET Qn in the peripheral circuit formation region and the p-channel MISFET Qp in the peripheral circuit formation region.
[0063]
Since the process after removing the resist film 2R is the same as that in the first embodiment described with reference to FIGS. N^-Type semiconductor region and p^-The type semiconductor regions 14 and 15 may be formed before the formation of the silicon nitride film 12a or before the light oxidation in the oxidizing atmosphere.^-The type semiconductor region 13 is formed after light oxidation in the oxidizing atmosphere.
[0064]
As described above, in this embodiment, since the write oxide films 11a and 11b of the information transfer n-channel type MISFET are thickened, they are formed at the interfaces between the write oxide films 11a and 11b and the upper layer films 12 and 16. The negative charge amount can be reduced, and the information transfer n-channel MISFET has the same effect as in the first embodiment. Further, the driving capability of the MISFETs Qn and Qp in the peripheral circuit formation region is not impaired. That is, in order to improve the drive capability of the MISFETs Qn and Qp in the peripheral circuit formation region, n under the light oxide film 11b is used.^-Type semiconductor region 14 or p^-The type semiconductor region 15 needs to be formed shallower and with a higher concentration. On the other hand, when the light oxide film 11b is thickened, n^-Type semiconductor region 14 or p^-It is necessary to increase the energy of impurity implantation for forming the type semiconductor region 15. Therefore, in the case of the present embodiment, the light oxide film 11b is not formed in the peripheral circuit formation region.^-Type semiconductor region 14 or p^-Since the energy of impurity implantation for forming the type semiconductor region 15 can be kept low, n^-Type semiconductor region 14 or p^-The type semiconductor region 15 can be formed shallowly, and the drive capability of the MISFETs Qn and Qp in the peripheral circuit formation region is not impaired.
[0065]
Further, as shown in FIG. 14C, the refresh time of the DRAM shown in this embodiment is 150 ms.
[0066]
(Embodiment 3)
In the first embodiment, the memory cell selection MISFETQs in the memory cell array portion, the write oxide films 11a and 11b of the n-channel MISFETQn and p-channel MISFETQp in the peripheral circuit formation region are formed thick. Only the light oxide films 11a and 11b of the selection MISFET Qs and the p-channel type MISFET Qp may be formed thick. 18 and 19 are cross-sectional views showing the method of manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention in the order of steps. Since the steps from the formation of the light oxide film 11a described with reference to FIGS. 1 to 3 are the same as those in the first embodiment, the description thereof is omitted.
[0067]
A semiconductor substrate 1 shown in FIG. 3 is prepared. As shown in FIG. 18, a silicon nitride film 12a having a thickness of about 10 nm is deposited on the semiconductor substrate 1 by a CVD method to form an n-channel MISFET Qn in the peripheral circuit formation region. A sidewall film 12 is formed on the sidewalls of the gate electrode 9 of the memory cell selection MISFET Qs and the p-channel type MISFET Qp in the peripheral circuit formation region by covering the predetermined region with the resist film 3R and then anisotropically etching. . Next, after removing the resist film 3R, as shown in FIG. 19, light oxidation is performed in an oxidizing atmosphere, so that both sides of the gate electrode 9 of the memory cell selection MISFET Qs and the p-channel type MISFET Qp in the peripheral circuit formation region are formed. The surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) is oxidized to form a light oxide film 11b. Here, the sum of the thicknesses of the light oxide film 11b and the light oxide film 11a (including the thickness of the gate oxide film 8 if it remains) is about 8 nm. Note that the light oxide film 11b is not formed on the n-channel MISFET Qn in the peripheral circuit formation region because it is covered with the silicon nitride film 12a.
[0068]
Accordingly, the write oxide films 11a and 11b of the memory cell selection MISFET Qs and the p-channel type MISFET Qp in the peripheral circuit formation region are thicker than the write oxide film 11a of the n-channel type MISFET Qn in the peripheral circuit formation region.
[0069]
The subsequent steps are the same as those in the first embodiment described with reference to FIGS. N^-Type semiconductor region and p^-The type semiconductor regions 14 and 15 may be formed before the formation of the silicon nitride film 12a or before the light oxidation in the oxidizing atmosphere.^-The type semiconductor region 13 is formed after light oxidation in the oxidizing atmosphere.
[0070]
As described above, in this embodiment, since the write oxide films 11a and 11b of the information transfer n-channel type MISFET and the p-channel type MISFET Qn in the peripheral circuit formation region are thickened, the write oxide films 11a and 11b and the upper layer films thereof are formed. The amount of negative charge formed at the interface with the transistors 12 and 16 can be reduced, and the same effect as in the first embodiment can be obtained with respect to the information transfer n-channel MISFET and the p-channel MISFET Qn in the peripheral circuit formation region. Have. Further, the driving capability of the n-channel type MISFET Qn in the peripheral circuit formation region is not impaired. That is, in order to improve the driving capability of the MISFET in the peripheral circuit formation region, as described above, n under the light oxide film 11b is used.^-The type semiconductor region 14 needs to be formed shallower and with a higher concentration. In the present embodiment, the light oxide film 11b is not formed in the n-channel MISFET Qn in the peripheral circuit formation region.^-Since the energy of impurity implantation for forming the type semiconductor region 14 can be kept low, n^-The type semiconductor region 14 can be formed shallowly, and the driving capability of the n-channel type MISFET Qn in the peripheral circuit formation region is not impaired.
[0071]
Further, as shown in FIG. 14D, the refresh time of the DRAM shown in this embodiment is 150 ms.
[0072]
(Embodiment 4)
In the first embodiment, the light oxide film 11b is formed by performing light oxidation in an oxidizing atmosphere. However, after the light oxide film 11b is formed to have a thickness of about 6 nm, heat treatment is performed in an NO atmosphere to obtain the light oxide film. Nitrogen may be introduced into the interface between 11b and the semiconductor substrate 1 (p-type well 3 and n-type well 4). In addition, since it is the same as the case of Embodiment 1 except the heat treatment process in said NO atmosphere, the description is abbreviate | omitted.
[0073]
In the present embodiment, the nitrogen concentration at the interface is 4%.
[0074]
Thus, in the present embodiment, nitrogen is introduced into the interface between the light oxide film 11b and the semiconductor substrate 1 (p-type well 3 and n-type well 4), so that positive charges are generated at this interface. As a result, the amount of negative charge formed at the interface can be further reduced.
[0075]
As shown in FIG. 14E, the refresh time of the DRAM shown in this embodiment is 120 ms.
[0076]
(Embodiment 5)
Further, the heat treatment in the NO atmosphere described in the fourth embodiment may be applied to the manufacturing process described in the second and third embodiments. Also in this case, after forming the light oxide film 11b to about 6 nm, heat treatment is performed in an NO atmosphere to introduce nitrogen into the interface between the light oxide film 11b and the semiconductor substrate 1 (p-type well 3, n-type well 4). . Except for the heat treatment step in the NO atmosphere, the description is omitted because it is the same as in the case of the second and third embodiments.
[0077]
In the present embodiment, the nitrogen concentration at the interface is 4%.
[0078]
Thus, also in this embodiment, since nitrogen is introduced into the interface between the light oxide film 11b and the semiconductor substrate 1 (p-type well 3 and n-type well 4), a positive charge is generated at this interface. As a result, the amount of negative charge formed at the interface can be further reduced.
[0079]
As shown in FIGS. 14F and 14G, the refresh time of the DRAM shown in this embodiment is 110 ms. FIG. 14F shows the refresh time when the heat treatment in the NO atmosphere is performed in the second embodiment, and FIG. 14G shows the refresh time when the heat treatment in the NO atmosphere is performed in the third embodiment. .
[0080]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0081]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0082]
According to the present invention, the light oxide film of the information transfer n-channel type MISFET is made thicker than the light oxide film of the CMIS configuration n-channel type MISFET and p-channel type MISFET. The amount of negative charge formed can be reduced, and the refresh characteristics of the memory cell can be improved. In addition, the junction leakage current of the n-channel type MISFET constituting the memory cell can be reduced. Further, the subthreshold coefficient can be reduced, and an increase in the threshold potential Vth can be suppressed.
[0083]
Further, according to the present invention, since the light oxide film of the p-channel type MISFET is thicker than the light oxide film of the n-channel type MISFET, the amount of negative charge formed at the interface between the light oxide film and the upper layer film is reduced. Therefore, the occurrence of the kink phenomenon of the p-channel type MISFET can be reduced.
[0084]
In particular, in a gate electrode having a polycrystalline silicon film and a tungsten film, the light oxide film can be made thick while preventing oxidation of the tungsten film by forming a sidewall film on the side wall of the gate electrode.
[0085]
Further, according to the present invention, since the light oxide film is formed after the side wall film is formed on the side wall of the gate electrode, the light oxide film can be thickened while preventing the oxidation of the tungsten film in the gate electrode, When applied to an information transfer n-channel MISFET, the refresh characteristics of the memory cell can be improved and the junction leakage current of the n-channel MISFET constituting the memory cell can be reduced. Further, the subthreshold coefficient can be reduced, and an increase in the threshold potential Vth can be suppressed. Further, when applied to a p-channel type MISFET for CMIS configuration, it is possible to reduce the occurrence of the kink phenomenon of the p-channel type MISFET.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view of a substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention;
FIG. 2 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 3 is a cross-sectional view of the principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
4 is a cross-sectional view of the principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention; FIG.
FIG. 5 is a cross-sectional view of the principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
6 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention; FIG.
7 is a fragmentary cross-sectional view of the substrate, illustrating the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention; FIG.
FIG. 8 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 9 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is Embodiment 1 of the present invention.
FIG. 10 is a cross-sectional view of the principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
12 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention; FIG.
13 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention; FIG.
FIG. 14 is a diagram showing a refresh time of the semiconductor integrated circuit device of the present invention.
15 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to Embodiment 2 of the present invention; FIG.
FIG. 16 is a diagram showing a structure of a plug of a semiconductor integrated circuit device according to a second embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing a semiconductor integrated circuit device which is Embodiment 2 of the present invention;
FIG. 18 is a cross-sectional view of the principal part of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 3 of the present invention;
FIG. 19 is a fragmentary cross-sectional view of a substrate showing a method of manufacturing a semiconductor integrated circuit device which is Embodiment 4 of the present invention;
FIG. 20 is a diagram for illustrating the effect of the present invention.
FIG. 21 is a diagram illustrating a problem to be solved by the present invention.
FIG. 22 is a diagram for illustrating a problem of the present invention.
[Explanation of symbols]
1 Semiconductor substrate
2 Element isolation groove
3 p-type well
4 n-type well
5 Silicon oxide film
8 Gate oxide film
9 Gate electrode
9a Polycrystalline silicon film
9b W film
10 Silicon nitride film
11a Light oxide film
11b Light oxide film
12 Side wall film
13 n^-Type semiconductor region
14 n^-Type semiconductor region
15 p^-Type semiconductor region
16 Sidewall spacer
17 n⁺Type semiconductor region
18 p⁺Type semiconductor region
19 Silicon oxide film
20, 21 Contact hole
22 plug
23 Silicon oxide film
24, 25 Contact hole
26 plug
30-33 wiring
34 Silicon oxide film
38 through hole
40 Silicon nitride film
41 Silicon oxide film
42 groove
43 Lower electrode
44 capacitive insulation film
45 Upper electrode
50 Silicon oxide film
51 through hole
52 plug
53-55 wiring
BL bit line
WL Word line
C Information storage capacitor
Qn n-channel MISFET
Qp p-channel MISFET
Qs MISFET for memory cell selection
2R resist film
3R resist film
12a Silicon nitride film

Claims (8)

(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a gate electrode including the polycrystalline silicon film and the refractory metal film by sequentially forming and patterning a polycrystalline silicon film, a refractory metal film and a silicon nitride film on the gate insulating film; When,
(C) performing wet hydrogen oxidation to form a first light oxide film on the side surface of the polycrystalline silicon film and the surface of the semiconductor substrate;
( D ) forming a sidewall film using a silicon nitride film on the sidewall of the gate electrode;
( E) performing a heat treatment in an oxidizing atmosphere to form a second light oxide film on the surface of the semiconductor substrate not covered with the gate electrode and the sidewall film ;
(F) the method for manufacturing a semiconductor integrated circuit device characterized in that it comprises a step of forming a by implanting impurities into the semiconductor substrate lightly doped diffusion layer. 2. The semiconductor integrated circuit device according to claim 1, wherein in the step (c), a thickness of the first light oxide film formed on a side surface of the polycrystalline silicon film is 5 nm or less. Manufacturing method. In the step (e), after forming the second light oxide film, heat treatment is performed in an atmosphere of nitrogen monoxide to introduce nitrogen into the interface between the second light oxide film and the semiconductor substrate. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein: An n-channel type MISFET for information transfer formed in a memory cell formation region of a semiconductor substrate, a n-channel type MISFET and a p-channel type MISFET for CMIS configuration formed in a memory cell composed of a capacitive element and a peripheral circuit formation region, A method for manufacturing a semiconductor integrated circuit device, comprising:
  (A) forming a gate insulating film on the semiconductor substrate;
  (B) A polycrystalline silicon film, a refractory metal film and a silicon nitride film are sequentially formed on the gate insulating film and patterned to form the polycrystalline silicon film and the high-concentration film in the memory cell region and the peripheral circuit region. Forming a gate electrode including a melting point metal film;
  (C) side surfaces of the polycrystalline silicon film of the gate electrode formed in the memory cell region and the peripheral circuit region by performing wet hydrogen oxidation; and the surface of the semiconductor substrate in the memory cell region and the peripheral circuit region And forming a first light oxide film;
  (D) forming a silicon nitride film that covers the semiconductor substrate in the memory cell region and the peripheral circuit region;
  (E) performing anisotropic etching to remove the silicon nitride film formed on the semiconductor substrate in the memory cell region, thereby nitriding the side wall of the gate electrode formed in the memory cell region; Forming a sidewall film made of a silicon film and leaving the silicon nitride film formed on the semiconductor substrate in the peripheral circuit region;
  (F) performing a heat treatment in an oxidizing atmosphere to form a second light oxide film on the surface of the semiconductor substrate in the memory cell region;
  (G) forming a low-concentration diffusion layer by injecting impurities into the semiconductor substrate in the memory cell region, and a method for manufacturing a semiconductor integrated circuit device. An n-channel type MISFET for information transfer formed in a memory cell formation region of a semiconductor substrate, a n-channel type MISFET and a p-channel type MISFET for CMIS configuration formed in a memory cell composed of a capacitive element and a peripheral circuit formation region, A method for manufacturing a semiconductor integrated circuit device, comprising:
  (A) forming a gate insulating film on the semiconductor substrate;
  (B) A polycrystalline silicon film, a refractory metal film and a silicon nitride film are sequentially formed on the gate insulating film and patterned to form the polycrystalline silicon film and the high-concentration film in the memory cell region and the peripheral circuit region. Forming a gate electrode including a melting point metal film;
  (C) side surfaces of the polycrystalline silicon film of the gate electrode formed in the memory cell region and the peripheral circuit region by performing wet hydrogen oxidation; and the surface of the semiconductor substrate in the memory cell region and the peripheral circuit region And forming a first light oxide film;
  (D) forming a silicon nitride film that covers the semiconductor substrate in the memory cell region and the peripheral circuit region;
  (E) performing anisotropic etching on the semiconductor substrate in a region in which the p-channel MISFET is to be formed in the silicon nitride film and the peripheral circuit region formed on the semiconductor substrate in the memory cell region; By removing the formed silicon nitride film, a side wall film made of the silicon nitride film on the side wall of the gate electrode formed in the memory cell region and the side wall of the gate electrode of the p-channel type MISFET And leaving the silicon nitride film formed on the semiconductor substrate in the region for forming the CMIS constituting n-channel MISFET in the peripheral circuit region; and
  (F) Heat treatment is performed in an oxidizing atmosphere, and a second surface is formed on the surface of the semiconductor substrate in the memory cell region and the surface of the semiconductor substrate in the region in which the p-channel MISFET is formed in the peripheral circuit region. Forming a light oxide film of
  (G) forming a low-concentration diffusion layer by injecting impurities into the semiconductor substrate in the memory cell region, and a method for manufacturing a semiconductor integrated circuit device. 6. The method according to claim 4, further comprising a step of forming a low-concentration diffusion layer of the CMIS constituting n-channel MISFET and the p-channel MISFET before the step (d). A method of manufacturing a semiconductor integrated circuit device. Between the step (d) and the step (f), the method further includes a step of forming a low-concentration diffusion layer of the CMIS constituting n-channel MISFET and the p-channel MISFET. A method for manufacturing a semiconductor integrated circuit device according to claim 4 or 5. After the step (f),
  Forming a sidewall spacer film on a side wall of the gate electrode of each of the CMIS constituting n-channel MISFET and the p-channel MISFET;
  An n-type high-concentration diffusion layer is formed by implanting n-type impurities into the semiconductor substrate in the region where the CMIS configuration n-channel MISFET is to be formed using the gate electrode and the sidewall spacer film as a mask. And a process of
  A p-type high-concentration diffusion layer is formed by implanting p-type impurities into the semiconductor substrate in the region for forming the CMIS configuration p-channel MISFET using the gate electrode and the sidewall spacer film as a mask. And a process of
  The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein:

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