JP2000260962A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable DRAM by improving the refreshing characteristics of the DRAM. SOLUTION: In a semiconductor integrated circuit device, the impurity concentrations in data line-side n- and p-type semiconductor regions 7a and 10a are set relatively higher than those in capacitance element-side n-- and p--type semiconductor regions 7b and 10b. The device is operated by selecting the substrate voltage and data-line voltage, so that the reverse voltage (= data-line voltage + |substrate voltage|) impressed upon a data line-side joining area becomes 2.5 V or smaller. Therefore, the pose characteristic of the device can be improved, while the deterioration of the disturbance characteristic of the device is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a DRAM (Dynamic Random Access Memory).
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a memory in which a memory circuit and a logic circuit and a logic circuit are provided on the same semiconductor substrate.

[0002]

2. Description of the Related Art Along with the high integration of DRAM, the miniaturization of memory cells has progressed, and currently, a MISFET (Metal Insulator) for selecting a memory cell having a gate length of 0.3 μm or less.
Semiconductor Field Effect Transistor) is formed.

A method for obtaining good refresh characteristics in the memory cell selecting MISFET is described in, for example, "Super LSI Memory" published by Baifukan on November 5, 1994, by Kiyo Ito, pages 239 to P240. Another method is to apply a negative voltage to the substrate.

Further, the impurity concentration of the semiconductor substrate on which the data lines are formed (data line side) is set higher than the impurity concentration of the semiconductor substrate on which the information storage capacitor is formed (capacitor side). An asymmetric method has been proposed, which controls the threshold voltage of the memory cell selecting MISFET, and at the same time, suppresses an increase in the junction electric field strength near the end of the gate electrode on the side of the capacitive element, thereby causing a refresh failure. It is possible to reduce the rate.

[0005]

However, according to studies made by the present inventor, it has been found that the following problems occur.

That is, when the voltage (substrate voltage) applied to the substrate is changed from -1.5 V to -0.5 V to the negative side, the refresh time pause characteristic is improved, but the drain current increases. Therefore, it is difficult to satisfy both the pause characteristic and the disturbance characteristic only by controlling the substrate voltage. Here, the pause characteristic is a storage information retention characteristic in a state where a voltage of V _D / 2 is applied to the data line almost all the time when viewed from a specific bit, and the disturb characteristic is:
When viewed from a specific bit, this is a storage information retention characteristic when a pulse voltage between 0 and V _D / 2 or a pulse voltage between V _D / 2 and V _D is applied to the data line. Most of the time is about 9 of the refresh cycle time.
It means 4%. Incidentally, illustrating the data line potential and V _D.

In the asymmetric method, when the substrate voltage is increased to the negative side, the leakage current increases due to an increase in the electric field on the capacitive element side and the expansion of the depletion layer, so that the pause characteristic of the refresh time deteriorates. When the substrate voltage is increased to the negative side, the junction electric field on the data line side is increased, and the generated electrons flow to the capacitor element side, thereby deteriorating the disturb characteristic of the refresh time. Therefore, since the refresh time is easily affected by the substrate voltage, it is considered that the refresh time is easily changed by a voltage change due to noise or the like.

An object of the present invention is to provide a technology capable of realizing a highly reliable DRAM by improving refresh characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention has a MIS transistor in which one of a source and a drain is formed by a first semiconductor region and the other of the source and the drain is formed by a second semiconductor region on a semiconductor substrate. The impurity concentration of the first semiconductor region is relatively higher than the impurity concentration of the second semiconductor region, and the impurity concentration of the first semiconductor region provided around the first semiconductor region is opposite to that of the first semiconductor region. The impurity concentration of the third semiconductor region is relatively higher than the impurity concentration of the fourth semiconductor region made of an impurity of the opposite conductivity type to the impurity of the second semiconductor region provided around the second semiconductor region. (1) The voltage applied between the semiconductor region and the semiconductor substrate is set to 2.5 V or less.

(2) In the semiconductor integrated circuit device of the present invention, in the MIS transistor of (1), the voltage applied to the semiconductor substrate is a ground potential.

(3) In the semiconductor integrated circuit device according to the present invention, in the MIS transistor according to the above (1) or (2),
The above-mentioned MIS transistor is connected in series with the information storage capacitance element to form a memory cell selecting MI which constitutes a memory cell.
An S-range transistor in which a data line for transferring data is formed above the first semiconductor region and an information storage capacitor is formed above the second semiconductor region.

(4) In the semiconductor integrated circuit device of the present invention, in the MIS transistor of (1) or (2),
The first semiconductor region and the second semiconductor region are made of n-type impurities, and the third semiconductor region and the fourth semiconductor region are made of p-type impurities.

(5) In the semiconductor integrated circuit device of the present invention, in the MIS transistor of (4), the impurity forming the first semiconductor region is arsenic, the impurity forming the second semiconductor region is phosphorus, Third semiconductor region and fourth semiconductor region
The impurity forming the semiconductor region is boron.

(6) In the semiconductor integrated circuit device of the present invention, in the MIS transistor of (4), the first semiconductor region may be formed in a region having a depth of about 10 to 20 nm from the surface of the semiconductor substrate in a range of 0.2 to 2.2. The second semiconductor region is made of arsenic having an impurity concentration of 0 × 10 ¹⁹ cm ⁻³ , and the second semiconductor region is formed at a depth of about 20 to 40 nm from the surface of the semiconductor substrate by 0.5.
The third semiconductor region is formed at a depth of about 50 to 100 nm from the surface of the semiconductor region in a range of 0.5 to ^1.5 × 10 × 10 ¹⁷ cm ⁻³ .
The fourth semiconductor region is formed of boron having an impurity concentration of 10 ¹⁸ cm ^-3 , and the fourth semiconductor region is 50 to 1 cm from the surface of the semiconductor region.
0.5 to 5.0 × 10 ¹⁷ c in a region having a depth of about 00 nm.
It is made of boron having an impurity concentration of m ^-3 .

According to the above means, the threshold voltage of the memory cell selecting MISFET is controlled by setting the impurity concentration of the semiconductor substrate on the data line side higher than the impurity concentration of the semiconductor substrate on the capacitance element side. At the same time, it is possible to suppress an increase in the junction electric field intensity near the end of the gate electrode on the side of the capacitor, thereby reducing the rate of occurrence of refresh failure. In addition, by setting the reverse voltage applied to the junction region on the data line side to 2.5 V or less by selecting the substrate voltage and the data line voltage, the amount of electrons generated in the junction region on the data line side is reduced. Since the number of electrons decreases, the amount of electrons injected to the capacitor element side decreases, and deterioration of the disturb characteristics is suppressed. Further, since the degree of freedom in setting a voltage such as a data line voltage or a word line voltage is increased, it is possible to set an optimal voltage for obtaining a good pause characteristic, thereby improving the pause characteristic.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a DR according to an embodiment of the present invention.
FIG. 2 is a sectional view of a main part of a semiconductor substrate showing a memory cell selection MISFET of AM. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

As shown in FIG. 1, in a device isolation region on a main surface of a semiconductor substrate 1 made of silicon single crystal, a trench type device isolation insulating film 2 is formed. An n-type buried well 3 and a p-type well 4 are formed deep in a semiconductor substrate 1 of a memory array).

The memory cell selecting MISFET is composed of a gate insulating film 5 composed of a silicon oxide film, a gate electrode 6, and one n-type semiconductor region 7a constituting the source and drain and the other n ^- type semiconductor region 7b. The gate electrode 6 is formed integrally with a word line for selecting a memory cell.

The gate electrode 6 is composed of a polycrystalline silicon film into which an n-type impurity is introduced, and a tungsten silicide film provided on the polycrystalline silicon film for reducing a resistance value. A silicon nitride film 8 is formed on the gate electrode 6
Are formed, and a sidewall spacer 9 made of a silicon nitride film is formed on a side wall in the gate length direction.
Are formed.

Above one of the n-type semiconductor regions 7a constituting the source and the drain, a data line DL composed of a polycrystalline silicon film into which an n-type impurity is introduced is formed. The data line DL is connected to the n-type semiconductor region 7a via a plug formed of a polycrystalline silicon film into which impurities are introduced. An information storage capacitance element C is formed above the other n ⁻ -type semiconductor region 7b constituting the source and the drain. For example, a plug formed of a polycrystalline silicon film doped with an n-type impurity is formed. , The storage electrode forming the information storage capacitor C is connected to the n ⁻ type semiconductor region 7b.

A p-type semiconductor region 10a for adjusting a threshold voltage is formed in the p-type well 4 on the data line side, and the impurity concentration is formed in the p-type well 4 on the capacitive element side. The impurity concentration is set higher than that of the p ⁻ type semiconductor region 10b.

Further, the n-type semiconductor region 7a on the data line side
Is set higher than the impurity concentration of the n ⁻ -type semiconductor region 7b on the side of the capacitive element, and offset due to the provision of the high-concentration p-type semiconductor region 10a is prevented. In other words, the impurity concentration of the n-type semiconductor region 7a and the p-type semiconductor region 10a on the data line side is
^- it is relatively high respectively set than the impurity concentration of the semiconductor region 10b ^- -type semiconductor regions 7b and p.

The n-type semiconductor region 7a on the data line side is made of, for example, arsenic (As), and its impurity concentration is about 0.2 to 20 nm from the surface of the semiconductor substrate 1 to a depth of about 10 to 20 nm. The distribution is such that the maximum concentration of about 2.0 × 10 ¹⁹ cm ⁻³ is located. In addition, n on the capacitor element side
^{The −} type semiconductor region 7 b is made of, for example, phosphorus (P), and has an impurity concentration of about 0.5 to 5.0 × 1 at a depth of about 20 to 40 nm from the surface of the semiconductor substrate 1.
It is distributed so that the maximum concentration of about 0 ¹⁷ cm ^-3 is located.

The p-type semiconductor region 10a on the data line side
Is formed of, for example, boron (B), and its impurity concentration is about 50 to 100 from the surface of the semiconductor substrate 1.
The distribution is such that the maximum concentration of about 0.5 to 1.5 × 10 ¹⁸ cm ⁻³ is located at a depth of about nm. The p ⁻ type semiconductor region 10 b on the capacitive element side is made of, for example, B, and has an impurity concentration of about 0.5 to 5.5 nm at a depth of about 50 to 100 nm from the surface of the semiconductor substrate 1.
The distribution is such that the maximum concentration of about 0 × 10 ¹⁷ cm ⁻³ is located.

When the substrate voltage is applied and the data line voltage reciprocates between the ground potential (0 V) and V _D ,
Data line side n-type semiconductor region 7a and p-type semiconductor region 10
a-n ^- type semiconductor region 7 on the capacitive element side from the junction region with
Electrons are supplied to the junction region between b and p ⁻ type semiconductor region 10b.

FIG. 2 shows an example of the relationship between the amount of electrons supplied from the junction region on the data line side to the capacitor element for a certain period of time and the reverse voltage applied to the junction region on the data line side. The reverse voltage is the sum of the data line voltage and the absolute value of the substrate voltage, and V _D is applied to the junction region on the capacitor element side.

As shown in FIG. 2, the amount of supplied electrons increases as the reverse voltage increases, and in particular, rapidly increases when the voltage exceeds 2.0 V. For example, a memory cell in a “high” state in which a pause refresh time is set to 200 ms and a charge amount of 40 fC is held in a capacitor element is 2.5 V.
When a reverse voltage is applied, about 20 f
When the amount of C electrons is supplied, the amount of accumulated charge is halved, and the refresh time is reduced to about half, causing the memory cell to malfunction.

Therefore, the reverse voltage is set to 2.5 V or less so that the refresh time does not become less than half. In order to make the reverse voltage 2.5 V or less, for example, the substrate voltage is set to -1.0 V and the data line voltage is set to 1.4 V which is 1.5 V or less, or the substrate voltage is set to -0.5 V and the data line voltage is set to -0.5 V. The substrate voltage and the data line voltage can be arbitrarily selected, for example, by setting to 2V.

As described above, by setting the reverse voltage to 2.5 V or less, the leak current can be reduced and the pause refresh time can be extended, and the amount of electrons generated in the junction region on the data line side can be reduced. The amount of electrons injected into the capacitor element decreases sharply, and degradation of the disturb characteristics can be suppressed.

Further, when the substrate voltage is set to the ground potential, the disturb characteristic hardly deteriorates. Therefore, the data line voltage can be set to a voltage value effective for improving the pause characteristic. The problem of a decrease in signal amount due to a decrease in the number of pixels is eliminated, and the refresh characteristics are improved.

As described above, according to the present embodiment, p-type semiconductor region 10 surrounding n-type semiconductor region 7a on the data line side is formed.
By setting the impurity concentration of “a” higher than the impurity concentration of the p ⁻ -type semiconductor region 10b surrounding the n ⁻ -type semiconductor substrate 7b on the capacitive element side, the memory cell selecting MISFET Q
At the same time as controlling the threshold voltage of s, it is possible to suppress an increase in the junction electric field strength near the end of the gate electrode 6 on the side of the capacitor, thereby reducing the rate of occurrence of refresh failure.

In addition, the substrate voltage and the data line voltage are selected and operated so that the reverse voltage applied to the junction region on the data line side is 2.5 V or less, or the substrate voltage is set to the ground potential. In this case, the amount of electrons generated in the junction region on the data line side is reduced, so that the amount of electrons injected to the capacitor element side is reduced, and degradation of the disturb characteristic is suppressed. Further, since the degree of freedom in setting a voltage such as a data line voltage or a word line voltage is increased, it is possible to set an optimal voltage for obtaining a good pause characteristic, thereby improving the pause characteristic.

Next, a method of manufacturing the DRAM having the memory cell selecting MISFET of the present embodiment configured as described above will be described in the order of steps with reference to FIGS. Qs
Is a memory cell selecting MISF formed in a memory array.
ET, and Qn and Qp are an n-channel MISFET and a p-channel M
3 illustrates an ISFET.

First, as shown in FIG. 3, a trench type element isolation insulating film 2 made of a silicon oxide film is formed on a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm. Next, an n-type impurity, for example, P is ion-implanted into the semiconductor substrate 1 of the memory array to form an n-type buried well 3, and an n-channel MISFE of the memory array and peripheral circuits is formed.
A p-type impurity, for example, B is ion-implanted in a region for forming TQn to form a p-type well 4, and an n-type impurity is formed in a region for forming a p-channel MISFET Qp of a peripheral circuit.
For example, P ions are implanted to form the n-type well 11.

After the impurity ions are implanted into the semiconductor substrate 1, the semiconductor substrate 1 is subjected to 1000 ° C. to activate the impurity ions, recover crystal defects generated in the semiconductor substrate 1 or obtain an optimum impurity concentration distribution. For about 30 minutes.

Next, although not shown, the n-channel MISFET Qn and the p-channel MISFE
In order to adjust the threshold voltage of TQp, p-type impurities, for example, B ions are implanted into p-type well 4 and n-type well 11.

Next, as shown in FIG. 4, a clean gate insulating film 5 having a thickness of about 7 nm is formed on each surface of the p-type well 4 and the n-type well 11 by using a hydrogen combustion method.
A polycrystalline silicon film having a thickness of about 50 nm, a tungsten silicide film having a thickness of about 120 nm, and a silicon nitride film 8 having a thickness of about 200 nm are sequentially deposited on the semiconductor substrate 1, and then, using a photoresist pattern as a mask, Is processed to form a gate electrode 6 composed of a tungsten silicide film and a polycrystalline silicon film.

Thereafter, using the photoresist pattern 12 as a mask, a p-type impurity, for example, B ion is implanted into the p-type well 4 on the data line side of the gate electrode 6 of the memory cell selecting MISFET Qs to form the p-type semiconductor region 10a. Then, an n-type impurity, for example, As ion is implanted to form an n-type semiconductor region 7a inside the p-type semiconductor region 10a.

Next, as shown in FIG. 5, after the photoresist pattern 12 is removed, a p-type impurity, for example, a B ion is added to the p-type well 4 of the gate electrode 6 of the memory cell selecting MISFET Qs on the capacitor element side. Is implanted to form a p-type semiconductor region 10b, and then an n-type impurity, for example, P ions is implanted to form an n ⁻ -type semiconductor region 7b inside the p-type semiconductor region 10b.

Next, an n-type impurity, for example, P ion is implanted into the p-type well 4 on both sides of the gate electrode 6 of the n-channel type MISFET Qn to form an n ^- type semiconductor region 13a.
Further, the gate electrode 6 of the p-channel type MISFET Qp
A p-type impurity, for example, B ion is implanted into the n-type wells 5 on both sides of the p ^- type semiconductor region 14a. afterwards,
The semiconductor substrate 1 is subjected to a heat treatment at 950 ° C. for about 20 seconds.

Next, a CVD (Chemic) is formed on the semiconductor substrate 1.
After a silicon nitride film having a thickness of about 80 nm is deposited by an Al Vapor Deposition method, the silicon nitride film is anisotropically etched to form sidewall spacers 9 on the side walls of the silicon nitride film 8 and the gate electrode 6. I do.

Next, as shown in FIG. 6, an n-type impurity, for example, As ion is implanted into the p-type well 4 of the peripheral circuit to form an n ⁺ -type semiconductor region 13b of the n-channel MISFET Qn. To the n-type well 11
By implanting a type impurity, for example, B ion, the p ⁺ type semiconductor region 14b of the p-channel type MISFET Qp is formed. After that, the semiconductor substrate 1 is subjected to a heat treatment at 800 ° C. for about 60 seconds.

As a result, the n-channel MI
An SFET Qn and a p-channel MISFET Qp are formed.

Next, after depositing a silicon oxide film on the semiconductor substrate 1, the surface of the silicon oxide film is polished by chemical mechanical polishing (CMP) to flatten the surface. Then, an interlayer insulating film 15 composed of a silicon oxide film is formed. The silicon oxide film is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, the insulating film of the same layer as the interlayer insulating film 15 and the gate insulating film 5 is sequentially removed by dry etching using a photoresist pattern as a mask, thereby forming one n-type semiconductor region of the memory cell selecting MISFET Qs. A contact hole 16 is formed to reach 7a, and a contact hole 17 is formed to reach the other n ⁻ type semiconductor region 7b.

This etching is performed under the condition that the silicon nitride film forming the side wall spacer 9 is anisotropically etched so that the silicon nitride film remains on the side wall of the gate electrode 6 of the memory cell selecting MISFET Qs. . As a result, contact holes 16 and 17 having a fine diameter equal to or smaller than the resolution limit of photolithography are formed by self-alignment with the gate electrode 6 of the MISFET Qs for selecting a memory cell.

Next, plugs 18a and 18b are formed inside the contact holes 16 and 17, respectively. The plugs 18a and 18b are formed by depositing a polycrystalline silicon film in which an n-type impurity, for example, P is introduced at a ^{concentration of} about 1 × 10 ²⁰ cm ⁻³ , over the interlayer insulating film 15 by a CVD method. Polished by CMP method, contact holes 16,
17 is formed by leaving a polycrystalline silicon film inside.

Next, as shown in FIG.
A silicon oxide film 19 is deposited on the upper layer. The silicon oxide film 19 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas.

Next, the silicon oxide film 19 on the contact hole 16 is removed by dry etching using a photoresist pattern as a mask to remove the contact hole 20a.
Is formed to expose the surface of the plug 18a. at the same time,
The silicon oxide film 19 of the peripheral circuit, the interlayer insulating film 15, and the insulating film of the same layer as the gate insulating film 5 are sequentially removed by dry etching using a photoresist pattern as a mask, thereby forming the n ⁺ -type semiconductor region of the n-channel MISFET Qn. A contact hole 20b reaching 13b and a contact hole 20c reaching the p ⁺ type semiconductor region 14b of the p-channel type MISFET Qp are formed.

Next, the data line DL of the memory array in contact with the plug 18a through the contact hole 20a and the n-channel MISFE through the contact hole 20b.
First layer wiring 2 in contact with n ⁺ type semiconductor region 13b of TQn
1 and a p-channel type M through the contact hole 20c.
The first contacting the p ⁺ type semiconductor region 14b of the ISFET Qp
The layer wiring 21 is formed. The data line DL and the first layer wiring 21 are formed by depositing a conductive film on the silicon oxide film 19 and then processing the conductive film using a photoresist pattern as a mask.

Next, as shown in FIG.
After depositing a silicon oxide film on the L and the first layer wiring 21, the surface of the silicon oxide film is polished by a CMP method to flatten the surface, and an interlayer insulating film 22 is formed. Next, the interlayer insulating film 22 and the silicon oxide film 19 on the plug 18b are sequentially removed by dry etching using a photoresist pattern as a mask, and a through hole 23 reaching the plug 18b is formed.

After that, as shown in FIG.
After depositing a polycrystalline silicon film in which an n-type impurity, for example, P is introduced at about 1 × 10 ²⁰ cm ^{−3, the} polycrystalline silicon film is processed by dry etching using a photoresist pattern as a mask. The storage electrode 24 of the storage capacitor C is formed. Next, after the surface of the storage electrode 24 is nitrided or oxynitrided, a tantalum oxide film is deposited, and then this heat-treated tantalum oxide film is crystallized to crystallize the tantalum oxide film to form a capacitance insulating film 25. Thereafter, after depositing a titanium nitride film, the titanium nitride film is patterned, and a plate electrode 26 is formed, whereby a DRAM is formed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the DRAM
MISFET for selecting a memory cell of a memory cell constituting a memory cell
Has been described, but the present invention is not limited to this, and is applicable to any n-channel or p-channel MISFET.

[0057]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the degradation of the disturb characteristic is suppressed and the pause characteristic is improved, so that a DRAM having high reliability can be realized by improving the refresh characteristic. Further, power consumption in the refresh operation can be reduced by the low-voltage operation.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a memory cell selecting MISFET of a DRAM according to an embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the amount of charge supplied from the junction region on the data line side to the junction region on the capacitive element side and the reverse voltage.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 trench-type element isolation insulating film 3 n-type buried well 4 p-type well 5 gate insulating film 6 gate electrode 7 a n-type semiconductor region 7 b n ^- type semiconductor region 8 silicon nitride film 9 sidewall spacer 10 a p-type semiconductor Region 10bp p ^- type semiconductor region 11 n-type well 12 photoresist pattern 13a n ^- type semiconductor region 13bn ⁺ type semiconductor region 14a p ^- type semiconductor region 14bp ⁺ type semiconductor region 15 interlayer insulating film 16 contact hole 17 contact hole 18a Plug 18b Plug 19 Silicon oxide film 20a Contact hole 20b Contact hole 21 First layer wiring 22 Interlayer insulating film 23 Through hole 24 Storage electrode 25 Capacitive insulating film 26 Plate electrode DL Data line C Information storage capacitor Qs Memory cell selection MIS ET Qn n-channel type MISFET Qp p-channel type MISFET

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hidetoshi Iwai 6-16, Shinmachi, Shinmachi, Ome-shi, Tokyo 3 Within the Device Development Center, Hitachi, Ltd. (72) Inventor Yutaka Ito 6--16, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Hideaki Kato 5-2-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Co., Ltd. Hitachi Intranet LLC Systems Co., Ltd. (72) Inventor Kazuhiko Sato 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-LSI Systems Co., Ltd. (72) Inventor Makoto Ogasawara 6-16-16, Shinmachi, Ome-shi, Tokyo Hitachi, Ltd. F term in development center (reference) 5F083 AD01 AD21 AD48 GA11 GA30 HA01 HA03 JA35 JA39 JA53 MA06 MA17 MA20 NA01 PR21 PR33 P R36 PR43 PR44 PR53 PR54

Claims (6)

[Claims] 1. A semiconductor integrated circuit device having an MIS transistor on a semiconductor substrate, wherein one of a source and a drain is constituted by a first semiconductor region, and the other of the source and the drain is constituted by a second semiconductor region. The impurity concentration of the first semiconductor region is relatively higher than the impurity concentration of the second semiconductor region, and is made of an impurity of a conductivity type opposite to that of the first semiconductor region provided around the first semiconductor region. An impurity concentration of the third semiconductor region is relatively higher than an impurity concentration of the fourth semiconductor region which is formed around the second semiconductor region and has an opposite conductivity type to that of the second semiconductor region; A semiconductor integrated circuit device, wherein a voltage applied between the first semiconductor region and the semiconductor substrate is 2.5 V or less. 2. The semiconductor integrated circuit device according to claim 1, wherein the voltage applied to said semiconductor substrate is a ground potential. 3. The semiconductor integrated circuit device according to claim 1, wherein said MIS transistor is a MIS transistor for selecting a memory cell, which is connected in series with a capacitance element for storing information and constitutes a memory cell. A data line for transferring data is formed above one semiconductor region,
A semiconductor integrated circuit device, wherein an information storage capacitive element is formed above the second semiconductor region. 4. The semiconductor integrated circuit device according to claim 1, wherein said first semiconductor region and said second semiconductor region are made of n-type impurities, and said third semiconductor region and said fourth semiconductor region are made of p-type. A semiconductor integrated circuit device characterized by being constituted by type impurities. 5. The semiconductor integrated circuit device according to claim 4, wherein the impurity forming the first semiconductor region is arsenic, the impurity forming the second semiconductor region is phosphorus, and the third semiconductor region and A semiconductor integrated circuit device, wherein the impurity forming the fourth semiconductor region is boron. 6. The semiconductor integrated circuit device according to claim 4, wherein said first semiconductor region is formed at a depth of about 10 to 20 nm from a surface of said semiconductor substrate in a range of 0.2 to 2.0 × 1.
The second semiconductor region is formed of arsenic having an impurity concentration of 0 ¹⁹ cm ^-3 , and the second semiconductor region is 2 cm from the surface of the semiconductor substrate.
0.5 to 5.0 × 10 in a region having a depth of about 0 to 40 nm.
Constituted by phosphorus having an impurity concentration of ¹⁷ cm ^-3 ,
The third semiconductor region is 50 to 50 mm from the surface of the semiconductor region.
0.5 to 1.5 × 10 ¹⁸ in a region having a depth of about 100 nm.
constituted by boron having an impurity concentration of cm ^-3 ,
The fourth semiconductor region is 50 to 50 mm from the surface of the semiconductor region.
0.5 to 5.0 × 10 ¹⁷ in a region having a depth of about 100 nm.
A semiconductor integrated circuit device comprising boron having an impurity concentration of cm ^-3 .