JP2001267531A - Semiconductor ic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve refresh characteristic and a writing characteristic of a memory cell provided with MISFETs for selecting a memory cell, each of which has a P+ gate electrode. SOLUTION: The impurity concentration in a part of a p-type well 4 in contact with n-type semiconductor regions 9 on the capacitor side, which constitute the source and drain of MISFETQs for selecting a memory cell is set relatively low, to lower an electric field in junctions, N-type semiconductor regions 8 on the bit line side, which constitute the source and drain of the MISFETQs for selecting a memory cell are surrounded by p-type semiconductor regions 10, having a relatively high-impurity concentration to prevent punch- through effect. Vth is adjusted, by introducing nitrogen into an interface between a gate insulation film 6a of the MISFETQs for selecting a memory cell and the p-type well 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a DRAM (Dynamic Random Access Memory).
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having

[0002]

2. Description of the Related Art A memory cell of a DRAM is a MISFET (Metal Insulator Semiconducer) for selecting one memory cell.
tor Field Effect Transistor) and a capacitor connected in series with it. A capacitor is used as an element for storing information. And the stored contents are lost.

For this reason, in the DRAM, a so-called refresh operation for periodically reproducing the stored contents is necessary in order to keep storing the information of the memory cells.
Various structural and circuit studies and technological developments have been made to improve the refresh characteristics as well as the operating speed of the entire AM.

In a DRAM, a memory cell selection M
There is a problem of increasing the Vth (threshold voltage) of the ISFET.
Japanese Patent Application Laid-Open Nos. 2-214155 and 4-5 disclose the use of a p-type polycrystalline silicon film for the gate electrode.
No. 8556 or JP-A-9-36318.

[0005]

As one means for improving the refresh characteristics, the impurity concentration (substrate concentration) of a semiconductor substrate in contact with a pair of source and drain semiconductor regions of a memory cell selecting MISFET is considered. There has been proposed a method of reducing the junction electric field strength by lowering the electric field.

However, a polycrystalline silicon film having a p-type conductivity is used.
Gate electrode (p ⁺With gate electrode)
N channel type MISFET for selecting memory cells
Can reduce punch through by lowering the substrate concentration.
-The problem that the phenomenon easily occurs occurs.

Therefore, the present inventor has proposed that in an n-channel type memory cell selecting MISFET having ap ⁺ gate electrode, only the impurity concentration of the semiconductor substrate in contact with the semiconductor region on the bit line side is increased and the junction on the capacitor side is increased. The electric field strength is kept low, and Vth
We studied to secure.

However, the above-described method has a problem that Vth is increased by about 0.3 V from 1.1 to 1.3 V, which is the target value, to 1.1 to 1.3 V. As a result, when writing high information, the drain current is reduced by an amount corresponding to the higher Vth, resulting in insufficient writing, causing a failure in a margin test of the writing characteristics and making it impossible to cope with high-speed operation.

An object of the present invention is to provide a technique capable of improving the refresh characteristics of a DRAM memory cell provided with a memory cell selecting MISFET having ap ⁺ gate electrode and at the same time improving the write characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) A semiconductor integrated circuit device of the present invention has a MISFET whose threshold voltage is adjusted by introducing nitrogen into an interface between a gate insulating film and a substrate. (2) The semiconductor integrated circuit device of the present invention has a MISFET whose threshold voltage is adjusted by introducing nitrogen into the interface between the gate insulating film and the substrate.
T is a memory cell selecting MISFET which is connected in series with the capacitor to constitute a memory cell. (3) The semiconductor integrated circuit device of the present invention has a MISFET whose threshold voltage is adjusted by introducing nitrogen into the interface between the gate insulating film and the substrate.
T is an n-channel type memory cell selection MISFET having ap ⁺ gate electrode which is connected in series with a capacitor to constitute a memory cell. (4) The semiconductor integrated circuit device of the present invention has a MISFET whose threshold voltage is adjusted by introducing nitrogen into the interface between the gate insulating film and the substrate.
T is an n-channel type memory cell selecting MISFET having ap ⁺ gate electrode which is connected in series with a capacitor to constitute a memory cell, and is a memory cell selecting MISFET.
The junction electric field of the n-type semiconductor region on the capacitor side, which constitutes one of the source and the drain of the ET, is reduced by the memory cell selection MIS.
It is lower than the junction electric field of the n-type semiconductor region on the bit line side that constitutes the other of the source and the drain of the FET. (5) The semiconductor integrated circuit device of the present invention has the MISFET whose threshold voltage is adjusted by introducing nitrogen into the interface between the gate insulating film and the substrate.
T is an n-channel type memory cell selecting MISFET having ap ⁺ gate electrode which is connected in series with a capacitor to constitute a memory cell, and is a memory cell selecting MISFET.
The region in contact with the capacitor-side n-type semiconductor region that constitutes one of the source and the drain of the ET has a relatively low impurity concentration, and the bit line-side n-type semiconductor that constitutes the other of the source and the drain of the memory cell selecting MISFET. The region in contact with the region has a relatively high impurity concentration. (6) In the semiconductor integrated circuit device of the present invention, the first MISFET in which a relatively large amount of nitrogen is introduced into the interface between the first gate insulating film and the substrate, and the second gate insulating film and the substrate Second MISF with relatively small amount of nitrogen introduced at the interface
ET, and the first MISFET is a memory cell selecting MISFET that is connected in series with a capacitor to constitute a memory cell, and the second MISFET is
Is a MISFET in the peripheral circuit section. (7) The semiconductor integrated circuit device according to the present invention is characterized in that the first MISFET in which a relatively large amount of nitrogen is introduced at the interface between the first gate insulating film and the substrate and the second gate insulating film and the substrate Second MISF with relatively small amount of nitrogen introduced at the interface
ET, and the first MISFET is a memory cell selecting MISFET that is connected in series with a capacitor to constitute a memory cell, and the second MISFET is
Denotes a MISFET in the peripheral circuit portion, in which the thickness of the first gate insulating film is larger than the thickness of the second gate insulating film. . (8) The semiconductor integrated circuit device of the present invention has a MISFET whose threshold voltage is adjusted by introducing nitrogen into the interface between the gate insulating film and the substrate.
T is a negative word type memory cell selecting MISFE which is connected in series with a capacitor to form a memory cell.
T.

According to the above-described means, in the n-channel type memory cell selecting MISFET having the p ⁺ gate electrode, the region (substrate or well region) where the n-type semiconductor region on the capacitor side constituting one of the source and the drain is in contact ), The junction electric field strength is reduced, and the impurity concentration of the region (substrate or well region) where the n-type semiconductor region on the bit line side, which constitutes the other of the source and the drain, is in contact is relatively reduced. In this case, the punch-through phenomenon can be prevented. Further, by introducing nitrogen having a positive fixed charge into the interface between the gate insulating film of the MISFET for memory cell selection and the substrate, Vth is lowered by about 0.05 V per about 1% of the amount of interface nitrogen, and the bit line side is reduced. Increase in Vth caused by relatively increasing the impurity concentration of the region in contact with the n-type semiconductor region can prevent insufficient writing due to a decrease in drain current caused by an increase in Vth.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a DR according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing AM. In the figure, Qs
Is a MISFET for selecting a memory cell formed in a memory array (a region where a memory cell is formed), and Qn and Qp are n-channel transistors formed in a peripheral circuit portion, respectively.
ISFET and p-channel MISFET
Reference symbol o denotes an n-channel MISFET formed in the input / output unit.

In all the drawings for describing the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

As shown in FIG. 1, a trench type element isolation insulating film 2 is formed in an element isolation region on a main surface of a semiconductor substrate 1 made of silicon single crystal, and further, a memory array and a peripheral circuit portion are formed. An n-type buried well 3 deep in the semiconductor substrate 1 in the A region (the region where the p-channel MISFET Qp is formed), the B region (the region where the n-channel MISFET Qn is formed) of the memory array and the peripheral circuit portion, and impurities in the input / output portion A p-type well 4 having a relatively low concentration is formed, and an n-type well 5 is formed in a region A of the peripheral circuit portion.

MISF for selecting a memory cell in a memory array
ETQs, a gate insulating film 6a composed of relatively thick silicon oxide film, the gate electrode 7a and the source, a low concentration of one of the n-type semiconductor region 8 and the other constituting the drain n ^- with type semiconductor region 9 by And one n-type semiconductor region 8 to which the bit line BL is connected.
A p-type semiconductor region 1 having a relatively high impurity concentration
0 is formed. The gate electrode 7a is composed of a silicon film into which a p-type impurity is introduced and a tungsten film in order from the lower layer, and is integrally formed with a word line WL for selecting a memory cell.

N-channel MISFET Q in peripheral circuit section
n is a gate insulating film 6b composed of a relatively thin silicon oxide film, a gate electrode 7b composed of a silicon film doped with n-type impurities and a tungsten film in order from the bottom, and a source and a drain. It comprises a pair of low-concentration n ^{− -type} semiconductor regions 9 and a pair of high-concentration n ^{+ -type} semiconductor regions 11. Similarly, the p-channel type MISFET Qp
Is a gate insulating film 6b composed of a relatively thin silicon oxide film, a gate electrode 7a composed of a silicon film doped with p-type impurities and a tungsten film in order from the bottom, and a pair constituting a source and a drain. It is constituted by a type semiconductor region 12 and a pair of high-concentration p ⁺ -type semiconductor region 13 ^- low-concentration p of.

N-channel MISFET Qo of input / output unit
Is a gate insulating film 6a composed of a relatively thick silicon oxide film, a gate electrode 7b composed of a silicon film doped with n-type impurities and a tungsten film in order from the lower layer, and a pair constituting a source and a drain. Low-concentration n ^{− -type} semiconductor region 9 and a pair of high-concentration n ⁺
It is constituted by the semiconductor region 11.

About 6% of nitrogen is introduced into the interface between the relatively thick gate insulating film 6a and the p-type well 4 of the memory array and the interface with the p-type well 4 in the input / output section. Interface between relatively thin gate insulating film 6b and p-type well 4 in the peripheral circuit portion and n-type well 5 in the peripheral circuit portion
About 4% of nitrogen has been introduced into the interface with.

Gate insulating films 6a and 6b and semiconductor substrate 1
Since nitrogen introduced at the interface with (p-type well 4 and n-type well 5) has a positive fixed charge, the amount of nitrogen at the interface is 1
It is possible to form a fixed charge of about 0.05 with a Vth difference per%. Therefore, for example, in the case of the memory cell selecting MISFET Qs in which Vth higher than the target Vth by about 0.3 V is obtained, nitrogen is present at the interface between the gate insulating film 6a and the semiconductor substrate 1 (p-type well 4). About 6% is introduced.

A silicon nitride film 14 is formed on an upper layer of a tungsten film provided to reduce the resistance value constituting the upper portions of the gate electrodes 7a and 7b. Further, on the side walls of the gate electrodes 7a and 7b in the gate length direction,
A sidewall spacer 15 made of a silicon nitride film is formed.

An interlayer insulating film 16 made of a silicon oxide film is formed on the silicon nitride film 14 and the sidewall spacers 15. Memory cell selecting MISFETQs source, while the n-type semiconductor region 8 and the source of which constitutes the drain, the other constituting a drain n ^- form semiconductor region 9 of the upper interlayer insulating film 16 and the gate insulating film 6a and the same layer Contact holes 17a and 17b are formed in the insulating film. Plugs 18a and 17a formed of a polycrystalline silicon film into which n-type impurities are introduced are formed in the contact holes 17a and 17b.
18b are respectively embedded.

A silicon oxide film 19 is formed on the interlayer insulating film 16. Further, a bit line BL formed of a polycrystalline silicon film into which an n-type impurity is introduced is formed on the upper layer of the silicon oxide film 19.

The bit line BL is connected to the silicon oxide film 19
Plug 1 through contact hole 20a formed in
8a, and further connected to one n-type semiconductor region 8 forming the source and drain of the memory cell selecting MISFET Qs via a plug 18a.

Further, a polycrystalline silicon layer in the same layer as the bit line BL is formed.
The first layer wiring M1 of the peripheral circuit portion is formed by the recon film.
Have been. The first layer wiring M1 includes a silicon oxide film 19,
Insulation of the same layer as the interlayer insulating film 16 and the gate insulating film 6b
Through the contact holes 20b and 20c formed in the film
And n of the n-channel type MISFET Qn in the peripheral circuit section. ⁺
Semiconductor region 11 and p-channel MISFET Qp
P⁺Connected to the semiconductor region 13. Sa
Further, the first layer wiring M1 is formed by the silicon oxide film 19, the interlayer insulation.
Formed on the same insulating film as the edge film 16 and the gate insulating film 6a
Through the contact hole 20d formed,
n of n-channel type MISFETQo⁺Semiconductor region 11
It is connected to the.

An interlayer insulating film 21 is formed above the bit line BL and the first layer wiring M1. Further, a storage electrode 22 of the capacitor is formed on the interlayer insulating film 21. The storage electrode 22 is made of, for example, a polycrystalline silicon film into which an n-type impurity is introduced.

The storage electrode 22 is connected to the plug 18 b through a through hole 23 formed in the interlayer insulating film 21 and the silicon oxide film 19,
It is connected to the other n ⁻ -type semiconductor region 9 constituting the source and the drain of the memory cell selection MISFET Qs via b.

The surface of the storage electrode 22 is covered with a capacitance insulating film 24, and the surface thereof is further covered with a plate electrode 25. The capacitance insulating film 24 is made of, for example, a tantalum oxide film or the like. The plate electrode 25 is made of, for example, a titanium nitride film and is formed so as to cover the plurality of storage electrodes 22.

An interlayer insulating film 26 is further formed on an upper layer of the capacitor including the storage electrode 22, the capacitor insulating film 24, and the plate electrode 25. A second layer wiring M2 is formed on the interlayer insulating film 26, and the second layer wiring M2 is connected to the first layer wiring M1 through contact holes 27 formed in the interlayer insulating films 21 and 26. . Further, a multilayer wiring is formed on the second layer wiring M2 and a passivation film is formed on the uppermost layer, but these are not shown.

Next, a method of manufacturing the DRAM having the above-described structure according to the present embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, a trench type element isolation insulating film 2 made of a silicon oxide film is formed on a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm. Next, an n-type impurity, for example, phosphorus (P) is ion-implanted into the semiconductor substrate 1 in the memory array and the region A (region where the p-channel MISFET Qp is formed) of the peripheral circuit portion, and n
A buried well 3 is formed, and a p-type impurity, for example, boron (B) is ion-implanted into the semiconductor substrate 1 of the memory array, the B region of the peripheral circuit portion (the region forming the n-channel MISFET Qn), and the input / output portion. Then, a p-type well 4 having a relatively low impurity concentration is formed, and an n-type impurity, for example, P is ion-implanted into an A region (a region where the channel MISFET Qp is formed) in the peripheral circuit portion to form an n-type well 5. .

Here, the n-type buried well 3 is, for example,
1 × 10 P ions at 1 MeV acceleration energy¹³cm
^-2It is formed by implanting a degree. p-type well 4
For example, B ions are accelerated with 300 keV acceleration energy.
1 × 10¹³cm^-2Degree, acceleration energy of 150 keV
2 × 10¹²cm^-2Degree, then accelerated energy of 40 keV
5 × 10 with lugi¹¹cm^-2Shape by injecting degree
N to be formed in a later step^-Semiconductor region 9
The B concentration in the contact area is set relatively low. n-type c
The L5 is, for example, a P ion accelerated energy of 500 keV.
2 × 10 in ghee ¹³cm^-2About 250 keV
5 × 10 with fast energy¹²cm^-2By injecting the degree
Is formed.

After the impurity ions are implanted into the semiconductor substrate 1, the semiconductor substrate 1 is heated to 1000 ° C. in order to activate the impurity ions, recover crystal defects generated in the semiconductor substrate 1 or obtain an optimum impurity concentration distribution. For about 30 minutes. Thereafter, although not shown, the MISFET
Impurity for adjusting the threshold voltage of p-type well 4
Then, ion implantation is performed on the n-type well 5.

Next, as shown in FIG. 3, a gate insulating film 28 having a thickness of about 6 nm is formed on each surface of the p-type well 4 and the n-type well 5, and then, at about 900.degree. The semiconductor substrate 1 is subjected to a heat treatment for about 30 minutes, and nitrogen of about 3% in area density is introduced into the interface between the gate insulating film 28 and the p-type well 4 and the interface between the gate insulating film 28 and the n-type well 5. .

Next, as shown in FIG. 4, the memory cell and the input / output portion are covered with a resist film 29, and the gate insulating film 28 in the peripheral circuit portion is removed using the resist film 29 as a mask.

After removing the resist film 29 and then subjecting the semiconductor substrate 1 to a cleaning treatment, as shown in FIG.
Thermal oxidation treatment is performed on each surface of the n-type well 4 and the n-type well 5 to form a gate insulating film 6a having a thickness of about 8 nm on each surface of the p-type well 4 of the memory array and the input / output unit;
A gate insulating film 6b having a thickness of about 4 nm is formed on each surface of the p-type well 4 and the n-type well 5 in the peripheral circuit portion.

Thereafter, a heat treatment is performed on the semiconductor substrate 1 at about 900 ° C. for about 30 minutes in a NO atmosphere. Thereby, about 3% of nitrogen is introduced into the interface between the gate insulating film 6a of the memory array and the input / output part and the p-type well 4, and
In combination with about 3% of nitrogen introduced in the process described with reference to FIG. 3, about 6% of nitrogen accumulates at the interface. Further, about 4% of nitrogen is introduced into the interface between the gate insulating film 6b and the p-type well 4 and the interface between the gate insulating film 6b and the n-type well 5 in the peripheral circuit portion.
About nitrogen accumulates.

Since the movement of nitrogen in the silicon oxide film is diffusion-controlled, the amount of nitrogen introduced into the relatively thin silicon oxide film in one nitrogen introduction step is
The amount is larger than the amount of nitrogen introduced into a relatively thick silicon oxide film. Therefore, compared with the amount of nitrogen (3%) introduced at the interface between the gate insulating film 6a of the memory array and the input / output part and the p-type well 4, the gate insulating film 6b of the peripheral circuit part and the p-type well 4 And the amount of nitrogen (4%) introduced at the interface between the gate insulating film 6b and the n-type well 5 increases.

In the n-channel MISFET Qn and the p-channel MISFET Qp in the peripheral circuit portion having the relatively thin gate insulating film 6b, if the amount of interface nitrogen increases, Ids (drain current) decreases and the current driving capability decreases. Therefore, the amount of interfacial nitrogen cannot be extremely increased. On the other hand, in the memory cell selecting MISFET Qs of the memory array having the relatively thick gate insulating film 6a and the n-channel MISFET Qo of the input / output unit, the reduction of the current driving capability due to the introduction of nitrogen does not pose a problem.
Nitrogen necessary for adjusting Vth can be introduced.

Next, as shown in FIG. 6, after a non-doped silicon film (not shown) having a thickness of about 70 nm is deposited on the semiconductor substrate 1, the A of the memory array and the peripheral circuit portion is deposited.
B ions are applied to the silicon film in the region (p-channel type MISFET Qp) at an acceleration energy of 3 keV to 3 × 10 ¹⁵ cm.
^By implanting about ^-2 , ap ^{+ type} silicon film 30a is formed. Next, the B region (n-channel MISFET) of the peripheral circuit portion
P ions are implanted into the silicon film of Qn) at an acceleration energy of 10 keV at a rate of about 2 × 10 ¹⁵ cm ⁻² to form an n ^{+ type} silicon film 30b. The area A (p
P ions may be implanted into the silicon film of the channel type MISFET Qp). Thereafter, the semiconductor substrate 1 is subjected to a heat treatment at about 950 ° C. for about 10 seconds.

Next, as shown in FIG. 7, a tungsten film 31 having a thickness of about 100 nm and a silicon nitride film 14 having a thickness of about 200 nm are sequentially deposited. Then, FIG.
As shown in FIG. 5, by processing these films using a photoresist pattern as a mask, the tungsten film 3 is formed.
1 and a silicon film 30a are formed, and at the same time, a gate electrode 7b formed of a tungsten film 31 and a silicon film 30b is formed. Thereafter, by performing a light oxidation process, although not shown, the gate electrode 7 is formed.
An oxide film having a thickness of about 5 nm is formed on the side surfaces of the tungsten films constituting the layers a and 7b.

Thereafter, as shown in FIG. 9, using the photoresist pattern as a mask, the memory cell selecting MISF is used.
B ions are tilted to the p-type well 4 on the data line side of the ETQs by, for example, about 15 ° and 6 ×
^Implant about 10 ¹² cm ^{-2 and} p with relatively high impurity concentration
The semiconductor region 10 is formed, and then arsenic (As) ions are implanted at an acceleration energy of, for example, 20 keV to 1 × 10 ^13.
By implanting about cm ⁻² , an n-type semiconductor region 8 is formed inside the p-type semiconductor region 10.

Next, as shown in FIG.
N-type impurities in p-type well 4 using
An object, for example, P ions is accelerated by 20 keV acceleration energy
× 10 ¹³cm^-2Memory cell by implanting about
P-type well on the capacitor side of selection MISFET Qs
4. Gate of n-channel MISFET Qn in the peripheral circuit section
P-type well 4 on both sides of gate electrode 7b and n-type
P on both sides of the gate electrode 7a of the channel type MISFET Qo
In shape well 4, n^-The semiconductor region 9 is formed.

Further, a p-type impurity, for example, B ion is implanted into the n-type well 5 using the photoresist pattern as a mask, thereby forming a p-channel type MI in the peripheral circuit portion.
N-type well 5 on both sides of gate electrode 7a of SFET Qp
A, p ^- forms a type semiconductor region 12.

Next, a CVD (Chemic) is formed on the semiconductor substrate 1.
After a silicon nitride film (not shown) having a thickness of about 50 nm is deposited by an Al Vapor Deposition method, the silicon nitride film is anisotropically etched to form a silicon nitride film 14 and sidewalls of the gate electrodes 7a and 7b. Next, a sidewall spacer 15 is formed.

Next, an n-type impurity, for example, As ion is implanted into the p-type well 4 in the peripheral circuit section and the input / output section, thereby forming the n-channel MISFET Qn in the peripheral circuit section.
And n ⁺ of n-channel type MISFET Qo of input / output unit
The semiconductor region 11 is formed, and the n-type well 5 of the peripheral circuit portion is formed.
Is implanted with p-type impurities, for example, B ions, to thereby obtain p ⁺ of the p-channel type MISFET Qp in the peripheral circuit section.
The semiconductor region 13 is formed. Thereafter, the semiconductor substrate 1 is subjected to a heat treatment at 950 ° C. for about 10 seconds.

As a result, the n-channel type M
ISFET Qn and p-channel MISFET Qp,
An n-channel MISFETQo is formed in the input / output unit.

Next, as shown in FIG.
After a silicon oxide film (not shown) is deposited thereon, the surface of the silicon oxide film is chemically mechanically polished (Chemical Mecha).
The surface is flattened by polishing by a CMP (Nical Polishing) method, thereby forming an interlayer insulating film 16 composed of a silicon oxide film. The silicon oxide film,
For example, ozone (O ₃ ) and tetraethoxysilane (TEO)
And S) as a source gas.

Next, the insulating film of the same layer as the interlayer insulating film 16 and the gate insulating film 6a is sequentially removed by dry etching using a photoresist pattern as a mask, thereby forming one n of the memory cell selecting MISFET Qs.
Forming a contact hole 17a reaching the type semiconductor region 8, the other to form an n ^- contact hole 17b reaching the type semiconductor region 9.

This etching is performed under the condition that the silicon nitride film forming the sidewall spacer 15 is anisotropically etched, and the memory cell selecting MISFET Qs
The silicon nitride film is left on the side wall of the gate electrode 7a. Accordingly, contact holes 17a and 17 having a fine diameter equal to or smaller than the resolution limit of photolithography are obtained.
b is the gate electrode 7 of the memory cell selecting MISFET Qs
It is formed in a self-alignment with respect to a.

Next, contact holes 17a, 17b
The plugs 18a and 18b are respectively formed inside. The plugs 18a and 18b are formed by depositing a polycrystalline silicon film in which an n-type impurity, for example, P is introduced at about 1 × 10 ²⁰ cm ⁻³ , on the interlayer insulating film 16 by a CVD method, and then removing the surface of the polycrystalline silicon film. Polished by CMP method, contact hole 17
It is formed by leaving a polycrystalline silicon film inside a and 17b.

Next, as shown in FIG.
6, a silicon oxide film 19 is deposited. The silicon oxide film 19 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas.

Next, the silicon oxide film 19 on the contact hole 17a is removed by dry etching using a photoresist pattern as a mask to remove the contact hole 20a.
is formed to expose the surface of the plug 18a. Also,
The silicon oxide film 19 of the peripheral circuit portion and the interlayer insulating film 16 are formed by dry etching using the photoresist pattern as a mask.
And the insulating film in the same layer as the gate insulating film 6b is sequentially removed, so that n ^{+ of the} n-channel type MISFET Qn is removed.
A contact hole 20b reaching the p-type semiconductor region 11 is formed, and a contact hole 20c reaching the p ^{+ -type} semiconductor region 13 of the p-channel MISFET Qp is formed. At the same time, the silicon oxide film 19 of the input / output unit and the interlayer insulating film 16
And the insulating film of the same layer as the gate insulating film 6a is sequentially removed, so that n ^{+ of the} n-channel type MISFET Qo is removed.
A contact hole 20d reaching the semiconductor region 11 is formed.

Next, in the memory array, the bit line BL of the memory array in contact with the plug 18a through the contact hole 20a and the contact hole 2 in the peripheral circuit portion.
0b through the first layer wiring M1 in contact with the n ^{+ -type} semiconductor region 11 of the n-channel MISFET Qn, and the p-type MISFET Qp through the contact hole 20c.
The first layer wiring M1 in contact with the ^{+ type} semiconductor region 13 and the first in contact with the n ^{+ type} semiconductor region 11 of the n-channel type MISFET Qo through the contact hole 20d in the input / output section.
The layer wiring M1 is formed. The bit line BL and the first layer wiring M1 are formed by depositing a conductive film (not shown) on the silicon oxide film 19 and then processing the conductive film using a photoresist pattern as a mask.

Next, as shown in FIG. 13, a silicon oxide film (not shown) is deposited on the bit line BL and the first layer wiring M1, and then the surface of the silicon oxide film is
The surface is flattened by polishing by the MP method, and the interlayer insulating film 21 is formed.
To form

Next, the interlayer insulating film 2 on the plug 18b is dry-etched using the photoresist pattern as a mask.
1 and the silicon oxide film 19 are sequentially removed, and the plug 1 is removed.
After forming the through hole 23 reaching 8b, an n-type impurity, for example, P is added to the upper layer of the interlayer insulating film 21 by 1 × 10 ²⁰ cm.
A polycrystalline silicon film (not shown) introduced by about ^-3 is deposited. Next, the polycrystalline silicon film is processed by dry etching using the photoresist pattern as a mask, and the storage electrode 22 of the capacitor is formed. Next, the storage electrode 22
After nitriding or oxynitriding the surface, a tantalum oxide film is deposited, and then the tantalum oxide film is subjected to a heat treatment to crystallize the tantalum oxide film, thereby forming the capacitance insulating film 24. Thereafter, after depositing a titanium nitride film, the titanium nitride film is patterned and a plate electrode 25 is formed.

Thereafter, a silicon oxide film (not shown) is deposited on the upper layer of the capacitor, and the surface of the silicon oxide film is polished by a CMP method to form an interlayer insulating film 26 having a flattened surface. .

Next, the interlayer insulating films 26 and 21 on the first layer wiring M1 in the peripheral circuit section and the input / output section are removed by dry etching using a photoresist pattern as a mask, and the contact reaching the first layer wiring M1 is removed. After forming the holes 27, a conductive film (not shown) is deposited on the interlayer insulating film 26. Next, the conductive film is processed by dry etching using a photoresist pattern as a mask, and the second layer wiring M
2 to form the DRAM shown in FIG.
Is formed.

As described above, according to the present embodiment, p ⁺
M for selecting an n-channel memory cell having a gate electrode
By relatively lowering the impurity concentration of the p-type well 4 in which the ISFET Qs is formed, the memory cell selection MI
The junction electric field strength at the junction between the n ⁻ -type semiconductor region 9 on the capacitor side, which constitutes one of the source and the drain of the SFET Qs, and the p-type well 4 can be reduced. Further, the n-type semiconductor region 8 on the bit line side, which constitutes the other of the source and the drain of the memory cell selection MISFET Qs, is surrounded by the p-type semiconductor region 10 having a relatively high impurity concentration, so that the p-type well 4 has a low level. It is possible to prevent a punch-through phenomenon caused by concentration. Further, since nitrogen introduced into the interface between the gate insulating film 6a and the p-type well 4 has a positive fixed charge, a fixed charge of about 0.05 V with a Vth difference per 1% of interface nitrogen amount in area density. Can be formed, so that the p-type semiconductor region 10 can be formed.
Can be suppressed by introducing nitrogen to the interface between the gate insulating film 6a and the p-type well 4. This can prevent insufficient writing due to a decrease in drain current caused by an increase in Vth.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, when the voltage of the word line at the time of OFF is 0 V
In addition to the MISFET for selecting the memory cell, the voltage of the word line at the time of OFF is set to the negative side (for example, -0.8 V or -0.5 V).
V) M for negative word type memory cell selection
The present invention can be applied to an ISFET, and a similar effect can be obtained.

[0063]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, in the n-channel type memory cell selecting MISFET having the p ⁺ gate electrode, the junction electric field strength between the substrate and the n-type semiconductor region on the capacitor side, which constitutes one of the source and the drain, is reduced. By doing so, the refresh characteristic of the memory cell is improved, and the punch-through phenomenon is suppressed by surrounding the n-type semiconductor region on the bit line side constituting the other of the source and the drain with a p-type semiconductor region.
Furthermore, by introducing nitrogen to the interface between the gate insulating film and the substrate, a desired Vth can be obtained, and the writing characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a DRAM according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

1 semiconductor substrate 2 trench element isolation insulating film 3 n form buried well 4 p type well 5 n-well 6a gate insulating film 6b gate insulating film 7a gate electrode 7b gate electrode 8 n-type semiconductor region 9 n ^- type semiconductor region 10 p-type semiconductor region 11 n ^{+ -type} semiconductor region 12 p ^--type semiconductor region 13 p ^{+ -type} semiconductor region 14 silicon nitride film 15 sidewall spacer 16 interlayer insulating film 17a contact hole 17b contact hole 18a plug 18b plug 19 silicon oxide film 20a contact Hole 20b Contact hole 20c Contact hole 20d Contact hole 21 Interlayer insulating film 22 Storage electrode 23 Through hole 24 Capacitive insulating film 25 Plate electrode 26 Interlayer insulating film 27 Contact hole 28 Gate insulating film 29 Resist film 3 a p ⁺ form silicon film 30b n ⁺ form silicon film 31 tungsten film Qn n-channel type MISFET Qp p-channel type MISFET Qs for memory cell selection MISFET Qo n-channel type MISFET A p-channel type MISFET region B n-channel type MISFET region BL bit Line WL Word line M1 First layer wiring M2 Second layer wiring

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shinichiro Kimura 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo F-term (reference) 5F048 AB01 AC03 BA01 BB06 BB07 BB09 BB12 BC06 BE02 BF04 BG01 BG13 DA01 DA27 5F083 AD42 AD48 GA30 JA06 JA39 MA06 MA17 MA19 MA20 NA01 PR03 PR21 PR33 PR34 PR36 PR40

Claims (5)

[Claims] An MISFET whose threshold voltage is adjusted by introducing nitrogen into an interface between a gate insulating film and a substrate.
A semiconductor integrated circuit device comprising: 2. A MISFET whose threshold voltage is adjusted by introducing nitrogen into an interface between a gate insulating film and a substrate.
And the MISFET is connected in series with a capacitor to form a memory cell.
T is a semiconductor integrated circuit device. 3. A MISFET whose threshold voltage is adjusted by introducing nitrogen into an interface between a gate insulating film and a substrate.
Wherein the MISFET is an n-channel type memory cell selecting MISFET having ap ⁺ gate electrode which is connected in series with a capacitor to form a memory cell. 4. A MISFET whose threshold voltage is adjusted by introducing nitrogen into an interface between a gate insulating film and a substrate.
The MISFET is an n-channel type memory cell selecting MISFET having ap ⁺ gate electrode connected in series with a capacitor to form a memory cell, and one of a source and a drain of the memory cell selecting MISFET. Wherein the junction electric field of the semiconductor region constituting the semiconductor integrated circuit differs from the junction electric field of the semiconductor region constituting the other of the source and the drain of the memory cell selecting MISFET. 5. A first MISFET having a relatively large amount of nitrogen introduced at an interface between a first gate insulating film and a substrate;
A second MISFET having a relatively small amount of nitrogen introduced at an interface between the second gate insulating film and the substrate, wherein the first MISFET is connected in series with a capacitor to form a memory cell A memory cell selecting MISFET, wherein the second MISFET is a MISFE of a peripheral circuit section.
T is a semiconductor integrated circuit device.