JPS62232963A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacity markedly by a method wherein a step difference part near or above a contact region and a not yet ion-implanted part of a layer to be ion-implanted formed in the contact region are removed by etching process to make a fine window. CONSTITUTION:Polycrystalline Si ion-implanted layers 19 such as SiN4 films and the other material with different etching rate are left on the sidewalls of the step difference part of a base electrode end while overall surface is implanted with N2<+>or O2<+>ion etc. The polycrystalline Si implanted N2<+>ion and the like is formed into a film more hardly etched by KOH than the other films formed cf undoped polycrystalline. A fine window e.g. 1000Angstrom thick can be made making use of the different etching rate between an ion-implanted polycrystalline Si layer 18a and an Si3N4 film 18b. Later, an exposed part of this semiconductor substrate and the base electrode are connected by an impurity containing semiconductor layer and then the impurity is diffused into the substrate to form a graft base 7. Finally, an intrinsic base part is formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] In order to reduce the parasitic capacitance of the device and achieve miniaturization of the device, the present invention utilizes self-alignment lines to take out external electrodes such as polysilicon and the active area of the device. This invention relates to a method of manufacturing a semiconductor device that connects approximately 1,000 people with a fine width, and is an improved invention of Japanese Patent Application No. 11249 and No. 11250 of 1988 (hereinafter referred to as the prior invention) filed by the present applicant.

〔overview〕

This invention relates to a method for manufacturing a semiconductor device in which an external bridge made of polycrystalline Si or the like is connected to a contact region of a transistor or the like by a self-aligned line with a fine width. An ion-implanted layer is formed in the ion-implanted layer, and ions are implanted into the ion-implanted layer except for the sidewalls of the stepped portion and the contact portion. Taking advantage of the difference in etching ratio between the ion-implanted and non-ion-implanted areas, the ion-implanted layer is removed. By etching away the missing portions and forming fine windows, parasitic capacitance can be significantly reduced, thereby providing a method for manufacturing transistors and the like suitable for high-speed, highly integrated LSIs.

[Conventional technology]

In recent years, the operating speed of bipolar LSIs has increased, and patterns have become finer and junctions have become shallower. In order to reduce the base width of a bipolar transistor, it is necessary to make the base diffusion and emitter diffusion shallower. For that reason P
Boron ion implantation is used for type base diffusion, and As diffusion from As-doped polycrystalline Si is used for N type emitter.

Oxide film isolation is used for isolation between elements for reasons such as reducing stray capacitance. An example of a transistor made using these techniques is the LOGOS l shown in Figure 2A.
- It is a transistor. This is LOGOS (Local
Although the transistor is manufactured using the oxidation of silicon (oxidation of silicon) technology, the intrinsic base region and the graft base are formed separately with a margin for mask alignment. In the improved transistor shown in FIG. 2B, parasitic capacitance is reduced by using polycrystalline Si9 for lead electrodes such as the base region.

[Problem that the invention seeks to solve]

In the cross-sectional view of the transistor shown in FIG. 3A, the width of the active region of the transistor is significantly larger than that of the other regions. Therefore, the parasitic components (capacitance, resistance) have the drawback of limiting the speed-up of the transistor.

On the other hand, the transistor shown in Fig. 3B improves the drawbacks of the transistor structure shown in Fig. 3A by using polycrystalline St for the base electrode, and although the parasitic components are reduced, the emitter - As the stripe width becomes finer, the width a of the base contact portion becomes relatively larger than the intrinsic base width. This graft base region (a in FIG. 3B) is usually formed by diffusion from the polycrystalline Si layer 9 and is connected to the intrinsic part, but in addition to the width a of the contact part, there is a It was not possible to make it sufficiently narrow because it required a margin of . In particular, as the emitter stripe width continues to shrink in the future, this parasitic capacitance due to the graft base will become a major problem.

[Means for solving problems]

A contact region formed on a semiconductor substrate, and a step portion formed near or above the contact h GW region, and the step portion and the plane where the contact region is formed are in contact with each other or in the vicinity thereof. In a method of manufacturing a semiconductor device having a contact portion with a contact region, a step of forming an ion-implanted layer covering an SI region (contacting with the step portion), and connecting the contact portion and the step portion of the ion-implanted layer a step of implanting ions into a region excluding the sidewall; and a step of performing etching under conditions that provide a selectivity between the ion-implanted region and the non-ion-implanted region, and etching away the non-ion-implanted region. By the method of manufacturing a semiconductor device consisting of 10
The above-mentioned problems have been solved by forming the graft base part with Selfaline.

[Effect]

A substance with a different etching rate from the polycrystalline Si ion-implanted layer, such as a SiN4 film, is left on the side wall of the step at the end of the base electrode by anisotropic etching, and inert ions such as N2+ or 0□9 are ionized over the entire surface. Inject (Fig. 1E)
. Polycrystalline Si implanted with ions such as N2°
Annealing at about 900° C. results in a film that cannot be etched by KOH. The present invention utilizes the difference in etching ratio between the ion-implanted polycrystalline Si layer and the Si3N4 film to form a minute window of 1000 layers. Since this window is determined by the thickness of the 5iJa film, a fine width can be reliably obtained. Thereafter, the exposed portion of the semiconductor substrate and the base electrode are connected with an impurity-containing semiconductor layer, and the impurity is diffused into the substrate to form a graft base (
Figure 1 F). Furthermore, using a sidewall formed by anisotropically etching the impurity-containing semiconductor layer as a mask, an intrinsic base portion is formed (FIG. 1H). As is clear from these manufacturing steps, each region is formed in self-alignment.

〔Example〕

Example (i) The basic process of the present invention will be explained for each step of an NPN transistor.

Step After forming N+ buried N3 and P channel stopper 2 on AP type substrate 1, N type epitaxial layer 6 is grown. After this, insulation isolation is performed using an oxide film 4.4'.
An N+ collector extraction portion 5 is formed. Next, 3000 layers of 5i02 film 15 are grown using the CVD method, and 1500 layers of polycrystalline Si9 are further formed using the CVD method. Since this polycrystalline Si9 will be used for an extraction electrode such as a base after the element is completed, it is doped with P-type impurities to make it low in resistance.

Step B: After removing unnecessary portions of the polycrystalline Si 9 by photoetching, the entire Sing film 16 is grown by the 16D method.

RI E (Reactive Ton Eching)
) method to form the active region that will become the base emitter portion and the windows 25 and 26 for extracting the collector.

Step C: After forming a 50-layer SiO□ film 17 by thermal oxidation, a 2000-layer polycrystalline Si film 18a' is formed by the CVD method, and a SiJ film 18b, which becomes an oxidation-resistant film, is formed on top of it by the CVD method.
grew by 1000 people.

Process DRI E (Reactive Ion Et)
The upper layer 5iJ4 film 18b is removed by the 5iJ4 film 18b using the 5iJ4 film 18b, leaving the Si3N film 18b in the form of a sidewall only on the side wall of the window, as shown in FIG. 1D'.

Process E Nz” was accelerated at 40keV to form polycrystalline Si.
After doping the film 18a with 5×10”/cn1 or more, 8
Annealing is performed at 00° C. for 30 minutes to form a polycrystalline Si film 19 having KOH solution resistance.

In this example, N23 was used as the ion, but
It is also possible to use ions of other elements that do not function as impurities, such as 0□゛. .

Step E: Sidewall-shaped 5iJ4 with hot phosphoric acid
After removing the film 18b, polycrystalline S is formed using KOII solution.
The i-film 18a is also removed to expose a 1000 person wide window on the substrate surface.

Step F A polycrystalline Si film 20 of 2,000 layers is formed by the CVD method, a photoresist is applied thereon, a window is opened on the base region side, and B ions are implanted. Similarly, As ions are implanted into the collector extraction side. Since the diffusion constant of these impurities in polycrystalline Si is large, heat treatment at a low temperature of 800°C will
These impurities can be diffused into the polycrystalline Si, thereby establishing contact between the polycrystalline Si layer 20 and the base extraction region.

Step G Polycrystalline S is formed by RIE method using chlorine gas.
The i film 20 is etched to leave the polycrystalline Si film 20 in the form of a sidewall as shown in FIG. 1G'. Here, the ion-implanted polycrystalline Si layer 19 may be removed by RIE, and if necessary, a stabilizing film for ion implantation may be formed.

Step H Using photoresist 21 as a mask, BF is 60
Ion implantation is performed with acceleration to Kev, and a base intrinsic part is formed by the sidewall-like polycrystalline Si film and the self-alignment line.

Step I: 3000 5in2 films 22 are formed by CVD method.

Step J RIE method is used to remove the SiO□ film 22 on the top surface, leaving only the S+02 film 22 on the sidewall.

Step K Mask the area other than the collector part with photoresist, and remove the sidewall-shaped 5i02 film 22 in the collector part by etching.

Step L: Use photoetching to form windows 24 for base contacts. If a polycrystalline Si film is used for a resistor or the like, this serves as a contact window.

Note that the removal of the 5i02 film 22 in the collector region in step K and the opening of the base contact window in step K can be performed at the same time.

Step M: Form 1000 polycrystalline 5ilO by CVD method.

Step N Using the photoresist 11 as a mask, As ions are implanted, and emitter vines 8 are formed by subsequent diffusion.

Step 0 The base, emitter, and collector electrodes 12, 13, and 14 are formed in the same manner as in the conventional method.

Example (ii) This example differs from Example (i) in that a three-layer film is provided on the main SiO□ film 17: +Nn film - polycrystalline Si film - 3i3Nn film. A process different from Example (i) will be explained based on FIG. 2.

Step D' A new 5iJ4 film 18c is provided between the SiO2 film 17 and the polycrystalline Si film 18a, and a Si
A three-layer film consisting of 3N, film 18c, polycrystalline Si film 18a, and 5i3Na film 18b is formed.

The uppermost 5iJ4 film 18b is removed by RIE to expose the polycrystalline Si film 18a, and at the same time, the St zN4 film 18b is left in the form of a sidewall.

Process E Nz'' is accelerated at 40keV to form polycrystalline Si.
After doping the film 18a with 5×10”/cn! or more, 8
By annealing at 00° C. for 30 minutes, a polycrystalline Si film 19 having 011 solution resistance is formed.

In this example, N2゛ was used as the ion.
It is also possible to use ions of other elements that do not function as impurities, such as 0□°.

Step E After removing the sidewall-shaped Si3N4 film 18b with hot phosphoric acid, the polycrystalline Si film 18a is also removed with a KOH solution, and the SiN film 18c is removed again with hot phosphoric acid to form a 1000-layer width film on the substrate surface. Expose the window.

Process ■ Instead of uniformly forming the Si film 22 as in Example (i), the bottom layer of Si newly provided in Process C is
3N and film 18c as a mask, only the surface of the sidewall-shaped polycrystalline Si is thermally oxidized to form an oxide film 22'.

〔effect〕

The contact between the external electrode extraction region such as polycrystalline Si (or polycide) and the active region (base) of the transistor is made using sidewall technology in a self-fabricated manner with a microscopic width of approximately 1000 mm, which corresponds to the thickness of the oxidation-resistant film. could be formed into a line.

This eliminates the need for margins in mask alignment that were conventionally required when forming this region, and it was possible to significantly reduce the capacitance due to the graft base other than the intrinsic part of the collector-base junction capacitance of the transistor. . Furthermore, since the transistor of the present invention adopts a structure in which there is no LOGOS oxide film between the collector and base, which existed in conventional transistors, parasitic capacitance is significantly reduced, resulting in higher speed and higher integration of LSI. was achieved.

Further, in the present invention, the polycrystalline Si film 18a is converted into a Koji-resistant film 19 by ion implantation in step E, whereas in the prior invention, the polycrystalline Si film 18a is thermally oxidized to become KOII-resistant. It formed a film.

Since the present invention does not require a high temperature treatment step,
Redistribution of impurities can be prevented, and Si can be
Since there is no increase in volume when changing to , a narrow window can be stably obtained.

[Brief explanation of drawings]

FIG. 1A-0 is a diagram showing each step of the manufacturing method according to the first embodiment of the present invention. FIGS. 2D', E, E', and (2) are diagrams showing the steps of the manufacturing method of the second embodiment of the present invention. FIG. 3 is a diagram showing a conventional LOGO3) transistor and its improved transistor. ■...P-type substrate 2,...P channel stopper 3...
...N buried layer 4,4'...Oxide film 5,
...N collector extraction part 6, ...N type epitaxial layer 7, ...
・Base area 8. ...Emitter region 7'
... Graft base region 9, ... Polycrystalline Si layer lO6 ...
・Polycrystalline 5iN11,...Photoresist 1
2. ...Base N pole 13, ...Emitter electrode 14. ...Collector electrode 15, ...
...Si0g film 16.・・・・・・Si
n, film 17, thin oxide film 18a...
...Polycrystalline Si films 18b, 18c...Si
3N, film 19, ion-implanted polycrystalline S
i film 20, ... polycrystalline 5i 21, ... photoresist film 22, ... SiO□ film

Claims (1)

[Scope of Claims] A contact region formed on a semiconductor substrate, and a step portion formed near or above the contact region, and a portion where the step portion and the plane on which the contact region is formed are in contact with each other, or a portion thereof. In a method of manufacturing a semiconductor device having a contact portion with the contact region in the vicinity, forming an ion-implanted layer covering the step portion and the contact region; A step of implanting ions into the region excluding the sidewalls of the stepped portion, and performing etching under conditions that provide a selectivity between the ion-implanted region and the non-ion implanted region, and etching away the non-ion implanted region. A method for manufacturing a semiconductor device comprising steps.