JPS61269374A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61269374A JPS61269374A JP11124985A JP11124985A JPS61269374A JP S61269374 A JPS61269374 A JP S61269374A JP 11124985 A JP11124985 A JP 11124985A JP 11124985 A JP11124985 A JP 11124985A JP S61269374 A JPS61269374 A JP S61269374A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- semiconductor substrate
- base
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title description 14
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000012476 oxidizable substance Substances 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000000034 method Methods 0.000 description 15
- 229910005091 Si3N Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000605 extraction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は素子の寄生容量の低減及び素子の微細化を実現
するために、ポリシリコン等の外部電極取出しと素子の
能動領域をセルファラインで１０００Ａ程度の微細な幅
により接続させる半導体装置の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] In order to reduce the parasitic capacitance of the device and achieve miniaturization of the device, the present invention utilizes a self-line method for extracting external electrodes such as polysilicon and the active region of the device. The present invention relates to a method of manufacturing a semiconductor device that is connected by a fine width of about 1000A.
［概要］
この発明は、多結晶Ｓｉ等の外部電極とトランジスタ等
のベース、コレクタ等のアクティブ領域とのコンタクト
をセルファラインで、微細な幅で形成する半導体装置の
製造方法において、ベース電極端部段差部の側壁に耐酸
化物を異方性エツチングにより残し、他部を酸化した後
これを選択エツチングして微細な窓を形成することによ
り、寄生容量を大幅に減らし、高速化、高集積化したＬ
ＳＩに向くトランジスタ等の製造方法を提供するもので
ある。[Summary] The present invention provides a method for manufacturing a semiconductor device in which a contact between an external electrode made of polycrystalline Si or the like and an active region such as a base or collector of a transistor is formed with a self-aligned line with a fine width. By anisotropically etching an oxide-resistant material on the sidewalls of the step, oxidizing other parts, and then selectively etching it to form fine windows, parasitic capacitance is significantly reduced, speeding up, and high integration. L
The present invention provides a method for manufacturing transistors and the like suitable for SI.
［従来の技術］
近年パターンの微細化と接合のシャロー化が進んで、バ
イポーラＬＳＩが高速化している。バイポーラトランジ
スタのベース幅を薄くするために、浅いベース拡散とエ
ミッタ拡散が必要であるが、そのためにベース拡散には
ボロンのイオン注入が、エミッタにはＡｓドープの多結
晶ＳｔからのＡｓ拡散等が用いられている。浮遊容量の
低減等の理由から素子間分離には酸化膜分離が採用され
ている。これらの技術を用いて作られたトランジスタの
一例が、第６図Ａに示されたＬＯＧＯ９）ランジスタで
ある。これはＬＯＧＯ９（Ｌｏｃａｌ ０ｘｉｄａｔｉ
ｏｎ ｏｆＳｉｌｉｃｏｎ）を用いて作られたトランジ
スタであるが、イントリンシックなベースとグラフトベ
ースがマスク合わせの余裕度を持って別々に形成されて
いる。第６図Ｂの改良トランジスタにおいては、多結晶
Ｓｉ９がベース領域等の引き出し電極として用いられ、
寄生容量を減少させている。[Prior Art] In recent years, patterns have become finer and junctions have become shallower, and bipolar LSIs have become faster. In order to reduce the base width of bipolar transistors, shallow base diffusion and emitter diffusion are necessary. To achieve this, boron ion implantation is used for the base diffusion, and As diffusion from As-doped polycrystalline St is used for the emitter. It is used. Oxide film isolation is used for isolation between elements for reasons such as reducing stray capacitance. An example of a transistor made using these techniques is the LOGO9) transistor shown in FIG. 6A. This is LOGO9 (Local Oxidati
Although the transistor is manufactured using an on-of-Silicon method, the intrinsic base and the graft base are formed separately with sufficient margin for mask alignment. In the improved transistor shown in FIG. 6B, polycrystalline Si9 is used as an extraction electrode for the base region, etc.
Reduces parasitic capacitance.
［発明が解決しようとする問題点］
第６図Ａのトランジスタの断面図においては、トランジ
スタのアクティブ領域に比較してそれ以外の領域が大幅
に大きくなっている。そのためその寄生成分（容量、抵
抗）によって、トランジスタの高速化が制限されてしま
うという欠点があった。[Problems to be Solved by the Invention] In the cross-sectional view of the transistor in FIG. 6A, the other regions are significantly larger than the active region of the transistor. Therefore, the parasitic components (capacitance, resistance) have the disadvantage of limiting the speed-up of the transistor.
一方、第６図Ｂのトランジスタは、ベース電極に多結晶
Ｓｉを用いて第６図Ａのトランジスタ構造の欠点を改良
したもので、寄生成分は減少しているがこの構造のトラ
ンジスタにおいても、エミッタ・ストライプ幅が微細化
するに連れて、ベースコンタクト部（Ｐ 部、第６図Ｂ
に於けるａ）の幅がイントリンシックなベース（第６図
Ｂに於けるｂ）に比較して相対的に大きくなって来る。On the other hand, the transistor shown in FIG. 6B uses polycrystalline Si for the base electrode to improve the drawbacks of the transistor structure shown in FIG.・As the stripe width becomes finer, the base contact part (P part, Fig. 6B)
The width of a) in FIG. 6B becomes relatively large compared to the intrinsic base (b in FIG. 6B).
このグラフトベース領域（第６図Ｂに於げるａ）は通常
多結晶Ｓｔからの拡散で形成され、イントリンシック部
と接続されているが、コンタクト部の幅量外に、マスク
合わせのための余裕度が必要となることから、充分に狭
くすることができなかった。特に、今後エミッタストラ
イプ幅が縮小して行く状況においては、このグラフトベ
ースによる寄生容量は大きな問題となって来る。This graft base region (a in Figure 6B) is usually formed by diffusion from polycrystalline St and is connected to the intrinsic part, but in addition to the width of the contact part, there is a Since a margin was required, it was not possible to make it sufficiently narrow. In particular, as the emitter stripe width continues to shrink in the future, this parasitic capacitance due to the graft base will become a major problem.
本発明は、このグラフトベース部を１０００λ程度でセ
ルフ・アラインに形成する製造方法により上記問題点を
解決するものである。The present invention solves the above problems by using a manufacturing method in which the graft base portion is formed in a self-aligned manner with a thickness of about 1000λ.
［問題点を解決するための手段］
半導体基板上に絶縁層を介して形成されたベース電極の
端部に段差部を形成し、この上に半導体層と耐酸化物層
を一面に形成し、異方性エツチングを行なって上記段差
部側壁部に上記耐酸化物層を残す、このサイドウオール
状に残された耐酸化物層をマスクとして、半導体層の露
出部の表面を酸化した後、上記耐酸化物層と半導体層を
除去して半導体基板が一部露出する開孔部を形成し、さ
らにその開孔部に不純物含有半導体層を形成して、不純
物を半導体基板に拡散させてグラフトベース領域を形成
させる。さらに絶縁層をマスク１、明細書第６頁を下記
掩塙り全文浄書する。[Means for solving the problem] A stepped portion is formed at the end of a base electrode formed on a semiconductor substrate with an insulating layer interposed therebetween, and a semiconductor layer and an oxide-resistant layer are formed over the stepped portion, and a different Directional etching is performed to leave the oxidation-resistant layer on the sidewall of the stepped portion. Using this oxidation-resistant layer left in the form of a sidewall as a mask, the surface of the exposed portion of the semiconductor layer is oxidized, and then the oxidation-resistant layer is etched. and removing the semiconductor layer to form an opening through which a portion of the semiconductor substrate is exposed, further forming an impurity-containing semiconductor layer in the opening, and diffusing the impurity into the semiconductor substrate to form a graft base region. . Furthermore, using Mask 1 for the insulating layer, the entire text of page 6 of the specification is printed using the following cover-up.
とじてエミッタ領域を形成する０本願発明はこのような
製造方法によって上記問題点を解決している。The present invention solves the above problems by using such a manufacturing method.
［作用］
本発明は、ベース電極端部段差部の側壁に耐酸化物を異
方性エツチングにより残し、この耐酸化物をマスクとし
て半導体層の露出部分を酸化する（第３図Ｅ）、この耐
酸化物と酸化されていない半導体層を選択エツチングし
て１００ＯＡという微細な窓を形成している。この窓は
耐酸化膜の厚みで決まるので、確実に微細な幅が得られ
る。この半導体基板の露出部と前記ベース電極を不純物
含有半導体層で接続し、この不純物を基板に拡散させて
グラフトベースを形成する（第４図Ｆ）、さらに不純吻
合半導体層を異方性エツチングしたサイドウオールをマ
スクとして、イントリンシックなベース部を形成してい
る（第５図Ｈ）、これらの製造工程から明らかなように
、各領域はセルフ・アラインで形成される。半導体基板
上に露出する窓の幅が耐酸化物の膜厚（ｔ、ｏｏｏＸ程
度）であり、かつこれがセルファラインで形成できるこ
とは、従来マスクによりこの領域を形成した時に要した
マスク合わせの余裕度が必要なくなったことからみて、
非常に大きなメリットとなる。[Function] The present invention leaves an oxide resistant material on the side wall of the stepped portion at the end of the base electrode by anisotropic etching, and uses this oxide resistant material as a mask to oxidize the exposed portion of the semiconductor layer (FIG. 3E). A fine window of 100 OA is formed by selectively etching the unoxidized semiconductor layer. Since this window is determined by the thickness of the oxidation-resistant film, it is possible to reliably obtain a fine width. The exposed portion of this semiconductor substrate and the base electrode were connected with an impurity-containing semiconductor layer, and the impurity was diffused into the substrate to form a graft base (FIG. 4F). Furthermore, the impurity anastomotic semiconductor layer was anisotropically etched. The intrinsic base portion is formed using the sidewall as a mask (FIG. 5H). As is clear from these manufacturing steps, each region is formed in a self-aligned manner. The width of the window exposed on the semiconductor substrate is the thickness of the oxide resistant film (about t, ooo Considering that it is no longer necessary,
This is a huge benefit.
［実施例］
実施例（ｉ）
本発明の基本的プロセスをＮＰＮ ）ランジスタについ
て各工程毎に説明する。[Example] Example (i) The basic process of the present invention will be explained for each step of an NPN transistor.
工程ＡＰ型基板１にＮ 埋込層３とＰ チャンネルスト
ッパー２を形成した後、Ｎ型エピタキシャル層６を成長
させる。この後醸化膜４．４′による絶縁分離を行ない
。Step After forming the N 2 buried layer 3 and the P 2 channel stopper 2 on the AP type substrate 1, the N type epitaxial layer 6 is grown. After this, insulating separation is performed using the fermented film 4.4'.
Ｎ コレクタ取出し部５を形成する０次にＣｖＤ法ニヨ
リ３０００λｆ） Ｓ ｉ ０２膜１５を成長させて、
さらに多結晶Ｓｉ９をＣＶＤ法により １５００λ形成
する。この多結晶Ｓｉ９は、素子の完成後にはベース等
の取り出し電極に使用されるので、Ｐ型不純物をドープ
させて低抵抗にしておく。Grow the S i 02 film 15 (0-order CvD method (3000λf) to form the N collector extraction part 5,
Furthermore, polycrystalline Si9 having a thickness of 1500λ is formed by CVD. Since this polycrystalline Si9 will be used for an extraction electrode such as a base after the element is completed, it is doped with P-type impurities to make it low in resistance.
工程Ｂ 多結晶Ｓｉ９をフォトエツチングして不要部分
を除去してから、５１０２膜１６をＣＶＤ法により成長
させる。Step B: Polycrystalline Si 9 is photoetched to remove unnecessary portions, and then 5102 film 16 is grown by CVD.
ＲＩ Ｅ （Ｒｅａｃｔｉｖｅ ｆａｎ Ｅｃｈｉｎｇ
）法により、ベース・エミッタ部分となる能動領域とコ
レクタ取り出しの窓２５．２６を形成する。RI E (Reactive fan Eching)
) method to form the active region that will become the base emitter portion and the windows 25 and 26 for extracting the collector.
工程Ｃ熱酸化により５０大の５Ｉ０２１１１７を形成し
た後、２０００Ｘの多結晶５ｉｌｌ１８ａをｃｖＤ法に
より形成し、その上に耐酸化膜となるＳｉ３Ｎ、ＩＩＩ
Ｅ １８ ｂをｔｏｏｏｆ成長させた。Step C After forming 5I021117 with a size of 50 by thermal oxidation, a polycrystalline 5ill18a with a size of 2000X is formed by the CVD method, and Si3N, III, which becomes an oxidation-resistant film, is formed on it by the CVD method.
E 18 b was grown too much.
工程Ｄ ＲＩ Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅ
ｔｃｈｉｎｇ）法により上層のＳｉ３Ｎ、ＩＮｌ ｌ
８ ｂをエツチングして第３図Ｄ′に示されるように窓
の側壁のみにサイドウオール状にＳｉ３Ｎ、ＩＩ ｌ
８ ｂを残す。Process DRI E (Reactive Ion E
The upper layer of Si3N, INl
8b and etched Si3N, IIl in the form of a sidewall only on the side wall of the window as shown in Figure 3D'.
8 Leave b.
工程Ｅ サイドウオール状のＳｉ３Ｎ、Ｉｌｌ １８
ｂをマスクとして、多結晶５ｉ１８ａを熱酸化させてＳ
ｉｏ ２膜１９を形成する。Process E Sidewall-shaped Si3N, Ill 18
Using b as a mask, polycrystalline 5i18a is thermally oxidized to form S
io2 film 19 is formed.
工程Ｅ’ ５ｔ３Ｎ４膜１８ｂと多結晶５ｉ１８ａと
５１０２膜１７を選択エツチングして、酸化膜１５と酸
化膜１９の間に５４３Ｎ、ＩＩＩＥ １８ ｂの厚さに
対応する１０００にの狭い幅の窓を形成する。Step E' Selectively etching the 5t3N4 film 18b, the polycrystalline 5i 18a, and the 5102 film 17 to form a narrow window of 1000 mm between the oxide film 15 and the oxide film 19, corresponding to the thickness of 543N, IIIE 18b. do.
工程Ｆ ２０ＧＯＡの多結晶Ｓｉ膜２０をＣＶＤ法に
より形成して、その上にフォトレジストをかけて、ベー
ス領域側に窓を開けて、Ｂをイオン注入する。同様にし
てコレクタ取り出し側にはＡｓをイオン注入する。これ
らの不純物の多結晶Ｓｉ中のの拡散定数は大きいので、
８００″Ｃの低温加熱処理により、これらの不純物は多
結晶Ｓｉ中を拡散して、ベース取り出し結晶Ｓｉとのコ
ンタクトがとられる。Step F A polycrystalline Si film 20 of 20 GOA is formed by the CVD method, a photoresist is applied thereon, a window is opened on the base region side, and B ions are implanted. Similarly, As ions are implanted into the collector extraction side. Since the diffusion constant of these impurities in polycrystalline Si is large,
By low-temperature heat treatment at 800''C, these impurities diffuse into the polycrystalline Si and come into contact with the base-extracting crystalline Si.
工程Ｇ 塩素系のガスを用いたＲＩＥ法により多結晶Ｓ
ｉ膜２０をエツチングし第５図Ｇ’ 【＝示すようにサ
イドウオール状に多結晶Ｓｉ膜２０を残す、ここで酸化
膜１９をＲＩＥ法で除去し、さらに、必要に応じてイオ
ン注入用安定化膜を形成してもよい。Step G Polycrystalline S is formed by RIE method using chlorine gas.
The i film 20 is etched to leave the polycrystalline Si film 20 in the form of a sidewall as shown in FIG. A chemical film may be formed.
工程Ｇ ベース及びコレクタ形成領域上の、ＳｉＯ□膜
、Ｓｉ３Ｎ４膜をＲＩＥ法等により除去し、必要に応じ
てイオン注入用安定化膜を形成する。Step G: The SiO□ film and Si3N4 film on the base and collector forming regions are removed by RIE method or the like, and a stabilizing film for ion implantation is formed if necessary.
工程Ｈフォトレジスト２１をマスクにしてＢＦ２を８０
Ｋｅマに加速してイオン注入を行ない、サイドウオー
ル状多結晶Ｓｉ膜とセルファラインでベースイントリン
シック部を形成する。Step H Using photoresist 21 as a mask, apply BF2 to 80%
Ion implantation is performed at high acceleration speed to form a base intrinsic portion with the sidewall-like polycrystalline Si film and the self-alignment line.
工程Ｉ ３０００λ（１） ５１０２膜２２をＣＶＤ
法ニヨり形成する。Step I 3000λ (1) CVD 5102 film 22
Forming a law.
工程Ｊ ＲＩＥ法により、上面のＳ ｉｏ ２膜を除
去してサイドウオールのＳ ＋ ０２膜２２のみをを残
す。Step J The S io 2 film on the top surface is removed by RIE method, leaving only the S + 02 film 22 on the sidewall.
工程Ｋ フォトレジストでコレクタ部分以外をマスクし
て、コレクタ部分にあるサイド
ウオール状のＳ ｉ Ｏ２膜をエツチング除去する。Step K Mask the area other than the collector part with photoresist, and remove the sidewall-shaped SiO2 film in the collector part by etching.
工程Ｌ フォトエツチングを使用して、ベースコンタク
ト用の窓２４を形成する。多結晶Ｓｉ膜を抵抗等に使用
している場合には、そのコンタクト用の窓となる。Step L: Use photoetching to form windows 24 for base contacts. If a polycrystalline Si film is used for a resistor or the like, this serves as a contact window.
工程Ｍ ＩＧＯＯＡ多結晶５ｉｌｏをＣＶＤ法ニヨり
形成する。Step M IGOOA polycrystal 5ilo is formed by CVD method.
工程Ｎ フォトレジスト１１をマスクにして、Ａｓをイ
オン注入して、その後の拡散によってエミッタ８を形成
する。Step N: Using the photoresist 11 as a mask, As ions are implanted, and the emitter 8 is formed by subsequent diffusion.
工程０ 従来法と同様にしてベース、エミッタ、コレク
タの各々の電極１２．１３．１４を形成する。Step 0 The base, emitter, and collector electrodes 12, 13, and 14 are formed in the same manner as in the conventional method.
実施例（ｉｉ）
本実施例に於ては、 ５ｉＯ７膜１７上に５１３Ｎ−一
多結晶Ｓｉ膜−９ｉ３Ｎ４膜の３層の膜を設ける点が実
施例（ｉ）と異なる。実施例（ｉ）と異なる工程を次に
示す。Example (ii) This example differs from Example (i) in that three layers of 513N--polycrystalline Si film and 9i3N4 film are provided on the 5iO7 film 17. The steps different from Example (i) are shown below.
工程ＣＳ ｉ ０２膜１７と多結晶Ｓｉ膜１８ａの間に
Ｓｉ３Ｎ、膜を設け、熱酸化膜１７の上に５ｔ３Ｎ、膜
−多結晶ｇｉ膜づ１３Ｎ４膜からなる３層の膜を形成す
る。Process: A Si3N film is provided between the CS i02 film 17 and the polycrystalline Si film 18a, and a three-layer film consisting of a 5t3N film and a polycrystalline gi film and a 13N4 film is formed on the thermal oxide film 17.
工程ＤＤ ＲＩＥ法により最上のＳｉ３Ｎ４膜を除去
して多結晶Ｓｉ膜を露出させ、同時に、サイドウオール
状にＳｉ３Ｎ４膜を残す。Step DD RIE method is used to remove the uppermost Si3N4 film to expose the polycrystalline Si film, and at the same time leave the Si3N4 film in the form of a sidewall.
工程Ｅ Ｓ ｒ ０２膜１９をマスクとしてＳｉ３Ｎ
、膜１８ｂ、多結晶Ｓｉ膜、Ｓｉ３Ｎ、膜を除去して、
開孔部を形成する。Process E Sr02 film 19 is used as a mask to form Si3N
, film 18b, polycrystalline Si film, Si3N film are removed,
Form an opening.
工程！ 実施例（ｉ）のようにＳ ＋ ０２膜２２を一
様に形成するのではなく、工程Ｃで設けた最下層のＳｉ
３Ｎ４膜をマスクとして、サイドウオール状の多結晶Ｓ
ｉの表面のみを熱酸化して第６図Ｊに示される酸化膜２
２と同様なものを形成する。Process! Instead of forming the S + 02 film 22 uniformly as in Example (i), the lowermost Si layer provided in step C
Using the 3N4 film as a mask, sidewall-shaped polycrystalline S
The oxide film 2 shown in FIG. 6J is obtained by thermally oxidizing only the surface of i.
Form something similar to 2.
［効果］
多結晶Ｓｉ （或いはポリサイド）等の外部電極取出し
とトランジスタのアクティブ領域（ベース）とのコンタ
クトを、サイドウオール技術を用いて１０００Ａ程度の
微細な幅でセルファラインに形成することができた。こ
れによって、トランジスタのコレクター・ベース接合容
量のうちイントリンシック部以外のグラフトベースによ
る容量を大幅に減らすことができた。さらに本発明の製
造方法によるトランジスタの微細化（例、従来のトラン
ジスタにあったコレクターベース間のＬＯＧＯ９酸化膜
が存在しない構造）も加えて、寄生容量が格段に減少し
た。このため本発明によりＬＳＩの高速化、高集積化が
達成できる。[Effects] Contact between the external electrode of polycrystalline Si (or polycide) and the active region (base) of the transistor could be formed in a self-aligned line with a fine width of about 1000A using sidewall technology. . As a result, it was possible to significantly reduce the capacitance due to the graft base other than the intrinsic portion of the collector-base junction capacitance of the transistor. Furthermore, in addition to miniaturization of the transistor by the manufacturing method of the present invention (for example, a structure in which the LOGO9 oxide film between the collector base and the base of the conventional transistor does not exist), the parasitic capacitance has been significantly reduced. Therefore, according to the present invention, higher speed and higher integration of LSI can be achieved.
第１図は本発明の製造方法の最終段階の工程Ｍ、Ｎ、Ｏ
を示す図である。
第２図は本発明の製造方法の最初の工程Ａ、Ｂ、Ｃを示
す図である。
第３図は本発明の製造方法の途中の工程り、Ｄ、Ｅを示
す図である。
第４図は本発明の製造方法の途中の工程Ｅ、Ｆ、Ｇを示
す図である。
第５図は本発明の製造方法の途中の工程Ｇ、Ｈ１■を示
す図である。
第６図は本発明の製造方法の途中の工程Ｊ、Ｋ、Ｌを示
す図である。
第７図は従来のＬＯＧＯＳトランジスタとその改良トラ
ンジスタを示す図である。
１、・・・・Ｐ型基板
２、・・・・Ｐ＋チャンネルスト−／パー＋
３、・・・・Ｎ 埋込層 ４，４′・・・・酸化膜
５、・・・・Ｎ＋コレクタ取出し部
６、・・・・Ｎ型エピタキシャル層
７、・・・・ベース領域 ８．・・・・エミッタ領
域７゛・・・・グラフトベース領域
８、・・・・多結晶Ｓｉ １０．・・・・多結
晶５ｉＩ１．・・・・フォトレジスト １２．・・・・
ベース電極＋３．・・・・エミッタ電極 １４．・・
・・コレクタ電極２１、・・・・フォトレジスト ２２
．・・・・Ｓ＋０２ＪＩｉ２３、・・・・フォトレジス
トFigure 1 shows steps M, N, and O in the final stage of the manufacturing method of the present invention.
FIG. FIG. 2 is a diagram showing the first steps A, B, and C of the manufacturing method of the present invention. FIG. 3 is a diagram showing intermediate steps D and E of the manufacturing method of the present invention. FIG. 4 is a diagram showing steps E, F, and G in the middle of the manufacturing method of the present invention. FIG. 5 is a diagram showing steps G and H1 in the middle of the manufacturing method of the present invention. FIG. 6 is a diagram showing steps J, K, and L during the manufacturing method of the present invention. FIG. 7 is a diagram showing a conventional LOGOS transistor and its improved transistor. 1,...P-type substrate 2,...P+ channel strike-/par+ 3,...N buried layer 4,4'...oxide film 5,...N+ collector Extracting portion 6, N-type epitaxial layer 7, base region 8. ...Emitter region 7゛...Graft base region 8, ...Polycrystalline Si 10. ...Polycrystalline 5iI1. ...Photoresist 12.・・・・・・
Base electrode +3. ...Emitter electrode 14.・・・
...Collector electrode 21, ...Photoresist 22
．． ...S+02JIi23, ...Photoresist
Claims (1)
電極の端部によって該基板上に段差部を形成する工程と
、 上記段差部を含む上記半導体基板上に第１の半導体層と
耐酸化物層を形成した後、異方性エッチングを行なって
上記段差部側壁部に上記耐酸化物層を残す工程と、 上記第１の半導体層を酸化する工程と、 上記段差部の側壁部に残した上記耐酸化物を除去する工
程と、 上記耐酸化物層を除去した上記半導体基板の露出部を含
み、かつ、上記ベース電極に接続された不純物含有半導
体層を形成する工程と、 上記不純物含有半導体層により不純物を半導体基板に拡
散させる工程と、 上記不純物含有半導体層に接して、上記半導体基板にベ
ース領域を形成する工程と、 上記不純物含有半導体層とその表面に形成した絶縁層を
マスクとして、エミッタ領域を上記半導体基板に形成す
る工程 とを有する半導体装置の製造方法。(1) A step of forming a step portion on a semiconductor substrate by an end of a base electrode formed on the substrate via an insulating layer, and forming a first semiconductor layer and an acid-resistant layer on the semiconductor substrate including the step portion. After forming the compound layer, performing anisotropic etching to leave the oxide resistant layer on the side wall of the step, oxidizing the first semiconductor layer, and leaving the oxide resistant layer on the side wall of the step. a step of removing the oxidation resistant material; a step of forming an impurity-containing semiconductor layer including an exposed portion of the semiconductor substrate from which the oxidation resistant layer has been removed and connected to the base electrode; a step of diffusing impurities into a semiconductor substrate; a step of forming a base region in the semiconductor substrate in contact with the impurity-containing semiconductor layer; and a step of forming an emitter region using the impurity-containing semiconductor layer and an insulating layer formed on its surface as a mask. forming a semiconductor device on the semiconductor substrate.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11124985A JPS61269374A (en) | 1985-05-23 | 1985-05-23 | Manufacture of semiconductor device |
| US06/865,295 US4678537A (en) | 1985-05-23 | 1986-05-21 | Method of manufacturing semiconductor devices |
| EP86106981A EP0208877A3 (en) | 1985-05-23 | 1986-05-22 | Method of manufacturing semiconductor devices having connecting areas |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11124985A JPS61269374A (en) | 1985-05-23 | 1985-05-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61269374A true JPS61269374A (en) | 1986-11-28 |
Family
ID=14556380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11124985A Pending JPS61269374A (en) | 1985-05-23 | 1985-05-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61269374A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0258233A (en) * | 1988-08-23 | 1990-02-27 | Oki Electric Ind Co Ltd | Manufacture of bipolar transistor |
| US7611954B2 (en) | 2003-07-01 | 2009-11-03 | International Business Machines Corporation | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same |
| US8716096B2 (en) | 2011-12-13 | 2014-05-06 | International Business Machines Corporation | Self-aligned emitter-base in advanced BiCMOS technology |
-
1985
- 1985-05-23 JP JP11124985A patent/JPS61269374A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0258233A (en) * | 1988-08-23 | 1990-02-27 | Oki Electric Ind Co Ltd | Manufacture of bipolar transistor |
| US7611954B2 (en) | 2003-07-01 | 2009-11-03 | International Business Machines Corporation | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same |
| US8716096B2 (en) | 2011-12-13 | 2014-05-06 | International Business Machines Corporation | Self-aligned emitter-base in advanced BiCMOS technology |
| US8916952B2 (en) | 2011-12-13 | 2014-12-23 | International Business Machines Corporation | Self-aligned emitter-base in advanced BiCMOS technology |
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