JPS63261878A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the high speed operation of a transistor, by forming the following in the same distance; an emitter region boundary and the outer sidewall of an aperture for emitter lead-out part, the inner sidewall of an aperture for base lead-out part and the outer sidewall of the aperture for base lead-out part, and the outer boundary of an external base region. CONSTITUTION:By a selective etching in which a thermal oxide film 10 of polysilicon is applied to a mask, polysilicon 6 and a nitride film 5 are eliminated in order, and an aperture 11 for base lead-out part is formed. After the thermal oxide film 10 is eliminated, a sidewall 12 of polysilicon is formed by an anisotropic etching, and contact of the base is made. By applying a nitride film 14 on an N<+> epitaxial layer to a mask, polysilicon is selectively oxidized to form an insulating oxide film 15. In this case, an external base layer 13 is formed by diffusion from P<+> polysilicon. Finally, after the nitride film 14 is eliminated and an emitter lead-out part is opened, N<+> type polysilicon 16 containing P-type impurity is grown, and a P-type base layer 17 and an N-type emitter layer 18 are simultaneously formed, by diffusion from said polysilicon. Thereby, the high speed operation of a transistor is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which bipolar transistors are miniaturized and operated at high speed.

Prior Art FIG. 2 shows a cross-sectional structure of an NPN transistor according to the prior art. This device consists of a P-type silicon substrate 19. N-type buried collector layer 20. An N-type epitaxial layer 21 is provided, and parasitic capacitance is reduced by separating a thick LOGO8 film 22, a thermal oxide film 23, and an N-type collector all layer 24.
．． P-type base layer 25, furthermore, high concentration external base layer 26
The speed is increased by reducing the base resistance and emitter 28 formed by diffusion from N+ polysilicon 27. In addition, in the figure, an N-type collector contact layer 29. Wiring metal 30 is also shown.

Problems to be Solved by the Invention In such a conventional structure, since the positions of each diffusion layer and the opening are determined by mask alignment using photolithography, a margin for alignment is required. Alignment margins are required between the external base region and the emitter region, between the external base region and the base contact opening, between the ILOcO8 region and the external base region, etc., which leads to an increase in the area of each region and an increase in parasitic capacitance and base resistance. This occurs and hinders the speeding up of transistors.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a base drawer hole, an external base region, an emitter drawer hole,
It has a structure in which the intrinsic base region and emitter region are all formed in a self-aligned manner.

According to the semiconductor device of the present invention, there is no need for a mask alignment margin between each diffusion layer and each opening, making it possible to minimize each region.

Embodiment FIGS. 1A to 1E are cross-sectional views of an embodiment of the present invention in the order of steps, mainly showing the emitter and base portions.

First, as shown in FIG. 1A, an N-type buried collector layer 2 is formed in a P-type substrate 1, an N-type epitaxial layer 3 is grown, and a CO8 film 4 is formed. Furthermore, the nitride film 5
After growing P+ polysilicon, a P+ polysilicon layer is formed on the entire surface, and a region of the P+ polysilicon in which an emitter is to be formed in the N-type epitaxial layer 3 is selectively removed by etching to form a polysilicon layer that will become a base electrode. After growing a nitride film 7, a CVD oxide film is grown, and this is left on the step part of the P+ polysilicon layer by anisotropic etching to form a so-called sidewall 8. do.

Further, as shown in FIG. 1, the nitride film 7 is selectively etched away using the sidewall 8 as a mask, and after removing the sidewall 8, the nitride film 9 on the stepped portion of the P+ polysilicon layer is removed as a mask. Then, the P+ polysilicon layer is selectively thermally oxidized to form an oxide film 10.

After that, as shown in FIG. 1, after removing the nitride film 9, the 1τ polysilicon layer and the nitride film 5 are sequentially removed by selective etching using the polysilicon thermal oxide film 1o as a mask, and the base lead-out portion is etched. An opening 11 is formed.

Next, as shown in FIG. 1d, after removing the thermal oxide film 10,
Polysilicon is layered and grown again, and then polysilicon sidewalls 12 are formed by anisotropic etching.
form and make base contact. Further, while keeping the nitride film 14 on the N1 epitaxial layer as a mask, polysilicon is selectively oxidized to form an insulating oxide film 15. At this time, an external base layer 13 is formed by diffusion from P+ polysilicon.

Finally, as shown in FIG. 1e, after removing the nitride film 14 and opening an emitter lead-out portion, polysilicon 16 of N-type and containing P-type impurities is grown. A P type base layer 17 and an N type emitter layer 18 are simultaneously formed by diffusion from the substrate. As described above, in the structure of the present invention, the base lead-out opening, the external base region, the emitter lead-out opening, the intrinsic base region, and the emitter region are formed in a self-aligned manner.

Effects of the Invention ゛As explained above, according to the semiconductor device of the present invention, there is no need for a mask alignment margin between each diffusion layer and an opening, and each region can be minimized, and each parasitic Capacitance and base resistance can be reduced, and high-speed transistor operation is possible.

[Brief explanation of the drawing]

Figures 1a to 1e show the structure and embodiment of the present invention, with NPN
The cross-sectional structural diagram of a transistor is shown in the order of steps, and FIG. 2 is a structural cross-sectional diagram of a conventional example. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type buried collector layer, 3... N-type epitaxial layer, 4... Separated LOGO3 film, 5 ...Nitride film, 6...P+ polysilicon, 7...
・Nitride film, 8...CVD oxide film side film, 9...Nitride film, 10...Polysilicon thermal oxide film, 11...Base extraction part opening Hole, 12
...Polysilicon side wall, 13...
... External base layer, 14... Nitride film, 15.
...Polysilicon thermal oxide film, 16...N
+Polysilicon, 17...P-type base layer, 18
...N-type emitter layer. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1

Claims (1)

[Claims] An intrinsic base region formed on the surface of the semiconductor substrate, an extrinsic base region surrounding the intrinsic base region, and an insulating film on the substrate extending from the outer edge of the extrinsic base region to the outer edge of the substrate from above the extrinsic base region. an emitter lead-out part forming hole extending to the outer edge of the substrate, having an outer wall of the base lead-out part forming hole on the outer edge of the external base region, and having a side wall on the outer edge of the intrinsic base region; an emitter drawer formed on the emitter region so as to be in contact with the base drawer through an insulating film extending from a boundary between the base region and the emitter region in the base drawer opening; In the semiconductor device, the emitter region boundary, the outer wall of the emitter lead-out aperture, the inner wall of the base draw-out aperture, the outer wall of the base draw-out aperture, and the outer side of the external base region A semiconductor device characterized in that boundaries are formed at equal distances.