JPH0519822B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary semiconductor device.

[Technical background of the invention and its problems]

As a complementary semiconductor device, a C-MOS inverter in which a p-channel MOS transistor 1 and an n-channel MOS transistor 2 are connected as shown in FIG. 1 is conventionally known. This C-MOS inverter has a structure in which no steady current flows even when the output is at the H (high) level or the L (low) level, so it can be highly integrated without suffering from power consumption problems. It is seen as a promising basic element in the future as a basic element for configuring large-scale integrated circuits such as memory and logic.

FIG. 2 is a cross-sectional view showing a schematic structure of a C-MOS inverter. In the figure, 3 is an n-type Si substrate, and 4 is a p-type impurity region (hereinafter abbreviated as p-well).
A p-channel MOS transistor 1 consisting of source/drain regions 5 and 6 and a gate electrode 7 is formed in an n-type impurity region that is the surface layer of the substrate 3.
An n-channel MOS transistor 2 consisting of source/drain regions 8, 9 and a gate electrode is formed in the p-well 4. Further, between each of the above regions, an element isolation oxide film 11 having a thickness smaller than the depth of the p-well 4 is formed by, for example, the LOCOS method. With this structure, when the input is H, transistor 1 is OFF and transistor 2 is OFF.
When ON, the output becomes L; when the input is L, transistor 1 is ON; when transistor 2 is OFF, the output becomes H. In other words, whether the output is H or L, one of transistors 1 and 2 is
It will be OFF and no steady current will flow.

However, in this type of device, a peculiar phenomenon called latch-up occurs, and this latch-up is a major factor hindering higher integration. The latchup consists of the source 5 (p ⁺ region) of the p-channel MOS transistor 1, the n-type Si substrate 3,
A parasitic thyristor with a pnpn structure formed by the p-well and the source 8 of the n-channel transistor 2 is
This is a phenomenon in which the circuit turns on due to a trigger such as a substrate current. As a result, a large current flows within the element, which may even lead to destruction of the element. The above pnpn structure can be considered as the following two parasitic bipolar transistors. That is, a PNP type bipolar transistor A has the source 5 of the transistor 1 as the emitter, the substrate 3 as the base, and the p-well 4 as the collector, and the NPN type bipolar transistor A has the source 8 of the transistor 2 as the emitter, the p-well as the base, and the substrate 3 as the collector. It can be decomposed into type bipolar transistor B. If the current amplification factors of transistors A and B are β _PNP and β _NPN , respectively, the latch up is β _PNP ×
It is known that this occurs under the condition of β _NPN >1.
When an integrated circuit constituted by a C-MOS inverter is miniaturized for the purpose of increasing the degree of integration, the base width of the parasitic bipolar transistor becomes narrower, β becomes larger, and as a result, latch-up becomes more likely to occur. For this reason, it has been difficult to achieve high integration.

As one means to prevent latch-up, a structure has been proposed in which a p-type high concentration impurity region (p ⁺ region) 12 is provided at the bottom of the P well 4 as shown in FIG. 3a (International Electron Device
Meeting, 1978, p. 230). In this structure, the Gummel number in the base region of the NPN transistor B increases due to the presence of the p ⁺ region 12,
β _NPN decreases. As a result, the occurrence of latch-up can be suppressed to some extent. however,
It is not possible to completely prevent the occurrence of latchups. In other words, the path of the collector current of NPN transistor B is as shown by the arrow in Figure 3a.
There are two types of routes: a route 13 that passes through the p ⁺ area 12 and a route 14 that does not pass through the p ⁺ area. In the path 13, a considerable number of electrons attempting to flow into the n-type Si substrate 3, which is the collector, causes recombination in the p ⁺ region 12 and becomes a base current, reducing β _NPN .
In addition, in the path 14, the electrons flow into the n-type Si substrate 3 without recombining, so β _NPN
does not contribute in any way to the decline in Therefore, it has been difficult to sufficiently suppress latch up.

On the other hand, as another method for preventing latch-up, recently, as shown in FIG.
A structure has been proposed in which the thickness of the NPN transistor B is made larger than the depth (5 to 7 μm) of the p-well 4, thereby increasing the effective base width of the NPN transistor B and reducing the β _NPN (43rd Japan Society of Applied Physics Proceedings of an academic conference, 1982, 30P-Q-5). However, with this structure, it is not possible to block the current passing through the path 13 shown in FIG. 3a, and the effective amount of increase in the base width cannot be increased very much. In other words, it is difficult to sufficiently suppress latch-up. Further, it is technically extremely difficult to form an embedded oxide film 15 with a thickness exceeding 5 to 7 [μm], and this method is impractical.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a complementary semiconductor device that can reliably prevent latch-up and has a structure suitable for high integration.

[Summary of the invention]

The gist of the present invention is to simultaneously inhibit both current paths 13 and 14 shown in FIG. 3a, thereby significantly expanding the effective base width of the parasitic transistor.

That is, the present invention provides a method for manufacturing a complementary semiconductor device in which p-channel and n-channel MIS transistors are formed on the surface of a first conductivity type semiconductor substrate, in which a second conductivity type high-density transistor is formed on the surface layer of the first conductivity type semiconductor substrate. After selectively forming the impurity concentration region, an epitaxial layer is grown on the substrate, and a low concentration impurity region (well) of the second conductivity type consisting of the epitaxial layer is grown on the high concentration impurity region of the second conductivity type. )
, a first conductivity type low concentration impurity region (well) made of the epitaxial layer is formed adjacent to this, and then a second conductivity type high concentration impurity region is formed between each region of the epitaxial layer. In this method, an isolation trench is formed and then an element isolation insulating film is buried in the trench.

The present invention also provides a method for manufacturing a complementary semiconductor device in which p-channel and n-channel MIS transistors are formed on the surface of a first conductivity type semiconductor substrate, including:
After selectively forming a first conductivity type high concentration impurity region and a second conductivity type high concentration impurity region in the surface layer of the first conductivity type semiconductor substrate, an epitaxial layer is grown on the substrate to form a second conductivity type semiconductor substrate. A low concentration impurity region (well) of the second conductivity type made of the epitaxial layer is placed on the high concentration impurity region of the mold, and a low concentration impurity region (well) of the first conductivity type made of the epitaxial layer is placed on the high concentration impurity region of the first conductivity type. A low concentration impurity region (well) is formed, then an element isolation trench reaching each high concentration impurity region is formed between each region of the epitaxial layer, and then an element isolation insulating film is buried in this trench. This is the method.

〔Effect of the invention〕

According to the present invention, due to the effects of the element isolation insulating film and the second conductivity type high concentration impurity region, the collector current of the parasitic transistor must necessarily pass through the impurity region, and most of the electrons are transferred to this impurity region. As a result, the effective base width of the parasitic transistor increases. For this reason,
β _NPN or β _PNP becomes significantly smaller, and the occurrence of latchup can be reliably prevented. Furthermore, the thickness of the insulating film buried in each of the first and second conductivity type regions may be smaller than the depth of the second conductivity type region. For this reason, the thickness of the insulating film is set to 1 to 2 [μm].
It can be made small and the insulating film can be easily formed. In addition, when a high concentration impurity region is formed under each region of the first and second conductivity type, the expansion of the base width becomes more remarkable, and β _NPN and β _PNP can be significantly reduced. Effects such as being able to prevent occurrence more reliably can be obtained.

Further, according to the present invention, since the p-well and n-well as low concentration impurity regions are formed by epitaxial layers, the carrier concentration of the high concentration impurity region and the low concentration impurity region (well) can be controlled independently. This can contribute to improving device characteristics.

[Embodiments of the invention]

FIG. 4 shows a C-MOS according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a schematic configuration of an inverter. n-type
A p-well (second conductivity type region) 22 is formed in a part of the surface layer of the Si substrate (first conductivity type semiconductor substrate) 21. An oxide film (insulating film for element isolation) 24 is buried between the first conductivity type region) 23 and the first conductivity type region) 23. A p ⁺ layer (high concentration impurity) 25 containing impurities at a higher concentration than that of the well 22 is formed below the p well 22 , and a part of the upper surface of this p ⁺ layer 25 is formed under the oxide film 24 . It has come into contact with P ⁺ layers 26 and 27 forming source/drain regions are formed in the n-type region 23, and a gate electrode 28 is formed on the n-type region 23 via a gate oxide film (not shown). A p channel is formed from these p ⁺ layers 26, 27 and gate electrode 28.
A MOS transistor is configured. In addition, the p-well 22 and its upper surface are provided with a source as well as the above.
N ⁺ layers 29 and 30 forming the drain region and a gate electrode 31 are formed, and an n channel is formed from these.
A MOS transistor is configured. The C-MOS inverter shown in FIG. 1 is constructed by commonly connecting the p ⁺ layer 27 and the n ⁺ layer 30 that form the drain, and also connecting the gate electrodes 28 and 31 in common. It's summery.

Next, a method for manufacturing the C-MOS inverter having the above configuration will be described. First, as shown in FIG. 5a, an n-type (100) Si substrate 21 with a specific resistance of 1 [Ωcm] is
Using ion implantation technology, the implantation amount was 1×10 ¹⁵ [cm ^-3 ]
Selectively add boron under the conditions of p ⁺ region 25
form. Next, using a vapor phase epitaxial growth technique, the resistivity was reduced to 4 [Ωcm] as shown in Figure 5b.
An n-type epitaxial layer 41 is grown to a thickness of 1.5 [μm]. After that, as shown in Figure 5c,
Using the CVD oxide film 42 as a mask, the epitaxial layer 41 is selectively etched. Next, boron ions are implanted into the sidewalls of the epitaxial layer 41' on the p ⁺ region 25 using exposure technology and ion implantation technology. In the same manner, arsenic ions are implanted into the sidewalls of the remaining epitaxial layer 41''.Subsequently,
After removing the CVD oxide film 32, boron ions are implanted into the surface of the epitaxial layer 41'. As a result, as shown in FIG. 5d, the epitaxial layer 41' on the p ⁺ region is converted into a p-type layer, that is, the p-well 22 is formed, and the n-type region is formed from the remaining epitaxial layer 41''. It is formed.

Here, the p-well 22 is formed by converting the n-layer into a p-layer by p-type ion implantation, but since the carrier concentration of the n-layer is low, the carrier concentration of the p-layer can be set with good controllability by p-conversion. I can do it. This is extremely important for determining the transistor threshold. Next, using an oxide film burying technique, an oxide film 24 is buried between the p well 22 and the n type region 23 as shown in FIG. 5e. Thereafter, the structure shown in FIG. 4 is realized by forming source/drain regions, gate electrodes, etc. using well-known techniques.

In the C-MOS inverter manufactured in this way, the mi)return carrier that is injected from the source 29 of the n-channel MOS transistor into the p-well 22 and tries to flow into the substrate 21 is always
must pass through the p ⁺ region 25, and most minority carriers recombine in this p ⁺ region.
Therefore, β _NPN of the NPN bipolar transistor (parasitic transistor) consisting of the source 29, p-well 22, substrate 21, etc. is significantly reduced. As a result, the occurrence of latch-up can be reliably prevented. In particular, when the impurity concentration of the p ⁺ region 25 exceeded 1×10 ¹⁷ [cm ^-3 ], the above-mentioned recombination occurred significantly and was effective in preventing latchup. Further, in the structure of this embodiment, the thickness of the buried insulating film 24 can be relatively small at 1.5 [μm], which has the advantage that the insulating film 24 can be easily formed.

In addition, the p-well 22 is formed independently of the high-concentration p ⁺ layer 25 and is formed by converting an n-type epitaxial layer with a low carrier concentration into a p ^- layer by ion implantation. In addition to making the impurity concentration sufficiently high, the carrier concentration of the p-well 22 can be set with good controllability, and latch-up can be reliably prevented and transistor characteristics can be improved.

FIG. 6 is a sectional view showing a schematic configuration of a C-MOS inverter according to another embodiment. In addition, the fourth
The same parts as those in the figures are given the same reference numerals, and detailed explanation thereof will be omitted. This embodiment differs from the previously described embodiments in that a high concentration impurity layer is formed not only under the p-well 22 but also under the p-well 22 and the n-type region 23. That is,
A p ⁺ region 25 is formed under the p well 22 as in the previous embodiment, and an n ⁺ region 51 is formed under the n type region 23. And n ⁺
Similar to the p ⁺ region 25, the region 51 has a portion of its upper surface in contact with the insulating film 24. In addition, in order to realize the above structure, boron and arsenic are selectively implanted into the surface of the n-type Si substrate 21 as shown in FIG. 7 in the step of FIG. 5a shown in the previous embodiment. What is necessary is to form the p ⁺ region 25 and the n ⁺ region 51.

Of course, even with such a configuration, the same effects as in the previous embodiment can be obtained. Further, in this embodiment, due to the existence of the n ⁺ region 51, the source 26 of the p-channel MOS transistor and the n-type region 2
β _PNP of a PNP bipolar transistor (parasitic transistor) consisting of P-well 22 and P-well 22 can also be significantly reduced. Therefore, it is possible to more reliably prevent the occurrence of latch-up.

Note that the present invention is not limited to the embodiments described above. For example, the high concentration impurity regions (p ⁺ region 25, n ⁺ region 51) may be formed as shown in FIGS. 8a to 8e. 8a shows an example in which a part of the upper surface and a part of the side surface of the high concentration impurity region 25 are in contact with the element isolation insulating film 24, and in FIG. 8b, the side surface of the high concentration impurity region 25 is in contact with the insulating film Figure c is an example in which a part of the upper surface of the high concentration impurity region 25 is in contact with the entire lower part of the insulating film 24. In other words, the high concentration impurity layer may be one in which a portion thereof is in contact with the element isolation insulating film. Also, the conductivity type of the semiconductor substrate is n
Of course, it is not limited to the type, and may be p-type. Furthermore, as a semiconductor substrate,
It is also possible to use a semiconductor film formed on an insulating film such as SiO ₂ . Further, the impurity concentration of the high concentration impurity region may be determined as appropriate according to specifications. In addition, without departing from the gist of the present invention,
Various modifications can be made.

[Brief explanation of the drawing]

Figures 1 and 2 are respectively conventional C-MOS
Figure 1 is an equivalent circuit diagram, Figure 2 is a cross-sectional view of the structure, Figures 3a and b are cross-sectional views showing the schematic structure of a conventional device with an improved latch-up, and Figure 4 is a cross-sectional view to explain the inverter. The figure is a sectional view showing a schematic structure of an embodiment of the present invention, FIGS. 5 a to 5 e are process sectional views for explaining the above embodiment, and FIG. , FIG. 7 is a sectional view for explaining the other embodiment, and FIGS. 8 a to 8 e are sectional views for explaining modified examples. 21... n-type Si substrate (first conductivity type semiconductor substrate),
22...p well (second conductivity type region), 23...
n-type region (first conductivity type region), 24... oxide film (insulating film for element isolation), 25... p ⁺ region (high concentration impurity region), 26, 27... p ⁺ region (source/
drain region), 28, 31...gate electrode, 2
9, 30...n ⁺ region (source/drain region),
41...n-type epitaxial layer, 42...CVD
Oxide film, 51...n ⁺ region (high concentration impurity region).

Claims (1)

[Scope of Claims] 1. A method for manufacturing a complementary semiconductor device in which p-channel and n-channel MIS transistors are formed on the surface of a first conductivity type semiconductor substrate, wherein a second conductivity type is formed on the surface layer of the first conductivity type semiconductor substrate. selectively forming a high concentration impurity region on the substrate, growing an epitaxial layer on the substrate, and depositing a second conductivity type low concentration impurity formed on the epitaxial layer on the second conductivity type high concentration impurity region; forming a low concentration impurity region of a first conductivity type made of the epitaxial layer adjacent to the region; and reaching a high concentration impurity region of the second conductivity type between each region of the epitaxial layer. 1. A method for manufacturing a complementary semiconductor device, comprising the steps of: forming an element isolation trench; and filling the trench with an element isolation insulating film. 2 the first and second layers comprising the epitaxial layer;
In the step of forming a low concentration impurity region of a conductivity type, after epitaxially growing a low concentration impurity region of a first conductivity type on the substrate, the epitaxial layer on the high concentration impurity region of a second conductivity type is grown using ions. 2. The method of manufacturing a complementary semiconductor device according to claim 1, wherein the region is converted into a low concentration impurity region of a second conductivity type by implantation. 3. In a method for manufacturing a complementary semiconductor device in which p-channel and n-channel MIS transistors are formed on a surface of a first conductivity type semiconductor substrate, a first conductivity type high concentration impurity region is formed in a surface layer of the first conductivity type semiconductor substrate. selectively forming a second conductivity type high concentration impurity region; and growing an epitaxial layer on the substrate, and forming a second conductivity type high concentration impurity region on the second conductivity type high concentration impurity region. forming a first conductivity type low concentration impurity region of the epitaxial layer on the first conductivity type high concentration impurity region; 1. A method for manufacturing a complementary semiconductor device, comprising the steps of: forming a trench for element isolation reaching a concentration impurity region; and filling the trench with an insulating film for element isolation. 4 the first and second layers comprising the epitaxial layer;
In the step of forming a low concentration impurity region of a conductivity type, after epitaxially growing a low concentration impurity region of a first conductivity type on the substrate, the epitaxial layer on the high concentration impurity region of a second conductivity type is grown using ions. 4. The method of manufacturing a complementary semiconductor device according to claim 3, wherein the region is converted into a low concentration impurity region of the second conductivity type by implantation.