CN114496792A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114496792A
CN114496792A CN202011265509.0A CN202011265509A CN114496792A CN 114496792 A CN114496792 A CN 114496792A CN 202011265509 A CN202011265509 A CN 202011265509A CN 114496792 A CN114496792 A CN 114496792A
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CN
China
Prior art keywords
layer
forming
isolation
semiconductor structure
channel
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CN202011265509.0A
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Chinese (zh)
Inventor
苏博
吴汉洙
施雪捷
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011265509.0A priority Critical patent/CN114496792A/en
Publication of CN114496792A publication Critical patent/CN114496792A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first area and a first fin part positioned on the surface of the first area; forming an isolation prefabricated layer on the surface of the substrate, wherein the isolation prefabricated layer is also positioned on the side wall of the first fin part; etching the first fin part, forming a plurality of openings in the isolation prefabricated layer, and exposing the isolation prefabricated layer from the side walls of the openings; forming a barrier layer on the sidewall of the opening; and forming a channel layer in the opening. The channel layer is formed by growing the channel layer material at the bottom of the opening without forming a channel material layer and then etching, so that the stress of the channel layer is determined by the growth of the material, the stress release condition caused by subsequent etching is avoided, the stress of the channel layer is maintained, the improvement of the mobility of the current carrier of the channel layer is not influenced, and the performance of the device is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
As the semiconductor process is further developed, the feature size of the transistor is reduced to the nanometer scale, and the scaling technique faces more and more serious challenges, such as: mobility degradation, source-drain punch-through leakage, hot carrier effects, etc. Wherein mobility degradation is a major difficulty affecting the speed increase of integrated circuits. By improving the mobility of carriers in the channel, the mobility degradation caused by factors such as coulomb interaction caused by high doping of the channel, effective electric field intensity improvement caused by thinning of a gate medium, interface scattering enhancement and the like can be compensated.
The strained silicon technology introduces strain, i.e., stress change, to the channel layer in terms of device structure and material design to change the lattice structure of the channel layer substrate, thereby increasing the mobility of the channel layer carriers and achieving the purpose of improving device performance. The direct epitaxial growth of channel materials with stress on the channel layer is a trend. Germanium-silicon materials have become a hotspot for research on novel channel materials due to the characteristics of higher carrier mobility, higher device reliability, compatibility with the existing silicon-based process and the like.
The technology of sige channel devices is still in need of improvement.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the formed semiconductor structure.
In order to solve the above technical problem, a method for forming a semiconductor structure is provided, which includes: providing a substrate, wherein the substrate comprises a first area and a first fin part positioned on the surface of the first area; forming an isolation prefabricated layer on the surface of the substrate, wherein the isolation prefabricated layer is also positioned on the side wall of the first fin part; etching the first fin part, forming a plurality of openings in the isolation prefabricated layer, and exposing the isolation prefabricated layer from the side walls of the openings; forming a barrier layer on the sidewall of the opening; and forming a channel layer in the opening.
Optionally, the material of the barrier layer includes silicon nitride.
Optionally, the barrier layer has a thickness in a range from 5 angstroms to 20 angstroms.
Optionally, the method for forming the barrier layer includes: forming a barrier material layer on the side wall and the bottom surface of the opening and the surface of the isolation prefabricated layer; and etching back the barrier material layer until the first fin part at the bottom of the opening is exposed so as to remove the barrier material layer at the bottom of the opening.
Optionally, the forming process of the barrier material layer includes an atomic layer deposition process.
Optionally, the parameters of the etching process for etching back the barrier material layer include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 to 2.5 degrees.
Optionally, after the channel layer is formed, the isolation prefabricated layer is etched to expose the top and a part of the sidewall of the channel layer, so as to form an initial isolation layer, where the top of the initial isolation layer is lower than the top of the channel layer and higher than or equal to the bottom of the channel layer.
Optionally, after the forming the initial isolation layer, the method further includes: and annealing the initial isolation layer to form the isolation layer.
Optionally, the annealing process includes a water vapor annealing process.
Optionally, the parameters of the annealing process include: the gases used include oxygen/ozone and gaseous water, and the annealing temperature ranges from 350 ℃ to 750 ℃.
Optionally, the material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Optionally, the substrate further includes a second region and a second fin portion located on a surface of the second region.
Optionally, after forming the channel layer and before forming the initial isolation layer, the method further includes: planarizing the isolation pre-formed layer, the channel layer until the channel layer is flush with the second fin top surface.
Optionally, the method further includes: the initial isolation layer is also located on the side wall of the second fin portion and exposes the top of the second fin portion and part of the side wall.
Optionally, after forming the initial isolation layer and before forming the isolation layer, the method further includes: modifying the channel layer and the second fin portion exposed by the initial isolation layer to enable the channel layer exposed by the initial isolation layer and the second fin portion exposed by the initial isolation layer to have the same size in the direction parallel to the substrate and in the direction perpendicular to the substrate.
Optionally, a selection ratio of the process of modifying the channel layer and the second fin portion exposed by the initial isolation layer to the channel layer and the second fin portion ranges from 1:3 to 1: 8.
Optionally, after the forming the initial isolation layer, before etching the channel layer and the second fin portion exposed by the initial isolation layer, the method further includes: and removing the barrier layer.
Optionally, a hard mask layer is further disposed on top surfaces of the first fin portion and the second fin portion.
Optionally, before forming the opening, the method further includes: and removing the hard mask layer on the first area.
Optionally, the method for removing the hard mask layer on the first region includes: forming a graphical layer on the surface of the isolation prefabricated layer, wherein the graphical layer exposes the isolation prefabricated layer on the first area and the top surface of the hard mask layer; etching the hard mask layer on the first area to expose the top surface of the first fin part; and removing the patterning layer after removing the hard mask layer on the first area.
Optionally, the method further includes: and forming a covering layer on the surface of the exposed channel layer.
Optionally, the material of the cover layer comprises silicon.
Optionally, the process of forming the channel layer includes an epitaxial growth process.
Optionally, the method for forming the isolation preform layer includes: and forming a dielectric material layer on the surface of the substrate, and flattening the dielectric material layer until the top surface of the first fin part is exposed to form the isolation prefabricated layer.
Optionally, the process parameters for forming the isolation preform layer include: the gas used comprises NH3And (SiH)3)3N，NH3The flow rate of (SiH) is 1sccm to 1000sccm3)3The flow rate of N is 3sccm to 8 sccm00sccm at a temperature of 50 ℃ to 100 ℃.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure, provided by the technical scheme of the invention, the first fin part is etched, a plurality of openings are formed in the isolation prefabricated layer, the isolation prefabricated layer is exposed from the side wall of each opening, and the channel layer is formed in each opening.
Drawings
Fig. 1-2 are cross-sectional views illustrating a semiconductor structure formation process.
FIGS. 3-10 are schematic structural views illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 11 to 20 are schematic structural views of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
As described in the background art, the performance of a semiconductor structure formed by using the existing sige channel device technology needs to be improved. An illustrative analysis will now be described in connection with a semiconductor structure.
Fig. 1-2 are cross-sectional views illustrating a semiconductor structure formation process.
Referring to fig. 1, a substrate 101 is provided; forming a channel material layer 102 on the substrate 101; a patterned layer 103 is formed on the channel material layer 102, and the patterned layer 103 exposes a portion of the surface of the channel material layer 102.
Referring to fig. 2, the patterned layer 103 is used as a mask to etch the channel material layer 101 and the substrate 101, so as to form a fin 104 and a bottom structure 105 located between the fin 104 and the substrate 101.
In the above method, the fin portion 104 is used to form a channel of a sige channel device, the fin portion 104 is located on the bottom structure layer 105, the fin portion 104 is made of a sige material, the bottom structure layer 105 is made of silicon, and due to lattice mismatch between ge and silicon, compressive stress is generated on the fin portion 104, which can reduce the effective quality of conductance of a hole in the channel direction and improve the speed of the PMOS device. In the process of forming the fin portion 104, the channel material layer 101 is etched, which may cause partial release of stress generated in the channel material layer 101, so that stress obtained by a finally formed channel is greatly reduced, thereby limiting improvement of channel carrier mobility and affecting device performance.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, the first fin portion is etched, a plurality of openings are formed in the isolation prefabricated layer, the isolation prefabricated layer is exposed from the side wall of each opening, and a channel layer is formed in each opening.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 3, a substrate is provided, which includes a first region i and a first fin 201 on a surface of the first region i.
The substrate can be made of monocrystalline silicon, polycrystalline silicon or amorphous silicon, can also be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide and the like, and can also be of a semiconductor-on-insulator structure. In this embodiment, the substrate is made of monocrystalline silicon.
The material of the first fin 201 includes silicon. In this embodiment, the first fin portion 201 is made of monocrystalline silicon, and in other embodiments, the first fin portion 201 may also be made of polycrystalline silicon, amorphous carbon, or the like.
In this embodiment, a hard mask layer 202 is further disposed on the top surface of the first fin 201.
The hard mask layer 202 is made of a material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the hard mask layer 202 is made of silicon nitride.
The method for forming the first fin portion 201 includes: forming a patterned hard mask layer 202 on the surface of the substrate, wherein the hard mask layer 202 exposes a part of the surface of the substrate; and etching the substrate by taking the hard mask layer 202 as a mask to form the first area I and a first fin part 201 on the surface of the first area I.
Referring to fig. 4, an isolation pre-fabricated layer 203 is formed on the surface of the substrate, and the isolation pre-fabricated layer 203 is also located on the sidewalls of the first fin 201.
The method for forming the isolation preform layer 203 comprises the following steps: a dielectric material layer (not shown) is formed on the surface of the substrate, and the dielectric material layer is planarized until the top surface of the first fin 201 is exposed, so as to form the isolation pre-fabricated layer 203. In this embodiment, the isolation pre-fabricated layer 203 is also located on the sidewall of the hard mask layer 202. Specifically, the dielectric material layer is planarized until the top surface of the hard mask layer 202 on the top of the first fin 201 is exposed.
The process parameters for forming the isolation pre-fabricated layer 203 include: the gas used comprises NH3And (SiH)3)3N，NH3The flow rate of (SiH) is 1sccm to 1000sccm3)3The flow rate of N is 3sccm to 800sccm, and the temperature is 50 ℃ to 100 ℃.
In this embodiment, the process of forming the isolation pre-fabricated layer 203 is a fluid chemical vapor deposition process that does not include an annealing process. The isolation pre-layer 203 is used for the subsequent formation of an initial isolation layer, which is used for the formation of an isolation layer, which is used for electrical isolation between different devices. In order to form the isolation layer, the initial isolation layer formed by the isolation prefabricated layer 203 is subsequently annealed, but the annealing is not performed in the process of forming the isolation prefabricated layer 203, so as to reduce the times of annealing, reduce the ion diffusion in the structure (such as a deep well region) formed before the process step, reduce the adverse effect of the ion diffusion on the device, and improve the performance of the device.
Referring to fig. 5, the first fin 202 is etched, a plurality of openings 204 are formed in the isolation preform layer 203, and sidewalls of the openings 204 expose the isolation preform layer 203.
The process of etching the first fin portion 202 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the first fin portion 202 is a dry etching process. The process parameters for etching the first fin portion 202 include: the etching gas comprises HBr and Cl2The power of the etching machine is 100w to 1000w, the pressure in the etching chamber is 2mTorr to 20mTorr, the flow rate of hydrogen bromide is 10sccm to 500sccm, and the flow rate of chlorine is 10sccm to 500 sccm. The dry etching process facilitates the formation of a better shaped opening.
Before forming the opening 204, the method further comprises: the hard mask layer 202 on the first area i is removed.
The process of removing the hard mask layer 202 on the first region includes one of dry etching and wet etching. In this embodiment, the process of removing the hard mask layer 202 on the first region is a wet etching process. The process parameters for removing the hard mask layer 202 in the first region include: the chemical liquid medicine is hot phosphoric acid with the concentration (volume fraction) of 60-95%, and the temperature range is 155-165 ℃. Because the hot phosphoric acid has a larger etching selectivity to the silicon nitride, the wet etching process has a larger selection ratio to the hard mask layer 202 and the isolation prefabricated layer 203, so that the hard mask layer 202 can be removed easily, and the isolation prefabricated layer 203 is damaged less.
Subsequently, a barrier layer is formed on the sidewall of the opening 204, and the method for forming the barrier layer is shown in fig. 6 to fig. 7.
Referring to fig. 6, a barrier material layer 205 is formed on the sidewall and bottom surface of the opening 204 and the surface of the isolation pre-fabricated layer 203.
The formation process of the barrier material layer 205 includes an atomic layer deposition process. In this embodiment, the forming process of the blocking material layer 205 is an atomic layer deposition process, and in other embodiments, the forming process may be another chemical vapor deposition process or a physical vapor deposition process. The atomic layer deposition process has good step coverage rate, and is beneficial to forming a film with uniform thickness.
The material of the barrier material layer 205 comprises silicon nitride; the barrier material layer 205 has a thickness in the range of 5 angstroms to 20 angstroms. The barrier material layer 205 is used for the subsequent formation of a barrier layer. In this embodiment, the material of the blocking material layer 205 is silicon nitride.
Referring to fig. 7, the blocking material layer 205 is etched back until the first fin portion 201 at the bottom of the opening 204 is exposed, so as to remove the blocking material layer 205 at the bottom of the opening 204.
In this embodiment, the method for forming the barrier layer 206 further includes: the barrier material layer 205 is etched back until the surface of the isolation pre-layer 203 is exposed.
The material of the barrier layer 206 comprises silicon nitride; the barrier layer has a thickness in the range of 5 angstroms to 20 angstroms. The material and thickness of the barrier layer 206 are determined by the barrier material layer 205. In this embodiment, the material of the barrier layer 206 is silicon nitride.
The barrier layer 206 is used for subsequently blocking the growth of the channel layer material on the sidewall, so that the channel layer material is epitaxially grown only from the first fin portion 201 at the bottom of the opening 204, the lateral growth of the channel layer material is inhibited, and the channel layer with a smooth surface is favorably formed.
The parameters of the etching process for etching back the barrier material layer 205 include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 to 2.5 degrees. Because the included angle between the incident direction of the ions and the normal direction of the substrate is small, the barrier material layer 205 at the bottom of the opening 204 and on the surface of the isolation pre-fabricated layer 203 can be removed, and the damage to the barrier layer 206 is reduced.
Referring to fig. 8, a channel layer 207 is formed in the opening 204.
The material of the channel layer 207 includes silicon germanium.
The process of forming the channel layer 207 includes an epitaxial growth process. In this embodiment, the process of forming the channel layer 207 is an epitaxial growth process. The technological parameters of the epitaxial growth process comprise: the reaction gas comprises SiH4、GeH4And H2The SiH4The flow rate of the GeH is in a range of 110sccm to 130sccm4The flow rate of (c) is in the range of 95sccm to 115sccm, and (H) is2The flow rate of (1) is in the range of 25slm to 35slm, and the gas pressure is in the range of 95 to 105 Torr.
The channel layer 207 is used to subsequently form a channel of a device. The channel layer 207 is formed by growing a channel layer material at the bottom of the opening, and is not required to be obtained by forming a channel material layer firstly and then etching, so that the stress of the channel layer is determined by the growth of the material, the stress release condition caused by subsequent etching cannot be generated, the stress of the channel layer is maintained, the improvement of the mobility of a current carrier of the channel layer is not influenced, and the performance of a device is improved.
The channel layer 207 is made of germanium-silicon, the substrate is made of silicon, and due to lattice mismatch of germanium and silicon, compressive stress is generated on the channel layer 207, so that the effective conductance quality of holes in the channel direction can be reduced by the compressive stress, and the speed of a PMOS (P-channel metal oxide semiconductor) device is improved.
Referring to fig. 9, after the channel layer 207 is formed, the isolation pre-fabricated layer 203 is etched to expose the top and a portion of the sidewall of the channel layer 207, so as to form an initial isolation layer 208, where the top of the initial isolation layer 208 is lower than the top of the channel layer 207 and higher than or equal to the bottom of the channel layer 207.
Etching the isolationThe process of the pre-fabricated layer 203 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the isolation pre-fabricated layer 203 is a dry etching process. The process parameters for etching the isolation pre-fabricated layer 203 include: the etching gas comprises HBr and Cl2The power of the etching machine is 100w to 1000w, the pressure in the etching chamber is 2mTorr to 20mTorr, the flow rate of hydrogen bromide is 10sccm to 500sccm, and the flow rate of chlorine is 10sccm to 500 sccm.
In this embodiment, the method further includes: the barrier layer 206 is removed.
The process of removing the barrier layer 206 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of removing the barrier layer 206 is a wet etching process. The process parameters for removing the barrier layer 206 include: the chemical liquid medicine is hot phosphoric acid with the concentration (volume fraction) of 60-95%, and the temperature range is 155-165 ℃. Because hot phosphoric acid has a larger etching selectivity to silicon nitride, the process for removing the barrier layer 206 has a larger selection ratio to the barrier layer 206 and the initial isolation layer 208, and has a larger selection ratio to the barrier layer 206 and the fin 201, which is beneficial to removing the barrier layer 206, and has less damage to the initial isolation layer 208 and the fin 201.
Referring to fig. 10, a capping layer 209 is formed on the exposed surface of the channel layer 207.
The material of the capping layer 209 comprises silicon. The material of the contact surface of the covering layer 209 and the channel layer 207 is silicon or silicon nitride material, the covering layer 209 may be a single-layer structure, and the material thereof may be silicon or SiN; the capping layer 209 may also be a multilayer structure, such as Si/SiO2/SiN or SiN/SiO2Three-layer structure of/SiN.
The capping layer 209 is used to protect the channel layer 207 from being oxidized, and may also be used to form a gate dielectric layer in a gate structure formation process through a subsequent oxidation process.
After the initial isolation layer 209 is formed, the method further includes: the initial isolation layer 209 is annealed to form an isolation layer.
The material of the isolating layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
The annealing treatment process comprises a water vapor annealing process, and the parameters of the annealing treatment process comprise: the gases used include oxygen/ozone and gaseous water, and the annealing temperature ranges from 350 ℃ to 750 ℃.
The annealing treatment is used for forming an insulating medium layer on the initial isolation layer 209 and also used for eliminating stress generated in the forming process of the channel layer 207, so that the performance of the device is improved. On the other hand, the number of annealing treatments is also reduced, for the reason and purpose, please refer to the process description of forming the isolation pre-fabricated layer 203, which is not described herein again.
Fig. 11 to 20 are schematic structural views of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
Referring to fig. 11, a substrate is provided, which includes a first region i, a first fin 301 on a surface of the first region i, a second region ii, and a second fin 302 on a surface of the second region ii.
The substrate can be made of monocrystalline silicon, polycrystalline silicon or amorphous silicon, can also be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide and the like, and can also be of a semiconductor-on-insulator structure. In this embodiment, the substrate is made of monocrystalline silicon.
The material of the first fin portion 301 comprises silicon; the material 302 of the second fin includes silicon. In this embodiment, the first fin portion 301 and the second fin portion 302 are made of monocrystalline silicon, and in other embodiments, the first fin portion 301 and the first fin portion 301 may also be made of polycrystalline silicon, amorphous carbon, or the like.
In this embodiment, a hard mask layer 303 is further disposed on the top surfaces of the first fin portion 301 and the second fin portion 302.
The hard mask layer 303 is made of one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the hard mask layer 303 is made of silicon nitride.
The method for forming the first fin portion 301 and the second fin portion 302 includes: forming a patterned hard mask layer 303 on the surface of the substrate, wherein the hard mask layer 303 exposes a part of the surface of the substrate; and etching the substrate by taking the hard mask layer 303 as a mask to form the first fin portion 301 located in the first area I and the second fin portion 302 located in the second area II.
Referring to fig. 12, an isolation pre-fabricated layer 304 is formed on the surface of the substrate, wherein the isolation pre-fabricated layer 304 is also located on the sidewalls of the first fin 301 and the sidewalls of the second fin 302.
The method for forming the isolation preform layer 304 comprises the following steps: forming a dielectric material layer (not shown) on the surface of the substrate, and planarizing the dielectric material layer until the top surfaces of the first fin 301 and the second fin 302 are exposed, thereby forming the isolation preform layer 304. In this embodiment, the isolation pre-fabricated layer 304 is also located on the sidewall of the hard mask layer 303. Specifically, the dielectric material layer is planarized until the top surface of the hard mask layer 303 is exposed.
The process parameters for forming the isolation pre-fabricated layer 304 include: the gas used comprises NH3And (SiH)3)3N，NH3The flow rate of (SiH) is 1sccm to 1000sccm3)3The flow rate of N is 3sccm to 800sccm, and the temperature is 50 ℃ to 100 ℃.
In this embodiment, the process of forming the isolation preform layer 304 is a fluid chemical vapor deposition process that does not include an annealing process. The isolation pre-layer 304 is used to subsequently form an initial isolation layer used to form an isolation layer used to electrically isolate different devices. In order to form the isolation layer, the initial isolation layer formed by the isolation prefabricated layer 304 is subsequently annealed, but the annealing is not performed in the process of forming the isolation prefabricated layer 304, so as to reduce the times of annealing, reduce the ion diffusion in the structure (such as the deep well region) formed before the process step, reduce the adverse effect of the ion diffusion on the device, and improve the performance of the device.
Subsequently, etching the first fin portion 301, and forming a plurality of openings in the isolation preform layer 304, before forming the openings, the method further includes: the hard mask layer 303 on the first region is removed. Please refer to fig. 13 for a method of removing the hard mask layer 303 in the first region.
Referring to fig. 13, a patterned layer 305 is formed on the surface of the isolation pre-fabricated layer 304, and the patterned layer 305 exposes the isolation pre-fabricated layer 304 and the top surface of the hard mask layer 303 on the first region i; etching the hard mask layer 303 on the first region I to expose the top surface of the first fin portion 301; after removing the hard mask layer 303 on the first region i, the patterned layer 305 is removed.
The process for removing the hard mask layer 303 on the first region includes one of dry etching and wet etching. In this embodiment, the process of removing the hard mask layer 303 on the first region is a wet etching process. The process parameters for removing the hard mask layer 303 on the first region include: the chemical liquid medicine is hot phosphoric acid with the concentration (volume fraction) of 60-95%, and the temperature range is 155-165 ℃. Since the hot phosphoric acid has a high etching selectivity to silicon nitride, the wet etching process has a high selectivity ratio to the hard mask layer 303 and the isolation preform layer 304, which is beneficial to removing the hard mask layer 303 and causes little damage to the isolation preform layer 304.
Referring to fig. 14, the first fin 301 is etched, and a plurality of openings 306 are formed in the isolation preform layer 304.
In this embodiment, the process of etching the first fin portion 301 is a dry etching process. The process parameters for etching the first fin portion 301 include: the etching gas comprises HBr and Cl2The power of the etching machine is 100w to 1000w, the pressure in the etching chamber is 2mTorr to 20mTorr, the flow rate of hydrogen bromide is 10sccm to 500sccm, and the flow rate of chlorine is 10sccm to 500 sccm. The dry etching process facilitates the formation of a better shaped opening.
Subsequently, a barrier layer is formed on the sidewall of the opening 303, and a method for forming the barrier layer is shown in fig. 15 to fig. 16.
Referring to fig. 15, a barrier material layer 307 is formed on the sidewall and bottom surface of the opening 306 and the surface of the isolation pre-fabricated layer 304.
The formation process of the barrier material layer 307 includes an atomic layer deposition process. In this embodiment, the forming process of the blocking material layer 307 is an atomic layer deposition process, and in other embodiments, the forming process may be another chemical vapor deposition process or a physical vapor deposition process. The atomic layer deposition process has good step coverage rate, and is beneficial to forming a film with uniform thickness.
The material of the barrier material layer 307 comprises silicon nitride; the barrier material layer 307 has a thickness in the range of 5 angstroms to 20 angstroms. The barrier material layer 307 is used for the subsequent formation of a barrier layer. In this embodiment, the material of the barrier material layer 307 is silicon nitride.
Referring to fig. 16, the barrier material layer 307 is etched back until the first fin 301 at the bottom of the opening 306 is exposed, so as to remove the barrier material layer 307 at the bottom of the opening 306.
In this embodiment, the method for forming the blocking layer 308 further includes: the barrier material layer 307 is etched back until the surface of the isolation pre-layer 304 is exposed.
The material of the barrier layer 308 comprises silicon nitride; the barrier layer has a thickness in the range of 5 angstroms to 20 angstroms. The material and thickness of the barrier layer 308 are determined by the barrier material layer 307. In this embodiment, the material of the barrier layer 308 is silicon nitride.
The barrier layer 308 is used for subsequently blocking the growth of the channel layer material on the sidewall, so that the channel layer material is epitaxially grown only from the first fin portion 301 at the bottom of the opening 306, the lateral growth of the channel layer material is inhibited, and the formation of the channel layer with a smooth surface is facilitated.
The parameters of the etching process for etching back the barrier material layer 307 include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 to 2.5 degrees. Because the included angle between the incident direction of the ions and the normal direction of the substrate is small, it is beneficial to remove the blocking material layer 307 at the bottom of the opening 306 and the surface of the isolation pre-made layer 304, and reduce the damage to the blocking layer 308.
Referring to fig. 17, a channel layer 309 is formed in the opening 306.
The material of the channel layer 309 includes silicon germanium.
The process of forming the channel layer 309 includes an epitaxial growth process. In this embodiment, the process of forming the channel layer 309 is an epitaxial growth process. The technological parameters of the epitaxial growth process comprise: the reaction gas comprises SiH4、GeH4And H2The SiH4The flow rate of the GeH is in a range of 110sccm to 130sccm4The flow rate of (b) is in the range of 95sccm to 115sccm, and the H2In the range of 25slm to 35slm, and in the range of 95 to 105 Torr.
The channel layer 309 is used to subsequently form a channel of a device. The channel layer 309 is formed by growing a channel layer material at the bottom of the opening, and is not required to be obtained by forming a channel material layer first and then etching, so that the stress of the channel layer is determined by the growth of the material, the stress release caused by subsequent etching is avoided, the stress of the channel layer is maintained, the improvement of the mobility of a carrier of the channel layer is not influenced, and the performance of a device is improved.
The channel layer 309 is made of germanium-silicon, the substrate is made of silicon, and due to lattice mismatch of germanium and silicon, compressive stress is generated on the channel layer 309, so that the effective conductance quality of holes in the channel direction can be reduced by the compressive stress, and the speed of a PMOS (P-channel metal oxide semiconductor) device is improved.
Subsequently, the isolation pre-layer 304 is etched to expose the top and part of the sidewalls of the channel layer 309, thereby forming an initial isolation layer.
Referring to fig. 18, after forming the channel layer 309 and before forming the initial isolation layer, the method further includes: the isolation pre-fabricated layer 304, the channel layer 309 are planarized until the channel layer 309 is flush with the second fin 302 top surface.
The process of planarizing the isolation pre-layer 304, the channel layer 309 includes a mechanochemical polishing process. The planarization process is used to make the channel layer 309 and the second fin 302 have the same height in the direction perpendicular to the substrate.
Referring to fig. 19, after forming the channel layer 309, the isolation pre-fabricated layer 304 is etched to expose the top and a portion of the sidewall of the channel layer 309, so as to form an initial isolation layer 310, wherein the top of the initial isolation layer 310 is lower than the top of the channel layer 309 and higher than or equal to the bottom of the channel layer 309.
The process of etching the isolation pre-fabricated layer 304 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the isolation pre-fabricated layer 304 is a dry etching process. The process parameters for etching the isolation pre-fabricated layer 304 include: the etching gas comprises HBr and Cl2The power of the etching machine is 100w to 1000w, the pressure in the etching chamber is 2mTorr to 20mTorr, the flow rate of hydrogen bromide is 10sccm to 500sccm, and the flow rate of chlorine is 10sccm to 500 sccm.
In this embodiment, the method further includes: the barrier layer 308 is removed. Specifically, the barrier layer 308 on the surface of the channel layer 309 on the initial isolation layer 310 is removed.
The process of removing the barrier layer 308 includes one or a combination of a dry etch process and a wet etch process. In this embodiment, the process of removing the barrier layer 308 is a wet etching process. The process parameters for removing the barrier layer 308 include: the chemical liquid medicine is hot phosphoric acid with the concentration (volume fraction) of 60-95%, and the temperature range is 155-165 ℃. Since hot phosphoric acid has a larger etching selectivity to silicon nitride, the process for removing the barrier layer 308 has a larger selection ratio to the barrier layer 308 and the initial isolation layer 208, and has a larger selection ratio to the barrier layer 308 and the channel layer 309, and has a larger selection ratio to the barrier layer 308 and the second fin portion 302, which is beneficial for removing the barrier layer 308, and has less damage to the initial isolation layer 310, the channel layer 309 and the second fin portion 302.
The initial isolation layer 310 is subsequently annealed to form an isolation layer.
In this embodiment, after forming the initial isolation layer 310 and before forming the isolation layer, the method further includes: modifying the channel layer 309 and the second fin 302 exposed by the initial isolation layer 310 so that the channel layer 309 and the second fin 302 exposed by the initial isolation layer 310 have the same size in the direction parallel to the substrate and in the direction perpendicular to the substrate.
The selection ratio of the process of modifying the channel layer 309 and the second fin 302 exposed by the initial isolation layer 310 to the channel layer 309 and the second fin 302 ranges from 1:3 to 1: 8. In this embodiment, the selection ratio of the process of modifying the channel layer 309 and the second fin portion 302 exposed by the initial isolation layer 310 to the channel layer 309 and the second fin portion 302 is 1: 3.
The process of modifying the channel layer 309 and the second fin 302 exposed by the initial isolation layer 310 includes one or a combination of dry etching and wet etching for the channel layer 309 and the second fin 302. In this embodiment, the process of modifying the channel layer 309 and the second fin portion 302 exposed by the initial isolation layer 310 is a dry etching process. The technological parameters of the dry etching process comprise: the etching gas comprises H2And Ar2The power range of the etching machine is 100W to 500W.
Referring to fig. 20, a capping layer 311 is formed on the exposed surface of the channel layer 309.
The material of the capping layer 311 includes silicon. The contact surface of the capping layer 311 and the channel layer 309 is made of silicon or silicon nitride material, the capping layer 311 may have a single-layer structure, and the material thereof may be silicon or SiN; the capping layer 311 may also be a multilayer structure, such as Si/SiO2SiN or SiN/SiO2Three-layer structure of/SiN.
In this embodiment, the covering layer 311 is further located on the surface of the second fin portion 302, and specifically, on the surface of the second fin portion 302 higher than the initial isolation layer 310.
The capping layer 311 is used to protect the channel layer 309 from being oxidized, and may also be formed with an oxide as a gate dielectric layer in a process of forming a gate structure through a subsequent oxidation process.
After the initial isolation layer 310 is formed, the method further includes: the initial isolation layer 310 is annealed to form an isolation layer.
The material of the isolating layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
The annealing treatment process comprises a water vapor annealing process, and the parameters of the annealing treatment process comprise: the gases used include oxygen/ozone and gaseous water, and the annealing temperature ranges from 350 ℃ to 750 ℃.
The annealing process is used to form an insulating medium layer on the initial isolation layer 310, and also to eliminate stress generated during the formation of the channel layer 309, thereby improving the performance of the device. On the other hand, the number of annealing treatments is also reduced, for the reason and purpose, please refer to the process description of forming the isolation pre-fabricated layer 304, which is not described herein again.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (25)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a first fin part positioned on the surface of the first area;
forming an isolation prefabricated layer on the surface of the substrate, wherein the isolation prefabricated layer is also positioned on the side wall of the first fin part;
etching the first fin part, forming a plurality of openings in the isolation prefabricated layer, and exposing the isolation prefabricated layer from the side walls of the openings;
forming a barrier layer on the sidewall of the opening;
and forming a channel layer in the opening.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the barrier layer comprises silicon nitride.
3. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness in a range of 5 angstroms to 20 angstroms.
4. The method of forming a semiconductor structure of claim 1, wherein the method of forming the barrier layer comprises: forming a barrier material layer on the side wall and the bottom surface of the opening and the surface of the isolation prefabricated layer; and etching the barrier material layer back until the first fin part at the bottom of the opening is exposed so as to remove the barrier material layer at the bottom of the opening.
5. The method of forming a semiconductor structure of claim 3, wherein the barrier material layer forming process comprises an atomic layer deposition process.
6. The method of forming a semiconductor structure of claim 3, wherein the parameters of the etch process to etch back the barrier material layer comprise: the angle between the incident direction of the ions and the normal direction of the substrate is 0 to 2.5 degrees.
7. The method of forming a semiconductor structure of claim 1, wherein after forming the channel layer, the isolation pre-layer is etched to expose a top portion and a portion of sidewalls of the channel layer to form an initial isolation layer, the initial isolation layer having a top portion lower than the top portion of the channel layer and higher than or level with the bottom portion of the channel layer.
8. The method of forming a semiconductor structure of claim 7, wherein after forming the initial isolation layer, further comprising: and annealing the initial isolation layer to form the isolation layer.
9. The method of forming a semiconductor structure of claim 8, wherein the annealing process comprises a water vapor annealing process.
10. The method of forming a semiconductor structure of claim 8, wherein the parameters of the annealing process comprise: the gases used include oxygen/ozone and gaseous water, and the annealing temperature ranges from 350 ℃ to 750 ℃.
11. The method of claim 8, wherein the isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
12. The method of claim 8, wherein the substrate further comprises a second region and a second fin portion on a surface of the second region.
13. The method of forming a semiconductor structure of claim 12, wherein after forming the channel layer and before forming the initial isolation layer, further comprising: and flattening the isolation prefabricated layer and the channel layer until the channel layer is flush with the top surface of the second fin part.
14. The method of forming a semiconductor structure of claim 12, further comprising: the initial isolation layer is also located on the side wall of the second fin portion and exposes the top of the second fin portion and part of the side wall.
15. The method of forming a semiconductor structure of claim 14, wherein after forming the initial isolation layer and before forming the isolation layer, further comprising: modifying the channel layer and the second fin portion exposed by the initial isolation layer to enable the channel layer exposed by the initial isolation layer and the second fin portion exposed by the initial isolation layer to have the same size in the direction parallel to the substrate and in the direction perpendicular to the substrate.
16. The method of forming a semiconductor structure of claim 15, wherein a selection ratio of the process of modifying the channel layer and the second fin exposed by the initial isolation layer to the channel layer and the second fin ranges from 1:3 to 1: 8.
17. The method of forming a semiconductor structure of claim 15, wherein after forming the initial isolation layer and before etching the channel layer and the second fin exposed by the initial isolation layer, further comprising: and removing the barrier layer.
18. The method of forming a semiconductor structure of claim 12, further comprising a hard mask layer on top surfaces of said first and second fins.
19. The method of forming a semiconductor structure of claim 18, further comprising, prior to forming the opening: and removing the hard mask layer on the first area.
20. The method of forming a semiconductor structure of claim 19, wherein removing the hard mask layer over the first region comprises: forming a graphical layer on the surface of the isolation prefabricated layer, wherein the graphical layer exposes the isolation prefabricated layer on the first area and the top surface of the hard mask layer; etching the hard mask layer on the first area to expose the top surface of the first fin part; and removing the patterning layer after removing the hard mask layer on the first area.
21. The method of forming a semiconductor structure of claim 1, further comprising: and forming a covering layer on the exposed surface of the channel layer.
22. The method of forming a semiconductor structure of claim 21, wherein a material of the capping layer comprises silicon.
23. The method of forming a semiconductor structure of claim 1, wherein the process of forming the channel layer comprises an epitaxial growth process.
24. The method of forming a semiconductor structure of claim 1, wherein the method of forming the isolation pre-layer comprises: and forming a dielectric material layer on the surface of the substrate, and flattening the dielectric material layer until the top surface of the first fin part is exposed to form the isolation prefabricated layer.
25. The method of claim 1, wherein the process parameters for forming the isolation pre-layer comprise: the gas used comprises NH3And (SiH)3)3N，NH3The flow rate of (SiH) is 1sccm to 1000sccm3)3The flow rate of N is 3sccm to 800sccm, and the temperature is 50 ℃ to 100 ℃.
CN202011265509.0A 2020-11-12 2020-11-12 Method for forming semiconductor structure Pending CN114496792A (en)

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