JPH02208943A - Manufacture of silicon thin film semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the cutting of a wiring due to steps by a method wherein oxygen ions or nitrogen ions are implanted to form insulating regions in a thin film and a FET operating region is separated individually in a state that there is no step. CONSTITUTION:A poly silicon thin film 11 is formed on an insulative substrate 10 and a mask 12 is formed to a region to become a FET operating region in the film 11. In a state that the mask 12 is formed, an ion implantation of oxygen ions or nitrogen ions is totally performed as shown by arrows 13 and the regions other than the FET operating region of the film 11 are converted into an insulator and are used as insulating regions 11a. Thereby, steps are never generated on the film 11 at all and the FET operating region 11b separated individually by the regions 11a is formed. Moreover, each electrode, a wiring and an insulating film are formed on the region 11b to form a FET. Thereby, at the time of an electrode wiring treatment and the like, the generation of steps is eliminated and the cutting due to steps of the wiring can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a MOS FET (field effect type The present invention relates to a method of manufacturing a silicon thin film semiconductor device (transistor).

BACKGROUND ART Conventionally, as shown in FIGS. 3 and 4, in a TPT-structured MOS FET, a source electrode and wiring 1, a drain electrode and wiring 2, and a gate electrode 3 are all formed on a semiconductor thin film 4 made of silicon. There is something I tried to do.

Looking at its manufacturing method, as shown in a conventional example in Japanese Patent Application Laid-Open No. 58-28871, first, a semiconductor thin film 4 is formed in the form of an island on an insulating substrate 5 such as quartz. Next, the entire surface of this semiconductor thin film 4 and insulating substrate 5 is covered with an insulating film 6, which is used as a gate insulating film. And the semiconductor thin film 4
A gate electrode 3 is formed across the island, and furthermore, the upper surface thereof is entirely covered with a thick interlayer insulating film 7. next,
Contact holes 8 are formed at appropriate locations in these insulating films 6 and 7, and a source electrode and wiring 1, a drain electrode and wiring 2, and a gate electrode wiring 9 are formed.

According to such a manufacturing method, since the gate electrode 3 is formed across the island-like region of the semiconductor thin film 4, the gate electrode 3
- In order to improve the insulation between the semiconductor thin films 4, the gate insulating film 6 must be made thicker.

In addition, in order to prevent the gate electrode 3 and each wiring 1, 2.9 from breaking, the semiconductor thin film 4 is made thinner, the side surfaces of the island-like portions are inclined, and the gate electrode 3 and each wiring 1, 2.9 are made thinner. 1, 2.9 must be made thicker. However, according to such a countermeasure, it becomes difficult to accurately form electrodes and wiring with minute dimensions, which is disadvantageous in achieving high integration.

For this reason, for example, the above-mentioned Japanese Patent Application Laid-Open No. 58-2887
As shown in Publication No. 1, an island-like region of a semiconductor thin film is
It is not only formed in the operating region of the FET, but also in the lower region of the source, drain, and gate electrodes as well as the entire wiring connected to these electrodes. Some are insulated by implanting ions or nitrogen ions. As a result, the step difference in the element in the FET operating region is reduced, reducing step breakage, and the gate electrode can be made thinner, thereby lowering the threshold voltage of the FET.

Furthermore, as shown in Japanese Patent Application Laid-Open No. 59-18672, a polycrystalline silicon thin film is formed on an insulating substrate, and FET
Some devices separate the FET operating region by selectively thermally oxidizing regions other than the operating region. As a result, the level difference in the element can be reduced and the number of level breaks can be reduced.

Problem to be Solved by the Invention However, in the case of the former method disclosed in Japanese Unexamined Patent Publication No. 58-28871, only the semiconductor thin film under the wiring is left and insulated. The difference in level is larger than that of the conventional method shown in . Furthermore, a process for leaving a semiconductor thin film in the operating area and below the wiring is also required, which is disadvantageous in terms of mass production.

In addition, in the case of using the method disclosed in Japanese Patent Application Laid-Open No. 59-18672,
Since it uses a process called selective thermal oxidation, it is disadvantageous in terms of lowering the temperature of the entire process.

Means for Solving the Problem A silicon thin film is formed on the surface of an insulating substrate, and oxygen ions or nitrogen ions are implanted into the silicon thin film to insulate the region other than the FET operating region. forming an individualized FET operating region in the thin film;
.

The silicon thin film formed on the active insulating substrate is partially insulated by ion implantation to form insulating regions and the FET operating regions are separated without any steps. There is almost no possibility of disconnection occurring during electrode wiring processing for a FET operating area. This also applies to wiring intersections, etc.
It is possible to keep intersections to the minimum necessary level difference,
Step breakage is prevented. For this purpose as well, since insulation treatment is performed by ion implantation of oxygen ions, etc., it is also possible to lower the process temperature.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2.

FIG. 1 shows the principle of this embodiment method. First, as shown in FIG. 1(a), a polycrystalline silicon thin film 11, for example, is formed as a silicon thin film on the surface of an insulating substrate lO made of quartz or the like. . In such a polycrystalline silicon thin film 11, F
A mask 12 is formed over a region that will become an ET operation region. Such a mask 12 is made of Si, for example, by sputtering.
n, formed as a film. With such a mask 12 formed, oxygen ions or nitrogen ions are implanted over the entire surface as shown by arrows 13. As a result, the region of the polycrystalline silicon thin film 11 other than the FET operating region covered by the mask 12 is insulated and becomes an insulating region tia, as shown in FIG. 3(b). Ion implantation for insulation is performed several times or once while changing the acceleration voltage to completely insulate the insulation region 11a. Insulating region 1 as shown in FIG. 1(b)
1a is formed, no step is formed in the polycrystalline silicon thin film 11, and individualized FET operating regions 11b are formed by the insulating regions 11a. Therefore, after this, the FET can be manufactured by forming each electrode, wiring, insulating film, etc. in the FET operating region 11b according to the conventional method.

FIG. 2 shows the FET operating region 1 that is individualized in this way.
An example of a FET fabrication process including the formation of 1b is shown. First, a quartz plate is used as the insulating substrate 11, and a polycrystalline silicon film gz is deposited on the surface thereof by low pressure CVD. At this time, the substrate temperature was 630° C. and the film thickness was 1000. On such a polycrystalline silicon thin film II, a film of Sin was deposited to a thickness of 800A using an RF sputtering device.
It is patterned by photolithography and used as a mask 12 for insulation by ion implantation. After this, oxygen ions are implanted at an acceleration voltage of 30 keV, a dose of 1, and OX 10 "am-" (ion implantation 13), and the polycrystalline silicon thin film 11 in the region other than the FET operating region 11b covered with the mask 12 is implanted. Insulate. As a result, an insulating region 11a is formed, and an FET operating region 11 is formed.
Individualize b.

Next, as shown in FIG. 2B, using the mask 12 as it is as a gate insulating film, a gate electrode 14 is formed from polycrystalline silicon thereon. In addition, an acceleration voltage of 30
Boron ions are implanted 15 at keV and at a dose of 1.0×10 cm − , and impurities are implanted into the source and drain in the FET operating region 11 b of the polycrystalline silicon thin film 11 .

Then, as shown in FIG. 3C, an interlayer insulating film 16 is deposited on these to a thickness of 5,000 yen, and contact holes 17 are formed at the source and drain locations. On top of this, AQ is deposited to a thickness of 5,000 yen and patterned to form a source electrode and wiring 18 and a drain electrode and wiring 19. The same applies to the gate electrode wiring for the gate electrode 14.

In this way, according to this embodiment, the FET operating region 11b
There is no difference in level between the remaining insulating region 11a and the remaining insulating region 11a.

In other words, a part of the insulating substrate is recessed, and a semiconductor thin film is deposited only in this recess, so that the surface becomes the same as the substrate surface.
This is equivalent to the assumption that an operating region is formed, and the FET operating region 11b, etc., including the lower part of the entire wiring, does not exist as an island on the insulating substrate 10.

As a result, the gate electrode and each wiring no longer cross the semiconductor island-like region or cross the step difference, as in the conventional case, and there is almost no possibility of step breakage occurring. That is, since the polycrystalline silicon thin film 11 remains as the insulating region 11a in areas other than the wiring portion, the step difference at the intersection of the wiring is only the film thickness on the lower wiring side at the intersection.

Claims (1)

[Claims] A silicon thin film is formed on the surface of an insulating substrate, and oxygen ions or nitrogen ions are injected into regions other than the FET operating region in this silicon thin film to insulate them. The FET operating region is formed and the FET operating region is individualized.
1. A method of manufacturing a silicon thin film semiconductor device, characterized in that a silicon thin film semiconductor device is formed.