JPH02299271A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a restraint on a hot carrier effect by a method wherein a channel region is provided above a source and and a drain diffusion layer, and a position at which an intermediate impurity concentration region becomes the highest in concentration is so set to be located distant from an interface between a semiconductor substrate and a gate oxide film. CONSTITUTION:A channel region is provided above source and drain diffusion layers 6, and an intermediate impurity concentration region 5 becomes the highest in concentration at a position which is so set to be located inside a semiconductor substrate 1 and distant from an interface between the semiconductor substrate 1 and a gate film 2. Therefore, the maximum point of impact ionization induced by an intense electrical field near drain is made distant from the interface between the semiconductor substrate 1 and the gate oxide film 2, and the intermediate impurity concentration region 5 is formed just under a gate electrode 3 so as to moderate the intensity of the electrical field of a point where impact ionization is liable to occur by the electrical field induced by the gate electrode 3. By this setup, hot carriers injected into the gate oxide film 2 or a side wall spacer 4 can be lessened in quantity, so that the effect of hot carriers can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device that can suppress hot carrier effects and realize high-speed operation.

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated, semiconductor devices have become increasingly finer. In this process, deterioration of device characteristics due to hot carrier effects has become a major problem.

Below, a conventionally used semiconductor device called an LDD structure will be described.

FIG. 4 is a sectional view of a main part of a semiconductor device of an N-channel transistor having an LDD structure. In FIG. 4, 1 is a semiconductor substrate such as silicon, 2 is a gate oxide film such as a silicon oxide film, 3 is a gate electrode such as polycrystalline silicon, 4 is a sidewall spacer such as an HTO film, and 5 is a medium concentration impurity region. ,
6 is a source/drain diffusion layer. FIG. 5 shows the impurity concentration distribution in the semiconductor substrate 1 taken along the line AB in FIG. 4. FIG.

Note that the medium concentration impurity region 5 is formed by implanting phosphorus ions P+ using the gate electrode 3 as a mask, and the source/drain diffusion layer 6 is formed by implanting arsenic ions As using the gate electrode 3 and sidewall spacers 4 as a mask.
It is formed by implanting + ions.

When a voltage is applied between the source and the drain, the depletion layer expands greatly in the medium concentration impurity region 5, thereby relaxing the high electric field and suppressing the hot carrier effect to some extent.

Problems to be Solved by the Invention However, in conventional semiconductor devices, a high electric field is generated near the substrate surface near the drain, so hot carriers generated by this electric field are injected into the gate oxide film 2 and the sidewall spacer 4. However, hot carrier effects such as an increase in the threshold voltage and subthreshold coefficient and a decrease in mutual conductance occur, which causes the device characteristics to deteriorate over time.

The present invention solves the above-mentioned conventional problems, and provides a semiconductor device that can reduce the amount of hot carriers injected into the gate oxide llI2 and the sidewall spanner 4, and suppress the hot carrier effect. With the goal.

Means for Solving the Problems To achieve this object, the semiconductor device of the present invention includes a channel region above the source/drain diffusion layer, and the position of maximum concentration of the medium concentration impurity region near the drain diffusion layer is located at the source. - It is configured to be below the upper limit of the drain diffusion layer.

Effect With this configuration, the intermediate concentration impurity region can be formed inside the semiconductor substrate by separating the position where the impurity concentration is maximum from the interface between the semiconductor substrate and the gate oxide film, and the maximum point of impact ionization caused by the high electric field near the drain can be located within the semiconductor substrate. It can be kept away from the interface between the substrate and the gate oxide film. Moreover, since the intermediate concentration impurity region can be formed directly under the gate electrode, the electric field strength at points where impact ionization is likely to occur can be alleviated by the electric field from the gate electrode. As a result, the amount of hot carriers injected into the gate oxide film and sidewall spacers can be reduced, and the hot carrier effect can be suppressed.

Furthermore, since the distance between the gate electrode and the source/drain diffusion layer is wide, the feedback capacitance between the gate electrode and the source/drain diffusion layer can be reduced, and the speed can be increased.

EXAMPLE Hereinafter, the present invention will be explained by way of an example with reference to the drawings.

FIG. 1 is a sectional view of a main part of a semiconductor device of an N-channel transistor in one embodiment of the present invention.

In FIG. 1, 1 is a semiconductor substrate such as silicon, 2 is a gate oxide film such as a silicon oxide film, 3 is a gate electrode such as polycrystalline silicon, 4 is a sidewall spacer such as an HTO film, and 5 is a medium concentration impurity region. , 6 are source/drain diffusion layers, which have the same structure as the conventional example. In addition, the second
The figure shows the impurity concentration distribution of the AB cross section in FIG.

In FIG. 1, after forming a gate oxide film 2 and a gate electrode 3 on a semiconductor substrate 1, the surface of the semiconductor substrate 1 at the position where the source/drain diffusion layer 6 is to be formed is formed into a channel using the gate electrode 3 as a mask. Approximately 1 thick, approximately the same thickness as the depth.
Dry etching by 0 nm. This step may be performed by selectively growing an oxide film and then removing the oxide film. Next, to form the medium concentration impurity region 5, phosphorus ions P+ were heated at 60KeV and 5X 10”el.
Ion implantation is performed at m −2. Source/drain diffusion layer 6
After forming the sidewall spacer 4, arsenic ions (As) were injected at 40K e V, 4 using the gate electrode 3 and the sidewall spacer 4 as masks.
Ion implantation at X 10"c++-2. Then 900
Annealing is performed at ℃ for 150 minutes. This annealing causes impurities to be diffused three-dimensionally, so that they are diffused not only downward but also upward. That is, a portion of medium concentration impurity region 5 diffuses from the inside of semiconductor substrate 1 toward the surface and comes into contact with the channel region.

Through the above manufacturing process, as shown in FIG. 2, the position where the impurity concentration of medium concentration impurity region 5 is maximum can be set away from the interface between semiconductor substrate 1 and gate oxide film 2.

A semiconductor device of the present invention and a conventional semiconductor device were manufactured under the same process conditions as described above, and when 2V was applied to the gate electrode and 5V was applied to the drain, the maximum position of impact ionization near the drain was compared. is about 50 nm
1 is pushed inside the semiconductor substrate 1.

The probability P that hot carriers are injected into the gate oxide film 2 and the sidewall spacers 4 is P=exp(-φ//
T) e xp (-x/λ) where φ is the energy required for hot carriers to overcome the interface between semiconductor substrate 1 and gate oxide film 2.

k is Boltzmann's constant.

T is the temperature of the hot carrier.

X is the path taken by hot carriers to reach the interface.

λ is the mean free path of hot carriers. It can be expressed as When φ and T are constant and λ=7.3 nm,
By pushing the maximum position of impact ionization into the semiconductor substrate 1 by about 50 nm, the probability that hot carriers will be injected into the gate oxide film 2 and the sidewall spacers 4 is reduced by 1/1000.

Therefore, with the semiconductor device of the present invention, the amount of hot carriers injected into the gate oxide film 2 and the sidewall spacers 4 can be reduced, and the hot carrier effect can be suppressed.

In the above embodiment, the medium concentration impurity region 5 and the source/drain diffusion layer 6 were formed using the sidewall spacer 4. However, in another embodiment, as shown in the cross-sectional view of FIG. Source without using 4.
The medium concentration impurity region 5 may be formed at the step between the drain diffusion layer 6 and the channel region.

Effects of the Invention According to the present invention, the channel region is provided above the source/drain diffusion layer, and the maximum concentration position of the medium concentration impurity region near the drain diffusion layer is located below the upper limit of the source/drain diffusion layer. By setting this, an excellent semiconductor device that can suppress the hot carrier effect can be realized.

[Brief explanation of drawings]

1 and 2 are a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention and an impurity concentration distribution of the main part, FIG. 3 is a cross-sectional view of a device according to another embodiment of the present invention, and FIG. , 5th
The figure shows a cross-sectional view of a conventional semiconductor device and an impurity concentration distribution. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate oxide film, 3... Gate electrode, 4... Side wall spacer, 5... Middle concentration impurity region,
6... Source/drain diffusion layer. Name of agent Patent attorney Shigetaka Kurino Haka 1 person 2- Gate entrance L around 3- Gate E 4゛°゜゛゛゛Source drain/drain rod 1 No. 2 Figure 2 L 2° - Gate oxidation R refreshing 3 -...Ge) 1 &5' = No refreeze in the upper part' Figure 3: Rain 5 Figure: Turtle

Claims (1)

[Claims] A channel region is provided above the main part of the source/drain diffusion layer, and at least the position of the maximum concentration of the intermediate concentration impurity region near the source/drain diffusion layer is below the upper limit of the source/drain diffusion layer. A semiconductor device characterized by: