KR20090044484A - Test pattern of semiconductor device and method for forming the same - Google Patents

Test pattern of semiconductor device and method for forming the same Download PDF

Info

Publication number
KR20090044484A
KR20090044484A KR1020070110605A KR20070110605A KR20090044484A KR 20090044484 A KR20090044484 A KR 20090044484A KR 1020070110605 A KR1020070110605 A KR 1020070110605A KR 20070110605 A KR20070110605 A KR 20070110605A KR 20090044484 A KR20090044484 A KR 20090044484A
Authority
KR
South Korea
Prior art keywords
metal
film
gate
polysilicon film
semiconductor device
Prior art date
Application number
KR1020070110605A
Other languages
Korean (ko)
Inventor
최신규
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070110605A priority Critical patent/KR20090044484A/en
Publication of KR20090044484A publication Critical patent/KR20090044484A/en

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Abstract

The present invention discloses a test pattern of a semiconductor device and a method of forming the semiconductor device for efficiently monitoring the presence or absence of abnormality occurring at an interface between a polysilicon film of a gate and a metal film. A test pattern of a semiconductor device according to the present disclosure includes: a semiconductor substrate having an active region, wherein the gate formation region is recessed including the active region to form a line type groove; A plurality of gates including a polysilicon film formed to fill the linear groove and serving as a first terminal, and a metal film formed on a portion of the polysilicon film disposed in the active region; And a metal pattern formed on the gate so as to connect only metal films of neighboring gates which are not interconnected by the polysilicon film, and serving as second terminals.

Description

TEST PATTERN OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

The present invention relates to a test pattern of a semiconductor device and a method of forming the semiconductor device, and more particularly, to a test pattern of a semiconductor device capable of efficiently monitoring the presence or absence of abnormality occurring at an interface between a polysilicon film of a gate and a metal film. It relates to the formation method thereof.

In general, a gate of a semiconductor device includes a gate conductive film made of an oxide film and a polysilicon film, and a laminated film of a protective film formed on the gate conductive film.

In other words, a gate of a semiconductor device has been commonly used a doped polysilicon film as a conductive film, which is characterized in that the polysilicon film has a high melting point, ease of thin film formation, ease of line pattern, stability to an oxidizing atmosphere, and flat surface formation. This is because the physical properties required as the same gate are sufficiently satisfied. In addition, in the actual semiconductor device, the polysilicon gate contains a dopant such as phosphorus (P), arsenic (As), and boron (B), thereby achieving low resistance.

However, in accordance with the recent trend of high integration of semiconductor devices, as the design rule decreases, the channel length of the gate becomes smaller than the width of the gate, thereby forming the gate having a lower resistance. As the conductive film, a laminated film of a polysilicon film and a metal silicide film or a laminated film of a polysilicon film, a metal silicide film and a metal film was used.

Specifically, a polyside gate structure made of a laminated film of a polysilicon film and a metal polyside film as a gate material has been converted to a metal gate structure made of a laminated film of a polysilicon film and a metal film.

Hereinafter, a manufacturing method of a semiconductor device for forming the metal gate will be briefly described.

First, a trench is formed by recessing the device isolation region of the semiconductor substrate having the active region and the device isolation region. Then, after the insulating film is deposited to fill the trench, the surface of the insulating film is planarized to form an isolation layer defining an active region of the semiconductor substrate.

Subsequently, a gate insulating film, a gate conductive film, and a gate hard mask film are sequentially deposited on the semiconductor substrate including the device isolation film. The gate conductive film is formed of a laminated film of a polysilicon film and a metal film, for example, a tungsten film. Then, the gate hard mask layer, the gate conductive layer, and the gate insulating layer are recessed to form a plurality of gates on the semiconductor substrate.

Thereafter, a series of known subsequent processes are sequentially performed to complete the semiconductor device to which the metal gate structure is applied.

However, when applying the metal gate structure consisting of the laminated film of the polysilicon film and the metal film, compound impurities at the interface between the polysilicon film and the metal film due to the difference in the composition between the polysilicon film and the metal film and the atmosphere of the forming process. Is formed. Since such compound impurities may still remain at the interface even after subsequent cleaning, annealing, or the like, the resistance of the gate is increased, resulting in deterioration of device characteristics.

As a result, a test pattern for monitoring an abnormality occurring at the interface between the polysilicon film and the metal film in the metal gate structure is formed.

However, in the case of the test pattern according to the prior art, in order to suppress the oxidation of the metal film, only the metal film of the gate conductive film is etched when the gate is formed, and the polysilicon film under the metal is not etched, so that there is no abnormality under the metal film. You cannot monitor it. Therefore, it is impossible to properly monitor the presence or absence of abnormality occurring at the interface between the polysilicon film and the metal film.

In addition, since the test pattern according to the related art has a structure different from that of the actual DRAM, a mask pattern for forming the test pattern must be additionally formed during the manufacturing process of the semiconductor device. The manufacturing cost of the device increases.

The present invention provides a test pattern of a semiconductor device and a method of forming the semiconductor device capable of efficiently monitoring the presence or absence of abnormality occurring at an interface between a polysilicon film of a gate and a metal film.

The test pattern of the semiconductor device according to the present invention includes a semiconductor substrate having an active region, the gate forming region including the active region and recessed to form a line type groove; A plurality of gates including a polysilicon film formed to fill the linear groove and serving as a first terminal, and a metal film formed on a portion of the polysilicon film disposed in the active region; And a metal pattern formed on the gate so as to connect only metal films of neighboring gates which are not interconnected by the polysilicon film, and serving as second terminals.

Here, the polysilicon film is formed by protruding a portion from the active region to the upper portion of the line-shaped groove.

The metal film is a film containing tungsten.

The metal pattern may include: a plug formed on the gate to contact the metal film of the gate; And a metal pad formed to connect the plug on the plug.

In addition, the method of forming a test pattern of a semiconductor device according to an embodiment of the present invention comprises the steps of: forming a linear groove by recessing a gate formation region including the active region of a semiconductor substrate having an active region; Forming a polysilicon film to fill the linear grooves; Forming a metal film on the polysilicon film; Etching the metal film and the polysilicon film to form a plurality of gates including a polysilicon film filling the line groove and serving as a first terminal and a metal film formed on a portion of the polysilicon film disposed in the active region; step; And forming only a metal pattern on the gate that connects only metal films of neighboring gates that are not interconnected by the polysilicon film, and serves as a second terminal.

The polysilicon film is formed to bury the linear groove and to protrude above the linear groove.

The metal film is formed of a film containing tungsten.

The forming of the metal pattern may include forming a plug on each gate to contact the metal layer of the gate; And forming a metal pad connecting the plug on the plug.

As described above, the present invention forms a gate including a polysilicon film formed to fill a line-shaped groove and serving as a first terminal and a metal film formed on a polysilicon film portion disposed in an active region portion, and forming the gate. By connecting to form a metal pattern to serve as a second terminal, it is possible to form a test pattern that can measure the interface resistance between the polysilicon film and the metal film.

In addition, the present invention by forming the test pattern through the same process as the process of forming a DRAM cell gate without any additional process, it is possible to accurately measure the interface resistance, and furthermore, the cost of forming the test pattern Can reduce the cost.

Therefore, the present invention can effectively monitor the presence or absence of the interface between the polysilicon film and the metal film of the gate.

According to the present invention, after the gate formation region of the semiconductor substrate is etched to form a linear groove, a polysilicon film is deposited to fill the linear groove, and then a metal film is deposited on the polysilicon film. Then, the metal layer and the polysilicon layer are etched to form gates on an active region, and a metal pattern connecting the gates is formed to form a test pattern.

In this case, the polysilicon film of the gate is deposited to fill the line-shaped groove and connected in a line shape in the semiconductor substrate to serve as a first terminal of the test pattern, and the metal films of the gate are connected to each other through the metal pattern. . That is, the metal layers of the gates not connected by the polysilicon layer are connected to each other through the metal pattern, and the metal pattern serves as a second terminal of the test pattern.

In this way, by measuring the resistance of the gates connected to each other through the first and second terminals of the test pattern, it is possible to measure the interface resistance between the polysilicon film and the metal film of the gate, thereby, the polysilicon film The abnormality which occurred in the interface between and a metal film can be monitored efficiently.

In addition, the present invention is formed by the same process as the formation of the normal cell gate of the DRAM (DRAM), thereby eliminating the need for additional mask pattern formation and processing in the manufacture of the test pattern, as a result However, there is no additional cost for monitoring the abnormality.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a perspective view illustrating a test pattern of a semiconductor device according to an exemplary embodiment of the present invention.

As shown, the gate forming region including the active region of the semiconductor substrate 100 having the active region is recessed to form a line type groove (H). An active region may be defined in the semiconductor substrate 100, and a device isolation layer (not shown) in which the gate formation region is recessed may be further formed. In this case, both the active region and the gate formation region of the device isolation film are recessed to form a line-shaped groove (H).

In order to fill the linear grooves H, a polysilicon film 102 having a portion protruding from the active region portion to the upper portion of the linear grooves H is formed, and the polysilicon film ( A metal film 104, for example, a tungsten film, is formed on the protruding portion of the 102, that is, the portion of the polysilicon film 102 disposed in the active region. As a result, a plurality of gates G including the polysilicon film 102 and the metal film 104 are formed on the active region of the semiconductor substrate 100.

The gate may further include a gate insulating layer (not shown) formed on the semiconductor substrate 100 on the surface of the linear groove H, and further include a hard mask layer 106 formed on the metal layer 104. You may. Here, the gates G are interconnected by a polysilicon film 102 formed to fill the line-shaped groove H in the semiconductor substrate 100, and the polysilicon film 102 is formed in the first pattern of the test pattern. It serves as a terminal.

A plug 108 is formed on each gate G to contact the metal film 104 of the gate G, and the metal pad 110 connecting the plug 108 to each other on the plug 108. Is formed to form a metal pattern 112 including the plug 108 and the metal pad 110. Here, the metal pattern 112 is formed to connect only the metal films 104 of neighboring gates G which are not interconnected by the polysilicon film 102, and the metal pattern 112 is a test pattern. It serves as the second terminal of.

2A to 2E are perspective views illustrating processes for forming a test pattern of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an isolation layer (not shown) defining the active region is formed in the isolation region of the semiconductor substrate 100 having the active region and the isolation region. Then, the gate forming region including the device isolation layer and the active region is recessed to form a line-shaped groove (H). The linear groove H is formed by recessing the active region and the device isolation layer together.

Referring to FIG. 2B, a gate insulating film (not shown) is formed on a surface of the semiconductor substrate 100 on which the linear grooves H are formed, and then poly is embedded to fill the linear grooves H on the gate insulating film. Silicon film 102 is deposited.

Subsequently, the polysilicon film 102 is planarized, for example, chemical mechanical polishing (CMP), or etch back. In this case, the etch back may be performed until the semiconductor substrate 100 is exposed or to protrude to the upper portion of the semiconductor substrate 100, that is, the upper portion of the line-shaped groove H.

Referring to FIG. 2C, a metal film 104, preferably a tungsten film, is deposited on the polysilicon film 102, and then a hard mask film 106 is deposited on the metal film 104.

Referring to FIG. 2D, the hard mask layer 106, the metal layer 104, the polysilicon layer 102, and the gate insulating layer are etched to form a plurality of gates G in an active region of the semiconductor substrate 100. do. In this case, the polysilicon film 102 of the gate G fills the line-shaped groove H, and the metal film 104 and the hard mask film 106 are disposed in the active region of the semiconductor substrate 100. It remains on the polysilicon film 102 part.

Here, since the polysilicon layer 102 of the gate G is formed to fill the linear groove H formed in the semiconductor substrate 100, the gates G formed on the linear groove H of the same line may be formed. Interconnected by the polysilicon film 102, this polysilicon film 102 serves as a first terminal in the test pattern of the present invention.

Referring to FIG. 2E, a plug 108 is formed on each gate G to contact the metal film 104 of the gate G. Referring to FIG. Subsequently, a metal pad 110 interconnecting the plugs is formed on the plug 108 to form a metal pattern 112 including the plug 108 and the metal pad 110.

Here, the metal pattern 112 is formed to connect only the metal films 104 of neighboring gates G that are not interconnected by the polysilicon film 102 on the gate G, and such metal The pattern 112 serves as the second terminal in the test pattern of the present invention.

3 is a plan view illustrating a test method of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 4A to 4B are cross-sectional views corresponding to lines A-A 'and B-B' of FIG. 3.

Referring to FIG. 3, a polysilicon film 102 of a gate is formed to fill a line-shaped groove formed in the semiconductor substrate 100 and is formed on a portion of the polysilicon film 102 formed in an active region of the semiconductor substrate 100. The metal film 104 of the gate is formed. A metal pattern 112 including a plug 108 contacting the metal film 104 and a metal pad 110 connecting the plug 108 is formed on the gate.

Referring to FIG. 4A, the gates G of the test pattern according to the exemplary embodiment of the present invention are interconnected through the polysilicon layer 102 formed to fill the linear grooves H under the gate G. The polysilicon film 102 serves as a first terminal of the test pattern.

Referring to FIG. 4B, the gate G of the test pattern according to the exemplary embodiment of the present invention may be formed of the polysilicon layer through the metal pattern 112 formed to contact the metal layer 104 on the gate G. Neighboring gates G which are not connected by 102 are connected, and the metal pattern 112 serves as a second terminal of the test pattern.

Referring to the test method according to the embodiment of the present invention, the current flowing through the metal pattern 112, the metal film 104 of the gate (G) and the polysilicon film 102 is embedded in the line-shaped groove (H). The polysilicon film 102 passes through the formed polysilicon film 102 to the polysilicon film 102, the metal film 104, and the metal pattern 112 of another adjacent gate G. The current flowing through the path A is measured. The interfacial resistance between the polysilicon film 102 and the metal film 104 of the gate G may be measured.

For example, when no abnormality occurs at the interface between the polysilicon film 102 and the metal film 104 of the gate G, the interface resistance has a relatively small value of about several Ω or less, and the gate G When an abnormality occurs at the interface between the polysilicon film 102 and the metal film 104, the interface resistance value has a relatively large value of several hundred Ω or more.

Therefore, the present invention can measure the interface resistance between the polysilicon film 102 and the metal film 104 of the gate G through the test pattern, by analyzing the measured interface resistance value, the gate (G) The abnormality occurring at the interface between the polysilicon film 102 and the metal film 104 can be efficiently monitored.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a perspective view for explaining a test pattern of a semiconductor device according to an embodiment of the present invention.

2A to 2E are perspective views illustrating processes for forming a test pattern of a semiconductor device according to an exemplary embodiment of the present invention.

3 is a plan view for explaining a test method of a semiconductor device according to an embodiment of the present invention.

4A to 4B are cross-sectional views corresponding to lines A-A 'and B-B' in FIG. 3.

Explanation of symbols on the main parts of the drawings

100: semiconductor substrate H: line groove

102 polysilicon film 104 metal film

106: hard mask film G: gate

108: plug 110: metal pad

112: metal pattern

Claims (8)

A semiconductor substrate having an active region, wherein the gate formation region is recessed including the active region to form a line type groove; A plurality of gates including a polysilicon film formed to fill the linear groove and serving as a first terminal, and a metal film formed on a portion of the polysilicon film disposed in the active region; And A metal pattern formed on the gate to connect only metal films of neighboring gates not interconnected by the polysilicon film, and serving as a second terminal; Test pattern of a semiconductor device comprising a. The method of claim 1, The polysilicon film is a test pattern of a semiconductor device, characterized in that formed by protruding a portion from the active region portion to the upper portion of the line-shaped groove. The method of claim 1, The metal film is a test pattern of a semiconductor device, characterized in that the film containing tungsten. The method of claim 1, The metal pattern is, A plug formed on the gate to contact the metal film of the gate; And A metal pad formed to connect the plug on the plug; Test pattern of a semiconductor device comprising a. Recessing a gate formation region including the active region of a semiconductor substrate having an active region to form a linear groove; Forming a polysilicon film to fill the linear grooves; Forming a metal film on the polysilicon film; Etching the metal film and the polysilicon film to form a plurality of gates including a polysilicon film filling the line groove and serving as a first terminal and a metal film formed on a portion of the polysilicon film disposed in the active region; step; And Forming a metal pattern on the gate to connect only metal films of neighboring gates not interconnected by the polysilicon film, and to serve as second terminals; Test pattern formation method of a semiconductor device comprising a. The method of claim 5, wherein The polysilicon film is a method of forming a test pattern of a semiconductor device, characterized in that to fill the line-shaped grooves and to protrude to the upper portion of the line-shaped grooves. The method of claim 5, wherein And the metal film is formed of a film including tungsten. The method of claim 5, wherein Forming the metal pattern, Forming a plug on each gate to contact the metal film of the gate; And Forming a metal pad connecting the plug on the plug; Test pattern formation method of a semiconductor device comprising a.
KR1020070110605A 2007-10-31 2007-10-31 Test pattern of semiconductor device and method for forming the same KR20090044484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070110605A KR20090044484A (en) 2007-10-31 2007-10-31 Test pattern of semiconductor device and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070110605A KR20090044484A (en) 2007-10-31 2007-10-31 Test pattern of semiconductor device and method for forming the same

Publications (1)

Publication Number Publication Date
KR20090044484A true KR20090044484A (en) 2009-05-07

Family

ID=40855039

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070110605A KR20090044484A (en) 2007-10-31 2007-10-31 Test pattern of semiconductor device and method for forming the same

Country Status (1)

Country Link
KR (1) KR20090044484A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571479A (en) * 2021-06-30 2021-10-29 华为技术有限公司 Test method of chip packaging assembly

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571479A (en) * 2021-06-30 2021-10-29 华为技术有限公司 Test method of chip packaging assembly

Similar Documents

Publication Publication Date Title
US7800155B2 (en) Semiconductor device
US10593622B2 (en) Electrical fuse and/or resistors structures
US20200111795A1 (en) Semiconductor device and manufacturing method thereof
CN109560001B (en) Defect detection structure, device and method for semiconductor device
JP2010157588A (en) Semiconductor device and method of manufacturing same
US9236315B2 (en) Electrical test structure for devices employing high-k dielectrics or metal gates
US8890551B2 (en) Test key structure and method for measuring step height by such test key structure
KR20090044484A (en) Test pattern of semiconductor device and method for forming the same
KR100370131B1 (en) Metal-Insulator-Metal Capacitor and Method for Fabricating the Same
JP2009164534A (en) Semiconductor device and manufacturing method therefor
TW201320212A (en) Testkey structure and method for measuring step height by such testkey structure
KR20110001136A (en) Method for manufacturing semiconductor device
US20130234138A1 (en) Electrical test structure for determining loss of high-k dielectric material and/or metal gate material
TW202205525A (en) Semiconductor structure and method for manufacturing the same
KR100788373B1 (en) Semiconductor device including silicidation monitoring pattern
TWI570926B (en) Embedded resistor
US8507378B2 (en) Method and structure for self aligned contact for integrated circuits
CN112289861B (en) Semiconductor structure and manufacturing method thereof
KR20090026675A (en) Test pattern of semiconductor device and method for forming the same
KR100505399B1 (en) Method for forming contact in semiconductor device
KR20090068569A (en) Test pattern for semiconductor device and method for aorming the test pattern
KR100745063B1 (en) Method for fabricating a landing plug of semiconductor device
KR100955933B1 (en) Semiconductor device and method of manufacturing the same
KR20080088996A (en) Test pattern of semiconductor device
CN113284845A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application