KR20110001136A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce interfacial resistance by depositing a poly-silicon layer between an active region and a storage node contact. CONSTITUTION: An element isolation film(220) defining an active region(210) on a substrate(200) is formed. A hard mask layer is formed on the entire surface of the substrate including the element isolation film. A buried gate(260) of a recess structure is formed. A poly-silicon layer(270) is formed on the entire surface of the substrate including the active region. A bit-line(320) including a contact is formed on the upper side of the poly-silicon layer. A storage node contact(340) in connection with the poly-silicon layer is formed.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of increasing an overlap CD (critical dimension) between an active region and a storage node contact in manufacturing a highly integrated semiconductor device.

A semiconductor is a class of materials according to electrical conductivity, and is a material belonging to an intermediate region of a conductor and a non-conductor. The semiconductor is used to add semiconductor impurities and connect conductors to create semiconductor devices such as transistors. A device that performs various functions such as data storage using such a semiconductor device is called a semiconductor device.

As the semiconductor devices are increasingly integrated, semiconductor chip sizes are reduced, and thus, the size of a plurality of semiconductor devices formed in the chip is also reduced.

1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, an isolation layer 120 defining an active region 110 is formed on a semiconductor substrate. In this case, the device isolation layer 120 is formed of a silicon on dielectric (SOD) film. A hard mask layer (not shown) is formed on the entire surface including the active region 110 as a nitride film.

Subsequently, after the photoresist film is formed on the hard mask layer, a photoresist pattern (not shown) is formed by an exposure and development process using a recess mask. The hard mask layer, the active region 110 and the device isolation layer 120 are etched using the photoresist pattern as a mask to form a recess (not shown). Thereafter, the photoresist pattern is removed.

The conductive layer 130 is formed on the entire surface including the recess. In this case, the conductive layer 130 is formed using any one selected from TIN, TIN / W, and a combination thereof. Thereafter, the conductive layer 130 is etched back so as to remain in the recess.

Next, the buried gate nitride film 140 is formed on the entire surface including the recess. Thereafter, the buried gate nitride layer 140 is buried until the active region 110 and the device isolation layer 120 are exposed to form a buried gate 150.

Next, a sealing nitride film 160 is formed on the entire surface including the buried gate 150. Thereafter, a first interlayer insulating film 170 is formed on the sealing nitride film 160.

Next, after the photosensitive film is formed on the first interlayer insulating film 170, a photosensitive film pattern (not shown) is formed by an exposure and development process using a bit line contact mask. The first interlayer insulating layer 170 and the sealing nitride layer 160 are etched using the photoresist pattern as a mask to form a bit line contact region (not shown). Thereafter, a conductive material is embedded in the bit line contact region to form the bit line contact 180.

Next, the bit line conductive layer 185 and the hard mask layer 195 are deposited on the bit line contact 180 to form the bit line 196. At this time, the hard mask layer 195 is formed of a nitride film.

Next, a second interlayer insulating film 197 is formed on the entire surface including the first interlayer insulating film 190.

Next, the second interlayer insulating layer 197, the first interlayer insulating layer 170, and the sealing nitride layer 160 are etched using the storage node contact mask until the active region is exposed, thereby forming the storage node contact region (not shown). Form. Thereafter, a conductive material is filled in the storage node contact region to complete the storage node contact 198.

Here, a problem occurs when the interlayer insulating films 197 and 170 and the nitride film 160 are removed to form the storage node contact region. First, since the selectivity ratio between the interlayer insulating film and the nitride film is different, a low etch target may result in a defect not being exposed to the lower active region 110, and a CD (Critical Dimension) overlapping even when the active region 110 is exposed. There is a problem that the interface resistance increases because of the small size. On the other hand, if the etch target is high, there is a problem that adjacent bit line contacts and self-aligned contact (SAC) defects occur.

In order to solve the above-mentioned problems, the present invention deposits a polysilicon layer between an active region and a storage node contact, thereby increasing an overlap CD (Critical Dimension) between the active region and the storage node contact to reduce the interface resistance. When etching the insulating layer and forming the storage node contact, the etching target is etched until the lower polysilicon layer is exposed, so it is easy to set an etching target, and the SAC with adjacent bit line contacts generated due to overetching (Self-aligned contact) Provides a method of manufacturing a semiconductor device that can prevent a fail.

The present invention provides a method of forming an isolation region defining an active region on a semiconductor substrate, forming a hard mask layer on an entire surface including the device isolation layer, forming a buried gate having a recess structure, and forming the hard mask layer. Removing, forming a polysilicon layer on the entire surface including the exposed active region, and then planarizing, forming a bitline including a contact on the polysilicon layer, and storage connected to the polysilicon layer. It provides a method for manufacturing a semiconductor device comprising forming a node contact.

Preferably, the hard mask layer is formed of an oxide film.

Preferably, the forming of the bit line may include forming a first insulating film on the entire surface including the polysilicon layer, etching the first insulating film to form a bit line contact region, and forming the bit line contact region. Embedding a conductive material in to form a bitline contact, and forming a bitline on the bitline contact.

Advantageously, forming the bit line on the bit line contact comprises depositing a bit line conductive layer and a hard mask layer on the entire surface including the bit line contact.

Preferably, the forming of the storage node contact comprises forming a second insulating film on the entire surface including the bit line, and etching the second insulating film and the first insulating film until the polysilicon layer is exposed. Forming a node contact region and embedding a conductive material in the storage node contact region.

The forming of the buried gate may include forming a recess by etching the hard mask layer, the active region and the device isolation layer, filling a conductive layer in the recess, and forming the recess in the recess layer. Leaving a portion in the recess, forming a nitride film in the recess, and planarizing etching the nitride film until the hard mask layer is exposed.

According to the present invention, by depositing a polysilicon layer between an active region and a storage node contact, an overlap CD (critical dimension) between the active region and the storage node contact is increased to reduce an interfacial resistance, and an insulating layer is etched to form a storage node contact. It is easy to set an etch target because it is etched until the lower polysilicon layer is exposed, and it is possible to prevent self-aligned contact (SAC) fail with adjacent bit line contacts caused by excessive etching. There are advantages to it.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2, a bar-type active region (not shown) having a 6F2 structure is arranged and arranged in an island type in an oblique direction on a semiconductor substrate 200, and an element is formed between the active regions. The separator 220 is formed.

Next, the buried gate 260 is formed to intersect with the longitudinal direction of the active region. At this time, by removing the insulating film around the buried gate 260, by depositing a polysilicon layer 270, the overlap margin between the storage node contact 340 and the polysilicon layer 270 formed during the subsequent process is Increases.

Here, the plurality of buried gates 260 divides one active region into three, each of which has storage node contacts 260 formed at both outer regions of the active regions exposed between the buried gates 260, and a bit line contact at the center thereof. 290 is formed.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention, and illustrate a cross-sectional view taken along line AA ′ of FIG. 2.

Referring to FIG. 3A, an isolation layer 220 defining an active region 210 is formed on a semiconductor substrate 200. In this case, the device isolation layer 220 may be formed of a silicon on dielectric (SOD) layer. The hard mask layer 230 is formed on the entire surface including the active region 210. At this time, the hard mask layer 230 is preferably an oxide (Oxide). The hard mask layer 230 may be easily removed due to the difference in etching selectivity with the buried gate nitride layer when the dip-out is removed in a subsequent process.

Referring to FIG. 3B, after the photoresist film is formed on the hard mask layer 230, a photoresist pattern (not shown) is formed by an exposure and development process using a recess mask. The hard mask layer 230, the device isolation layer 220, and the active region 210 are etched using the photoresist pattern as a mask to form a recess (not shown). Thereafter, the photoresist pattern is removed.

Next, the conductive layer 240 is buried in the recess. In this case, the conductive layer 240 is preferably formed using any one selected from TIN, TIN / W, and a combination thereof. Thereafter, only a portion of the conductive layer 240 is etched back to form the recess.

Next, the buried gate nitride film 250 is deposited on the entire surface including the recess. Subsequently, the buried gate nitride layer 250 includes the conductive layer 240 and the buried gate nitride layer 250 by chemically polishing the buried gate nitride layer 250 until the hard mask layer 230 is exposed. ).

3C and 3D, the hard until the active region 210 is exposed using a mask in the form of a line exposing the active region 210 on the front surface including the buried gate 260. The mask layer 230 is removed by performing a dip out process. In this case, the dip out process is preferably a wet dip out process.

Here, the hard mask layer 230 is easily removed because it is a material having a difference in etching selectivity from the buried gate nitride layer 250.

Thereafter, a polysilicon layer 270 is deposited on the entire surface including the exposed active region 210. Thereafter, the polysilicon layer 270 is planarized etched until the buried gate nitride layer 250 is exposed.

Here, the polysilicon layer 270 increases CD (Critical Dimension) overlapping with the storage node contact formed during the subsequent process, and decreases the interface resistance by increasing the CD with the lower active region 210. .

Referring to FIG. 3E, the first insulating layer 280 is formed on the entire surface including the polysilicon layer 270. After the photoresist layer is formed on the first insulating layer 280, a photoresist pattern (not shown) is formed by an exposure and development process using a bit line contact mask. Thereafter, the first insulating layer 280 is etched using the photoresist pattern as a mask to form a bit line contact region (not shown). A bit line contact 290 is formed by filling a conductive material in the bit line contact region.

Next, the bit line conductive layer 300 and the hard mask layer 310 which are connected to the bit line contact 290 are deposited to form a bit line 320 having a stacked structure. In this case, the bit line 320 may be formed in a line type, and the hard mask layer 310 may be formed in a nitride film.

Referring to FIG. 3F, a second insulating layer 330 is formed on the entire surface including the first insulating layer 280 and the bit line 320. After the photoresist layer is formed on the second insulating layer 330, a photoresist pattern (not shown) is formed by exposure and development using a storage node contact mask. Subsequently, the second insulating layer 330 and the first insulating layer 280 are etched using the photoresist pattern as a mask until the lower polysilicon layer 270 is exposed to form a storage node contact region (not shown). A conductive material is filled in the storage node contact region to complete the storage node contact 340.

Here, in the etching process, the second and first insulating layers 330 and 280 having the same reaction to the etching solution are etched to form the storage node contact region, so that an etching target is easy to set, and the storage node An overlap margin of the contact 340 and the lower polysilicon layer 270 increases.

As described above, according to the present invention, by depositing a polysilicon layer between an active region and a storage node contact, an overlap CD (critical dimension) between the active region and the storage node contact is increased to reduce interfacial resistance, and the insulating layer is etched. When the storage node contacts are formed, etching is performed until the lower polysilicon layer is exposed, so it is easy to set an etching target, and self-aligned contact with adjacent bit line contacts generated due to excessive etching. ) There is an advantage to prevent the fail.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

2 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (6)

Forming an isolation layer defining an active region on the semiconductor substrate; Forming a hard mask layer on the entire surface including the device isolation layer; Forming a buried gate having a recess structure; Removing the hard mask layer; Forming a polysilicon layer on the entire surface including the exposed active region, and then planarizing the polysilicon layer; Forming a bit line including a contact on the polysilicon layer; And Forming a storage node contact in contact with the polysilicon layer Method for manufacturing a semiconductor device comprising a. The method of claim 1, The hard mask layer is a method of manufacturing a semiconductor device, characterized in that formed by the oxide (Oxide). The method of claim 1, Forming the bit line Forming a first insulating film on the entire surface including the polysilicon layer; Etching the first insulating layer to form a bit line contact region; Filling a conductive material in the bit line contact region to form a bit line contact; And Forming a bit line on the bit line contact. The method of claim 3, wherein Forming a bit line on the bit line contact And depositing a bit line conductive layer and a hard mask layer on the entire surface including the bit line contacts. The method of claim 1, Forming the storage node contact Forming a second insulating film on the entire surface including the bit line; Etching the second insulating film and the first insulating film until the polysilicon layer is exposed to form a storage node contact region; And Embedding a conductive material in the storage node contact region. The method of claim 1, Forming the buried gate is Etching the hard mask layer, the active region, and the device isolation layer to form a recess; Embedding a conductive layer in the recess; Etching back the conductive layer leaving only a portion in the recess; Forming a nitride film in the recess; And And planarizing etching the nitride layer until the hard mask layer is exposed.

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