KR20060126310A - Semiconductor memory device having cylinder-type storage node and method of manufacturing thereof - Google Patents

Abstract

A semiconductor memory device having a cylindrical storage node is provided to prevent a polysilicon layer from being damaged by a wet etch process by interposing a buffer layer between a storage node layer and a storage node plug such that the buffer layer has corrosion resistance with respect to wet etch chemicals. An insulation layer(20) is formed on a semiconductor substrate(10), having a hole for an electrical contact with the semiconductor substrate. The hole is filled to form a conductive storage node plug. A buffer layer(200a) is formed on the storage node plug. An etch-resistant layer is formed on the insulation layer and the buffer layer, having an opening for exposing a partial surface of the buffer layer. A cylindrical storage node electrically comes in contact with the buffer layer through the opening of the etch-resistant layer, formed on the etch-resistant layer and the buffer layer. An ohmic contact layer(100a) is formed between the buffer layer and the storage node plug.

Description

Semiconductor memory device having a cylindrical storage node and a method for manufacturing the same

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device having a cylindrical storage node according to the prior art.

FIG. 2A is a cross-sectional view illustrating a plug of a single storage node damaged by wet etching. FIG.

2B and 2C are cross-sectional and planar views, respectively, illustrating plugs of several storage nodes damaged by wet etching.

3 is a view schematically showing a cause of a defect in a method of manufacturing a semiconductor memory device according to the prior art.

4A through 4J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device having a cylindrical storage node according to the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor substrate 20 insulating layer

25: first hole 30, 30a: polysilicon layer

40: etching stop layer 50: mold insulating layer

55: second hole 60: storage node

70 capping film 80 dielectric layer

90 upper electrode 100 ohmic contact layer

200: buffer layer

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a cylindrical storage node and a method of manufacturing the same.

Recently, with the development of semiconductor manufacturing process technology, scaling down of large scale integrated circuits (LSIs) has been accelerated. Design rules for semiconductor device manufacturing continue to decrease, requiring cell sizes of orders of 0.1 μm or less.

In the case of DRAM, the area occupied by a capacitor, which is a basic element of a memory cell, is decreasing. However, in order to obtain the required device performance, a memory cell needs to secure a predetermined capacitance, and various techniques have been proposed for this purpose.

A capacitor is a structure having a dielectric layer interposed between a storage node (or lower electrode) and a plate node (plate node, or upper electrode), respectively, and the capacitance is dependent on the surface area of the electrode, particularly the storage electrode, and the dielectric constant of the dielectric layer. Proportional and inversely proportional to the distance between the poles. Recently, in order to secure a large electrode area in a relatively simple process in order to obtain a high capacitance, a technique of forming a storage node in a cylindrical shape has been proposed.

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device having a cylindrical storage node according to the prior art.

Referring to FIG. 1A, an insulating layer 20 is formed on a semiconductor substrate 10, such as a silicon substrate, on which a suitable substructure, for example, a MOS transistor (not shown), a buried contact (not shown), is formed. ) Are stacked and patterned to form a first hole 25 for electrical contact with the buried contact.

Referring to FIG. 1B, a polysilicon layer 30 is formed on the insulating layer 20 to form a plug of the storage node for electrical contact inside the first hole 25 in the insulating layer 20.

Referring to FIG. 1C, an etch back process is performed on the polysilicon layer 30a until the upper surface of the insulating layer is exposed.

Referring to FIG. 1D, an etch stop layer 40 is formed on the insulating layer 20 and the polysilicon layer 30a to protect the insulating layer 20 from subsequent etching processes. For example, the etch stop layer 40 may be formed of silicon nitride.

Referring to FIG. 1E, a mold insulating layer 50 for forming a cylindrical capacitor is stacked on the etch stop layer 40, and patterned in a cylindrical form to form a second hole 55 therein, and to form an etch stop layer. Some surface of 40 is exposed. The mold insulating layer 50 may be formed of silicon oxide, for example, SOG (spin on glass), which is easily wet etched.

Referring to FIG. 1F, the etch stop layer 40 is etched to expose some surfaces of the polysilicon layer 30a so as to electrically contact the storage node.

Referring to FIG. 1G, the storage node 60 is formed on the mold insulating layer 50 and the exposed polysilicon layer 30a. For example, the storage node is formed of a TiN or TiN / Ti layer or the like.

Referring to FIG. 1H, an oxide film having a good charging characteristic is filled into the storage node 60 so that the storage node 60 formed in the second hole 55 is not etched in a subsequent process, thereby filling the capping film 70. Form. For example, the capping film 70 may be formed of USG, FOX, PE-TEOS, BPSG, or the like.

Referring to FIG. 1I, the capping layer 70 and the storage node 60 are exposed until the upper surface of the mold insulating layer 50 is exposed by a process such as etch back or chemical mechanical polishing (CMP). Remove the storage nodes by sequentially removing them.

Referring to FIG. 1J, the mold insulating layer 50 and the remaining capping film 70a are removed. Next, the dielectric layer 80 and the upper electrode 90 are formed on the storage node 60 to complete the capacitor.

In general, as shown in FIG. 1J, the mold insulating layer 50 is removed by wet etching using a hydrofluoric acid (HF) solution. In this case, the polysilicon layer 30a, that is, the underlying layer of the storage node 60, that is, the plug of the storage node is damaged and a defect occurs. Such defects may appear in the unit cell and may appear over several cells.

2A is a cross-sectional view showing a plug of a single storage node damaged by wet etching, and FIGS. 2B and 2C are cross-sectional and plan views showing plugs of several storage nodes damaged by wet etching, respectively.

The enclosed area of FIG. 2A shows a cavity formed by dissolving the polysilicon layer 30a after the wet etching process by HF.

The enclosed region of FIG. 2B shows that the cavity is formed by melting not only the polysilicon layer 30a but also the adjacent insulating layer 20 after the wet etching process by HF. The circumferentially dark areas in FIG. 2C are the damaged capacitor cells shown in FIG. 2B.

3 is a view schematically showing a cause of a defect in a method of manufacturing a semiconductor memory device according to the prior art.

Referring to FIG. 3, although a storage node made of a conventional TiN or TiN / Ti layer is excellent in capacitance or leakage current characteristics, the wet etch cami along the weak interface between the etch stop layer 40a and the Ti or Ti silicide 60 ′. Curl may penetrate (path A), and wet etching chemicals may directly penetrate through the storage node 60 (path B).

Thus, the use of TiN or TiN / Ti storage nodes requires improvements in materials, new structures and manufacturing processes that can effectively inhibit the two penetration pathways of wet etch chemicals.

Accordingly, an object of the present invention is to provide a semiconductor memory device having a cylindrical storage node in which damage to a storage node plug due to a wet etching chemical is suppressed and a method of manufacturing the same.

A semiconductor memory device according to the present invention for achieving the above technical problem, the semiconductor substrate; An insulating layer formed on the semiconductor substrate and having a hole for electrical contact with the semiconductor substrate; A conductive storage node plug formed by filling the hole; A buffer layer formed on the storage node plug; An etch stop layer formed on the insulating layer and the buffer layer and having an opening exposing a portion of the surface of the buffer layer; And a cylindrical storage node in electrical contact with the buffer layer through the opening of the etch stop layer and formed on the etch stop layer and the buffer layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method including: preparing a semiconductor substrate; Forming an insulating layer on the semiconductor substrate, the insulating layer having first holes for electrical contact; Forming a storage node plug to fill the first hole; Forming a buffer layer on the storage node plug; Forming an etch stop layer on the entire surface of the resultant including the buffer layer; Forming a mold insulating layer on the etch stop layer; Etching a predetermined region of the mold insulating layer and the etch stop layer in order to form a second hole exposing the surface of the buffer layer; And forming a cylindrical storage node on an inner wall of the second hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art, and the following examples can be modified in many different forms, and the scope of the present invention is as follows. It is not limited to an Example.

In the drawings, the thicknesses of layers or regions are exaggerated for clarity.

4A through 4J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device having a cylindrical storage node according to the present invention.

Referring to FIG. 4A, the insulating layer 20 is laminated and patterned on a semiconductor substrate 10 on which a suitable substructure, for example, a MOS transistor (not shown) and a buried contact (not shown) are formed. Thus, the first hole 25 for electrical contact with the buried contact is formed.

Referring to FIG. 4B, a polysilicon layer 30 is formed on the insulating layer 20 to form a plug of the storage node for electrical contact inside the first hole 25 in the insulating layer 20.

Referring to FIG. 4C, an etch back process is performed on the polysilicon layer 30a until the upper surface of the insulating layer 20 is exposed.

Preferably, the polysilicon layer 30 is selectively overetched with respect to the insulating layer 20 so that the polysilicon layer 30 is retracted into the first hole 25 of the insulating layer 20 by a predetermined depth. do. As a result, an interface between the buffer layer 200 and the polysilicon layer 30a and the buffer layer 200 of FIG. 4F may be formed in the first hole 25.

Referring to FIG. 4D, an ohmic contact layer 100 is formed on the insulating layer 20 and the polysilicon layer 30a. Preferably, the ohmic contact layer 100 is composed of a transition metal comprising Ti and W and a siliconide of a transition metal comprising TiSi _x and WSi _x . Also, preferably, when the buffer layer 200 of FIG. 4F is a material having ohmic contact characteristics with the polysilicon layer 30a, the process of forming the ohmic contact layer 100 may be omitted.

Referring to FIG. 4E, the buffer layer 200 is formed on the ohmic contact layer 100. Preferably, the buffer layer 200 is formed of a single metal or a material that is corrosion resistant to a wet etching chemical including a metal nitride such as WN _x , TaN, or the like.

Therefore, the semiconductor memory device according to the present invention includes a buffer layer 200 that protects the upper surface of the polysilicon layer 30a. Therefore, as shown in FIG. 1I, the mold insulating layer of FIG. 4H is removed. During the wet etching process, the wet etch chemical passing through the interface between the etch stop layer 40 and the storage node 60 provides an advantage of preventing damage to the polysilicon layer 30a.

Referring to FIG. 4F, a planarization process by chemical mechanical polishing or etch back is performed to form the buffer layer 200a and the ohmic contact layer 100a in the first hole 25 of the insulating layer 20.

Accordingly, in the semiconductor memory device according to the present invention, since the ohmic contact layer 100a is formed before the buffer layer 200a and the etch stop layer 40, the semiconductor memory device 100 may be formed to remove the mold insulating layer 50 of FIG. 4H. Wet etch chemicals provide the advantage of preventing damaging the ohmic contact layer 100a with the polysilicon layer.

Referring to FIG. 4G, an etch stop layer 40 is formed on the insulating layer 20 and the buffer layer 200 to protect the insulating layer 20 from subsequent etching processes. For example, the etch stop layer 40 may be formed of silicon nitride.

Referring to FIG. 4H, a mold insulating layer 50 for forming a storage node is formed on the etch stop layer 40, and patterned in a cylindrical form to form a second hole 55 therein, and to form an etch stop layer ( Some surface of 40) is exposed.

Referring to FIG. 4I, the etch stop layer 40 is etched to expose a portion of the surface of the buffer layer 200a to electrically contact the storage node.

Referring to FIG. 4J, a storage node 60, for example, a TiN or TiN / Ti layer, is formed on the mold insulating layer 50 and the exposed buffer layer 200a.

Therefore, the semiconductor memory device according to the present invention can be applied directly to the TiN layer through the interface between the grains in the TiN layer during the wet etching process of the mold insulation layer, even in the case of a storage node made of a TiN or TiN / Ti layer. It provides an advantage that can be blocked by the buffer layer 200 wet etching chemical that can penetrate through.

Next, as shown in FIG. 1H, an oxide film having a good charging characteristic is filled in the storage node 60 such that the storage node 60 formed in the second hole 55 is not etched in a subsequent process, and thus the capping film 70 is formed. To form. For example, the capping film 70 may be formed of USG, FOX, PE-TEOS, or BPSG.

Next, as illustrated in FIG. 1I, the capping layer 70 and the storage node (until the upper surface of the mold insulating layer 50 is exposed by a process such as etch back or chemical mechanical polishing (CMP)). 60) are removed sequentially to isolate the storage node.

Next, as shown in FIG. 1J, the mold insulating layer 50 and the remaining capping layer 70a are removed by a wet etching process. Next, the dielectric layer 80 and the upper electrode 90 are formed on the storage node 60 to complete the capacitor. Finally, a metal wiring according to what is known in the art may be manufactured to manufacture a semiconductor memory device.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, according to the present invention, by interposing a buffer layer having a corrosion resistance against the wet etching chemical between the storage node layer and the plug of the storage node, it is possible to prevent damage to the polysilicon layer by the wet etching process, thereby making it more reliable. A semiconductor device and a manufacturing process thereof can be provided.

Claims (13)

Semiconductor substrates; An insulating layer formed on the semiconductor substrate and having a hole for electrical contact with the semiconductor substrate; A conductive storage node plug formed by filling the hole; A buffer layer formed on the storage node plug; An etch stop layer formed on the insulating layer and the buffer layer and having an opening exposing a portion of the surface of the buffer layer; And And a cylindrical storage node in electrical contact with the buffer layer through the opening of the etch stop layer and formed on the etch stop layer and the buffer layer. The method of claim 1, And an ohmic contact layer between the storage node plug and the buffer layer. The method of claim 2, The ohmic contact layer is a semiconductor memory device, characterized in that formed of a transition metal containing Ti, W, or a silicon nitride transition metal containing TiSi _x , WSi _x . The method of claim 1, The buffer layer is a material having corrosion resistance to a wet etching chemical, a semiconductor memory device, characterized in that formed of a single metal containing W, Ta, or a metal nitride containing WN _x , TaN. The method of claim 1, The storage node is a semiconductor memory device, characterized in that formed of a TiN or TiN / Ti layer. Preparing a semiconductor substrate; Forming an insulating layer on the semiconductor substrate, the insulating layer having first holes for electrical contact; Forming a storage node plug to fill the first hole; Forming a buffer layer on the storage node plug; Forming an etch stop layer on the entire surface of the resultant including the buffer layer; Forming a mold insulating layer on the etch stop layer; Etching second portions of the mold insulating layer and the etch stop layer in order to form second holes exposing the surface of the buffer layer; And, Forming a cylindrical storage node on an inner wall of the second hole. The method of claim 6, The storage node plug deposits a polysilicon layer on the entire surface of the resultant including the first hole, selectively overetches the polysilicon layer with respect to the insulating layer, and stores the polysilicon layer over a predetermined depth into the first hole. A method of manufacturing a semiconductor memory device, characterized in that the surface of the node plug is retracted. The method of claim 6, After forming the storage node plug, forming an ohmic contact layer on the storage node plug. The method of claim 8, The ohmic contact layer is a method of manufacturing a semiconductor memory device, characterized in that made of a transition metal containing Ti, W, or a siliconized transition metal containing TiSi _x , WSi _x . The method of claim 6, The forming of the buffer layer includes applying a buffer layer over the entire surface of the resultant including the storage node plug, and planarizing the buffer layer material until the insulator layer is exposed. Method of preparation. The method of claim 10, Planarizing the buffer layer material is performed by a chemical mechanical polishing process or an etch back process. The method of claim 6, The buffer layer is a method of manufacturing a semiconductor memory device, characterized in that formed of a single metal or a material having corrosion resistance to a wet etching chemical containing a metal nitride such as WN _x , TaN and the like.  The method of claim 6, The storage node is a method of manufacturing a semiconductor memory device, characterized in that formed of a TiN or TiN / Ti layer.

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