KR101076813B1 - Semiconductor Device and Method for Manufacturing the same - Google Patents

Abstract

According to an exemplary embodiment of the present invention, a first storage node contact may be formed by using a mask in which two outer regions of different active regions are exposed at one time, thereby securing an overlap margin of the first storage node contact and the active region. In addition, by forming a second storage node contact in a line type on the first storage node contact, a short with a bit line contact can be prevented, and an upper CD of the second storage node contact It provides a semiconductor device and a method of manufacturing the same that can secure the critical dimension (maximum) to improve the resistance with the lower electrode formed during subsequent processes.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same, which can prevent a margin of a storage node contact and a short circuit with a bit line in manufacturing a highly integrated semiconductor device.

A semiconductor is a class of materials according to electrical conductivity, and is a material belonging to an intermediate region of a conductor and a non-conductor. The semiconductor is used to add semiconductor impurities and connect conductors to create semiconductor devices such as transistors. A device that performs various functions such as data storage using such a semiconductor device is called a semiconductor device.

As the semiconductor devices are increasingly integrated, semiconductor chip sizes are reduced, and thus, the size of a plurality of semiconductor devices formed in the chip is also reduced.

1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, an active region 110 having a bar-shaped 6F2 structure is arranged and arranged in an island type on a semiconductor substrate 100, and a device isolation layer is formed in the region between the active regions 110. (Not shown) is formed.

Next, a gate 120 intersecting in an oblique direction with respect to the longitudinal direction of the active region 110 is formed. The plurality of gates 120 divides one active region 110 into three portions, and first storage node contacts 130 are formed at both outer regions of the active region 110 exposed between the gates 120, respectively, The bit line contact 140 is formed therein. In this case, the first storage node contact 130 is formed in a hole type.

Next, a bit line 150 is formed on the bit line contact 140. At this time, the bit line 150 has a line structure.

Thereafter, a second storage node contact 160 is formed on the first storage node contact 130. In this case, the second storage node contact 160 is formed in a hole type.

In the above-described method of manufacturing a semiconductor device, since the first and second storage node contacts are all formed in a hole type, they cannot be implemented in a highly integrated semiconductor device of 30 nm or less, and the storage node contact (SNC) and the active In order to improve a region's overlap margin, if a CD is formed to have a large critical dimension, adjacent bit line contacts and self-aligned contact (SAC) fail may occur.

In order to solve the above-mentioned problems, the present invention forms a first storage node contact by using a mask in which both outer sides of the different active areas are exposed at one time, thereby forming the first storage node contact and the active area. It is possible to secure an overlap margin of, and by forming a second storage node contact in a line type on the first storage node contact, it is possible to prevent a short with the bit line contact. Provided are a semiconductor device and a method of manufacturing the same, which can improve resistance to a lower electrode formed during a subsequent process by securing the upper critical dimension of the second storage node contact to the maximum.

The present invention provides a semiconductor device including a first storage node contact having a hole structure formed on a semiconductor substrate and a second storage node contact having a line structure formed on the first storage node contact.

The present invention also provides a method of forming an isolation layer defining an active region on a semiconductor substrate, forming an insulating layer on the entire surface including the active region, and etching the insulating layer using a first storage node contact mask. Forming a storage node contact region, filling a conductive material in the first storage node contact region to form a first storage node contact, and forming a second storage node contact in a line structure on the first storage node contact It provides a method for manufacturing a semiconductor device comprising the step of.

Preferably, the first storage node contact mask may etch the insulating layer so that both outer regions of different active regions are exposed at once.

Preferably, the method further comprises embedding the conductive material, followed by etching or etching the conductive material.

The forming of the second storage node contact may include forming a second storage node contact region by partially etching the first storage node contact and the insulating layer, and forming a conductive material on the second storage node contact region. Involves landfilling.

According to an exemplary embodiment of the present invention, a first storage node contact may be formed by using a mask in which two outer regions of different active regions are exposed at one time, thereby securing an overlap margin of the first storage node contact and the active region. In addition, by forming a second storage node contact in a line type on the first storage node contact, a short with a bit line contact can be prevented, and an upper CD of the second storage node contact Critical Dimension) has the advantage of improving the resistance with the lower electrode formed during the subsequent process to maximize the.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2, an active region 310 having a bar-like 6F2 structure is arranged and arranged in an island type on a semiconductor substrate 300, and a device isolation layer is formed in the region between the active regions 310. (Not shown) is formed.

Next, a gate 320 intersecting in an oblique direction with respect to the longitudinal direction of the active region 310 is formed. The plurality of gates 320 divides one active region 310 into three parts, and first storage node contacts 370 are formed in both outer regions of the active region 310 exposed between the gates 320. The bit line contact 340 is formed at the center of the active region 310. Thereafter, a bit line 350 perpendicular to the gate 320 is formed on the bit line contact 340. At this time, the bit line 350 is preferably a line structure.

Here, when forming the first storage node contact 370, it is preferable to use an elliptical mask that exposes the outer regions of the different active regions 310 at once as shown in FIG. 2.

Thereafter, a second storage node contact 380 is formed on the first storage node contact 370. In this case, the second storage node contact 380 may be formed in a line structure.

3A to 3D are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention, and illustrate a cross-sectional view taken along line A-A 'of FIG.

Referring to FIG. 3A, an isolation layer 320 defining an active region 310 is formed on a semiconductor substrate 300. In this case, the device isolation layer 320 is preferably formed of a high density plasma (HDP) oxide film through a shallow trench isolation (STI) process. Although not shown, after the photoresist film is formed on the entire surface including the device isolation layer 320, the photoresist pattern is formed by an exposure and development process using a recess mask. The recess is formed by etching the active region 310 and the device isolation layer 320 using the photoresist pattern as a mask. A buried gate (not shown) is formed by filling a conductive material in the recess.

Next, after forming the first interlayer insulating layer 330 on the entire surface including the buried gate, the bit line contact region (not shown) for etching the first interlayer insulating layer 330 to expose the active region 310. To form. Subsequently, after the conductive material is filled in the bit line contact region, the bit line contact 340 is completed by planarization etching.

Next, a bit line 350 including a conductive layer 345 and a hard mask layer 355 is formed on the bit line contact 340.

Next, a second interlayer insulating layer 360 is formed on the entire surface including the bit line 350. Subsequently, after the photoresist layer is formed on the second interlayer insulating layer 360, a photoresist pattern (not shown) is formed by an exposure and development process using a first storage node contact mask. The second interlayer insulating layer 360 and the first interlayer insulating layer 330 are etched to form a first storage node contact region (not shown) using the photoresist pattern as a mask until the active region 310 is exposed. In this case, a first storage node contact mask is used to form the first storage node contact region, and an elliptical shape that exposes the outer regions of different active regions 310 at one time instead of the existing hole type is formed. desirable.

Here, when the second and first interlayer insulating layers 360 and 330 are etched by using the first storage node contact mask until the active region 310 is exposed, the lower bit line 350 may be formed of a hard mask layer ( The first storage node contact region is formed by performing a self-aligned contact (SAC) process using an etch selectivity difference between the hard mask layer 355 and the interlayer insulating layers 360 and 330 because of being surrounded by 355. can do. The method of forming the first storage node contact region through the SAC process may improve an overlap margin with the lower active region 310.

Next, after the conductive material is buried in the entire surface including the first storage node contact region, the first storage node contact 370 is formed by etching or planar etching.

3B and 3C, after forming a photoresist film on the entire surface including the first storage node contact 370, a photoresist pattern (not shown) is formed by an exposure and development process using a second storage node contact mask. . The second interlayer insulating layer 360 and the first storage node contact 370 are partially removed using a photoresist pattern as a mask to form a second storage node contact region (not shown). In this case, the second storage node contact region may be formed in a line structure.

After the insulating layer is partially deposited to form the second storage node contact region, the interlayer insulating layer 360 and the first storage node contact 370 are partially removed by an etch back process, and then a conductive material is removed from the second storage node. By depositing in the node contact region, the conventional insulating film deposition and etching process steps can be reduced, and since the insulating film etching process is not performed, a short with the lower bit line 350 can be prevented. .

Referring to FIG. 3D, after depositing a conductive material on the second storage node contact region, the conductive material is etched back or by chemical mechanical polishing to form a second storage node contact 380. At this time, since the upper CD of the second storage node contact 380 formed in the line-shaped second storage node contact region is wider than the contact of the conventional hole structure, the resistance with the lower electrode formed during the subsequent process is increased. It can be improved.

As described above, the present invention forms a first storage node contact by using a mask in which both outer sides of the different active regions are exposed at one time, thereby overlapping the margin between the first storage node contact and the active region. ), And by forming a second storage node contact in a line type on the first storage node contact, a short with a bit line contact can be prevented, and the second storage node The upper CD (Critical Dimension) of the contact as possible to secure the maximum has the advantage of improving the resistance with the lower electrode formed during the subsequent process.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a plan view showing a semiconductor device and a method of manufacturing the same according to the prior art.

2 is a plan view showing a semiconductor device and a manufacturing method according to the present invention.

3A to 3C are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

Claims (5)

delete Forming an isolation layer defining an active region on the semiconductor substrate; Forming an insulating film on the entire surface including the active region; Forming a first storage node contact region by etching the insulating layer using a first storage node contact mask so that both outer regions of the different active regions are exposed at one time; Filling a first storage node contact with a conductive material in the first storage node contact region; And Forming a second storage node contact in a line structure on the first storage node contact; Wherein the semiconductor device is a semiconductor device. delete Claim 4 was abandoned when the registration fee was paid. The method of claim 2, After the filling of the conductive material, the method of manufacturing a semiconductor device further comprising the etching (Etchback) or planar etching (Chemical Mechanical Polishing). Claim 5 was abandoned upon payment of a set-up fee. The method of claim 2, The forming of the second storage node contact may include Partially etching the first storage node contact and the insulating layer to form a second storage node contact region; And And embedding a conductive material in the second storage node contact region.

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