JP2000031439A - Soi substrate and its manufacture - Google Patents
Soi substrate and its manufactureInfo
- Publication number
- JP2000031439A JP2000031439A JP19687598A JP19687598A JP2000031439A JP 2000031439 A JP2000031439 A JP 2000031439A JP 19687598 A JP19687598 A JP 19687598A JP 19687598 A JP19687598 A JP 19687598A JP 2000031439 A JP2000031439 A JP 2000031439A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- silicon substrate
- substrate
- insulating layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 98
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 98
- 239000010703 silicon Substances 0.000 claims abstract description 98
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 29
- 239000001301 oxygen Substances 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000007547 defect Effects 0.000 abstract description 20
- 239000004065 semiconductor Substances 0.000 abstract description 20
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 11
- 238000005247 gettering Methods 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000001556 precipitation Methods 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 210000004940 nucleus Anatomy 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 60
- 235000012431 wafers Nutrition 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 125000004430 oxygen atom Chemical group O* 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 239000002244 precipitate Substances 0.000 description 4
- 238000011109 contamination Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、シリコン基板上
に絶縁層を介してシリコン層を形成したＳＯＩ基板とそ
の製造方法に関する。The present invention relates to an SOI substrate in which a silicon layer is formed on a silicon substrate via an insulating layer, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置の製造プロセスでは、製造工
程中に起こる重金属汚染に起因したｐｎ接合での漏れ電
流の増大（接合リークと言われている）やゲート酸化膜
の耐圧劣化などが発生する。重金属汚染による半導体装
置の前記特性劣化の対策として、いくつかのゲッタリン
グ技術が用いられている。通常、ＣＺ引き揚げ法によっ
て製造されたシリコンウエハでは、ウエハ内に含まれる
酸素の析出を利用したイントリンシックゲッタリング技
術が用いられる。シリコンウエハに１０００℃〜１２０
０℃の熱処理を施しこのシリコンウエハの表面の酸素原
子を外方拡散させて、表面濃度を低減し、その後で、６
００℃〜９００℃の熱処理により、シリコンウエハ中の
酸素原子は析出核を形成する。さらに、９００℃〜１２
００℃の熱処理を施すことにより、表面から１０μｍ〜
５０μｍ内部に微小欠陥や積層欠陥を形成する。2. Description of the Related Art In a semiconductor device manufacturing process, an increase in leakage current at a pn junction due to heavy metal contamination occurring during the manufacturing process (referred to as junction leakage) and deterioration in breakdown voltage of a gate oxide film occur. . As a countermeasure against the above-mentioned deterioration of the characteristics of the semiconductor device due to heavy metal contamination, several gettering techniques are used. Normally, for silicon wafers manufactured by the CZ pulling method, an intrinsic gettering technique utilizing precipitation of oxygen contained in the wafer is used. 1000 ° C ~ 120 for silicon wafer
A heat treatment of 0 ° C. is performed to diffuse out oxygen atoms on the surface of the silicon wafer to reduce the surface concentration.
Oxygen atoms in the silicon wafer form precipitate nuclei by the heat treatment at 00 ° C. to 900 ° C. In addition, 900 ° C ~ 12
By applying a heat treatment at 00 ° C., from the surface to 10 μm
Fine defects and stacking faults are formed within 50 μm.
【０００３】これらの欠陥は歪み場を形成し、重金属不
純物原子を固着しやすい特性を有している。素子を形成
するウエハ表面の酸素濃度を外方拡散により低減し、且
つ、ウエハ内部には酸素の析出を起こして重金属を固着
させる手法が、前記のイントリンシックゲッタリングと
呼ばれている。近年、低耐圧の制御回路と高耐圧の出力
回路を１チップ内に形成するパワーＩＣや高速動作ＬＳ
Ｉにおいて、分離面積や寄生効果の低減に効果があるＳ
ＯＩ基板が利用されている。[0003] These defects form a strain field, and have a characteristic of easily fixing heavy metal impurity atoms. A method of reducing the oxygen concentration on the surface of the wafer on which elements are formed by outward diffusion and causing the precipitation of oxygen inside the wafer to fix the heavy metal is called the intrinsic gettering. In recent years, power ICs and high-speed operation LSs in which a low breakdown voltage control circuit and a high breakdown voltage output circuit are formed in one chip
In I, S is effective in reducing the separation area and the parasitic effect.
An OI substrate is used.
【０００４】ＳＯＩ基板は、シリコン基板上に絶縁層を
介してシリコン層を形成した構造となっている。素子を
形成するシリコン層はＳＯＩ基板の製造工程の熱処理に
より、酸素濃度が５×１０17ｃｍ-3以下に減少するため
に、このシリコン層中には酸素の析出は起こらない。従
って、シリコン層内には重金属不純物は固着されない。[0004] The SOI substrate has a structure in which a silicon layer is formed on a silicon substrate via an insulating layer. Since the oxygen concentration of the silicon layer forming the element is reduced to 5 × 10 17 cm −3 or less by the heat treatment in the manufacturing process of the SOI substrate, no oxygen precipitates in the silicon layer. Therefore, heavy metal impurities are not fixed in the silicon layer.
【０００５】また、シリコン中に比べると、重金属不純
物は絶縁層中を拡散しにくい。シリコン層の重金属不純
物が絶縁層を通過してシリコン基板に固着させるために
は、シリコン基板のゲッタリング能力を大幅に高める必
要がある。公開公報である特開平２−４６７７０号や特
開平８−７８６４６号で、半導体素子を形成するシリコ
ン層の酸素濃度を１０17ｃｍ-3以下とし、酸素に起因す
る欠陥を低減し、接合リークやゲート酸化膜の耐圧劣化
を改善する方法が開示されている。[0005] Compared with silicon, heavy metal impurities are less likely to diffuse in the insulating layer. In order for heavy metal impurities in the silicon layer to pass through the insulating layer and adhere to the silicon substrate, it is necessary to greatly increase the gettering ability of the silicon substrate. In Japanese Patent Application Laid-Open Nos. 2-46770 and 8-78646, the oxygen concentration of a silicon layer forming a semiconductor element is set to 10 17 cm -3 or less, defects caused by oxygen are reduced, and junction leakage and A method for improving the deterioration of the breakdown voltage of the gate oxide film is disclosed.
【０００６】また、シリコン基板の酸素濃度が低下する
と、機械的強度が低下し、シリコン基板の反りが増大す
る。これを防止するために、シリコン層を支持するシリ
コン基板の酸素濃度は特開平２−４６７７０号では１０
17ｃｍ-3〜１０19ｃｍ-3、特開平８−７８６４６号では
１．０×１０18ｃｍ-3〜５×１０18ｃｍ-3と規定されて
いる。さらに、特開平２−４６７７０号では、シリコン
層の酸素濃度を低減するために、第１のシリコン基板と
第２のシリコン基板を絶縁層を介して結合した後、第２
のシリコン基板を研削研磨して、シリコン層とする研削
研磨工程の前に、４００℃〜９００℃の熱処理を施し、
第２のシリコン基板内の酸素原子を絶縁層または絶縁層
界面へ拡散させている。When the oxygen concentration of the silicon substrate decreases, the mechanical strength decreases, and the warpage of the silicon substrate increases. In order to prevent this, the oxygen concentration of the silicon substrate supporting the silicon layer is set to 10
It is specified as 17 cm -3 to 10 19 cm -3 and in Japanese Patent Application Laid-Open No. 8-78646 as 1.0 × 10 18 cm -3 to 5 × 10 18 cm -3 . Further, in Japanese Patent Application Laid-Open No. 2-46770, in order to reduce the oxygen concentration in the silicon layer, the first silicon substrate and the second silicon substrate are bonded via an insulating layer, and then the second silicon substrate is bonded to the second silicon substrate.
Before the grinding and polishing step of grinding and polishing the silicon substrate to form a silicon layer, a heat treatment at 400 ° C. to 900 ° C. is performed.
Oxygen atoms in the second silicon substrate are diffused into the insulating layer or the insulating layer interface.
【０００７】[0007]
【発明が解決しようとする課題】前記の公開公報である
特開平２−４６７７０号や特開平８−７８６４６号で
は、半導体素子を形成するシリコン層に含まれる酸素に
起因する欠陥や電気的特性の不具合を改善するために、
シリコン層の酸素濃度を前記のように規定している。ま
た、シリコン基板とシリコン層を絶縁層を介して結合し
てなるＳＯＩ基板の機械的強度を向上させるためにシリ
コン基板の酸素濃度を前記のように規定している。The above-mentioned publications, JP-A-2-46770 and JP-A-8-78646, describe defects and electrical characteristics caused by oxygen contained in a silicon layer forming a semiconductor element. To improve the bug,
The oxygen concentration of the silicon layer is defined as described above. Further, the oxygen concentration of the silicon substrate is specified as described above in order to improve the mechanical strength of the SOI substrate formed by connecting the silicon substrate and the silicon layer via an insulating layer.
【０００８】さらに、特開平８−７８６４６号では、シ
リコン層の酸素濃度を低減するために、シリコン基板と
シリコン層を絶縁膜を介して結合した後で、４００℃〜
９００℃の熱処理を施している。この熱処理は前記のイ
ントリンシックゲッタリング技術の析出核形成の熱処理
に相当するが、シリコン基板とシリコン層を絶縁膜を介
して結合した後で当該熱処理を施した場合、シリコン層
中にも酸素原子の析出核が形成され、形成された半導体
素子の電気的特性の改善は十分にはできない。Further, in Japanese Patent Application Laid-Open No. 8-78646, in order to reduce the oxygen concentration in the silicon layer, the silicon substrate is bonded to the silicon layer via an insulating film and then heated to 400 ° C.
A heat treatment at 900 ° C. is performed. This heat treatment corresponds to the heat treatment for the formation of precipitation nuclei in the intrinsic gettering technique. However, when the heat treatment is performed after the silicon substrate and the silicon layer are bonded via an insulating film, oxygen atoms are also present in the silicon layer. Precipitate nuclei are formed, and the electrical characteristics of the formed semiconductor element cannot be sufficiently improved.
【０００９】また、絶縁層とシリコン基板またはシリコ
ン層との結合界面に欠陥が多量に析出するため、結合界
面近傍の機械的強度が低下するために、半導体素子形成
工程で界面近傍から剥離が起こる。この発明の目的は、
前記の課題を解決し、半導体素子の形成において、ゲッ
タリング能力が強く、機械的強度が強いＳＯＩ基板とそ
の製造方法を提供することにある。In addition, since a large amount of defects precipitate at the bonding interface between the insulating layer and the silicon substrate or the silicon layer, the mechanical strength near the bonding interface is reduced. . The purpose of this invention is
An object of the present invention is to provide an SOI substrate having a high gettering ability and a high mechanical strength in forming a semiconductor element, and a method for manufacturing the same.
【００１０】[0010]
【課題を解決するための手段】前記の目的を達成するた
めに、シリコン基板上に絶縁層を介してシリコン層を形
成したＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔ
ｏｒ）基板において、シリコン基板の酸素濃度を１．５
×１０18ｃｍ-3以上とする。前記シリコン基板を６００
℃ないし８００℃の範囲で、所定の時間熱処理する工程
と、前記工程の後で、前記シリコン基板上に前記絶縁層
を形成する工程と、前記絶縁層上に前記シリコン層を形
成する工程を含む工程とする。In order to achieve the above object, an SOI (silicon on insulator) in which a silicon layer is formed on a silicon substrate via an insulating layer.
or) the substrate has an oxygen concentration of 1.5
× 10 18 cm -3 or more. The silicon substrate is
A step of performing a heat treatment at a temperature in a range of from about 800 ° C. to about 800 ° C. for a predetermined time; a step of forming the insulating layer on the silicon substrate after the step; and a step of forming the silicon layer on the insulating layer Process.
【００１１】前記所定の時間が１０分以上であるとよ
い。このように、支持体であるシリコン基板に含まれる
酸素濃度を最適化することで、重金属不純物のゲッタリ
ングと絶縁層との界面の機械的強度を強くする。Preferably, the predetermined time is 10 minutes or more. As described above, by optimizing the concentration of oxygen contained in the silicon substrate serving as the support, the mechanical strength of the interface between the gettering of heavy metal impurities and the insulating layer is increased.
【００１２】[0012]
【発明の実施の形態】図１はこの発明の第１実施例のＳ
ＯＩ基板の要部断面図である。シリコン基板１上に厚さ
１μｍ〜２μｍの絶縁層２を形成し、この絶縁層２上に
１０μｍ程度のシリコン層３を形成し、ＳＯＩ基板とな
る。シリコン基板１中の酸素濃度を１．５×１０18ｃｍ
-3以上とする。シリコン基板１は、絶縁層２と結合する
表面側と裏面側に１０μｍ〜２０μｍの深さまで、無欠
陥層５、６が拡がり、また、中央部には酸素に起因する
欠陥層４が存在する。FIG. 1 shows a first embodiment of the present invention.
It is principal part sectional drawing of an OI board. An insulating layer 2 having a thickness of 1 μm to 2 μm is formed on a silicon substrate 1 and a silicon layer 3 having a thickness of about 10 μm is formed on the insulating layer 2 to form an SOI substrate. The oxygen concentration in the silicon substrate 1 is 1.5 × 10 18 cm
-3 or more. In the silicon substrate 1, the defect-free layers 5 and 6 extend to a depth of 10 μm to 20 μm on the front surface side and the rear surface side bonded to the insulating layer 2, and a defect layer 4 caused by oxygen exists in the center.
【００１３】図２はこの発明の第２実施例のＳＯＩ基板
の製造工程で、同図（ａ）から同図（ｃ）は工程順に示
した要部工程断面図である。同図（ａ）において、ＣＺ
法で形成された酸素濃度１．５×１０18ｃｍ-3以上のシ
リコン基板１と、半導体素子を形成するシリコン層３と
なる第２のシリコン基板８を準備する。この酸素濃度の
上限はシリコンに対する酸素の固溶度により規定され
る。シリコン基板１は予め６００℃〜９００℃、１０分
以上（１時間程度が望ましい）の熱処理をして、欠陥の
析出核１１を形成しておく。一方第２のシリコン基板８
の表面層に１μｍ〜２μｍの絶縁層２、７を形成する。
同図（ｂ）において、シリコン基板１と第２のシリコン
基板８を絶縁層２を介して接触させ、１０００℃以上の
高温で２時間程度、熱処理を施こし、シリコン基板１と
第２のシリコン基板８を絶縁層２を介して結合する。こ
の熱処理でシリコン基板１の析出核１１に酸素原子が集
まり、結晶欠陥１２を形成する。同図（ｃ）において、
第２のシリコン基板８を、例えば５μｍ〜１０μｍ程度
の厚さに研磨部１３を研磨、除去し、シリコン層３とす
る。シリコン基板１と絶縁層２およびシリコン層３で構
成されるＳＯＩ基板１００が出来上がる。このＳＯＩ基
板１００は、シリコン基板１に多量の結晶欠陥１２を有
しており、シリコン層３に半導体素子を形成する場合、
シリコン層３に含まれる重金属不純物をゲッタリングす
る作用をして、接合リークやゲート耐圧の劣化を防止す
る。FIGS. 2A to 2C are cross-sectional views of a main part of a SOI substrate according to a second embodiment of the present invention. In FIG.
A silicon substrate 1 formed by a method and having an oxygen concentration of 1.5 × 10 18 cm −3 or more and a second silicon substrate 8 serving as a silicon layer 3 for forming a semiconductor element are prepared. The upper limit of the oxygen concentration is determined by the solid solubility of oxygen in silicon. The silicon substrate 1 is preliminarily subjected to a heat treatment at 600 ° C. to 900 ° C. for 10 minutes or more (preferably about 1 hour) to form defect nuclei 11. On the other hand, the second silicon substrate 8
The insulating layers 2 and 7 having a thickness of 1 μm to 2 μm are formed on the surface layer.
In FIG. 2B, the silicon substrate 1 and the second silicon substrate 8 are brought into contact with each other via the insulating layer 2 and subjected to a heat treatment at a high temperature of 1000 ° C. or more for about 2 hours. The substrate 8 is bonded via the insulating layer 2. Oxygen atoms collect in the precipitation nuclei 11 of the silicon substrate 1 by this heat treatment, and crystal defects 12 are formed. In FIG.
The polishing portion 13 is polished and removed from the second silicon substrate 8 to a thickness of, for example, about 5 μm to 10 μm to form the silicon layer 3. The SOI substrate 100 including the silicon substrate 1, the insulating layer 2, and the silicon layer 3 is completed. This SOI substrate 100 has a large number of crystal defects 12 in the silicon substrate 1, and when a semiconductor element is formed in the silicon layer 3,
It acts to getter heavy metal impurities contained in the silicon layer 3 to prevent junction leakage and deterioration of gate breakdown voltage.
【００１４】表１はシリコン基板内の酸素濃度と欠陥密
度およびＢモード不良率およびＣモード（良品率）の関
係を示したものである。Table 1 shows the relationship between the oxygen concentration in the silicon substrate, the defect density, the B-mode defect rate, and the C-mode (non-defective rate).
【００１５】[0015]
【表１】 通常、ゲート酸化膜の絶縁破壊強度は、破壊電圧を膜厚
で割った電界強度で表され、２ＭＶ／ｃｍより低いもの
をＡモード不良、２〜８ＭＶ／ｃｍの範囲のものをＢモ
ード不良、８ＭＶ／ｃｍより高いものをＣモード（良
品）と定義されている。Ａモード不良は、初期不良で半
導体素子の定格特性試験で、検知可能な不良である。Ｂ
モード不良は、ゲート酸化膜中に重金属不純物などの欠
陥が導入され、Ａモード不良のように定格特性試験では
検知できず、長期信頼性試験で検知される不良である。[Table 1] In general, the breakdown strength of a gate oxide film is represented by an electric field strength obtained by dividing a breakdown voltage by a film thickness. A breakdown voltage lower than 2 MV / cm is A-mode failure, a breakdown voltage of 2 to 8 MV / cm is a B-mode failure, Those higher than 8 MV / cm are defined as C mode (good). An A-mode failure is an initial failure that can be detected in a rated characteristic test of a semiconductor device. B
The mode failure is a failure in which a defect such as a heavy metal impurity is introduced into the gate oxide film, which cannot be detected by the rated characteristic test like the A-mode failure, but is detected by the long-term reliability test.
【００１６】表１に示すＢモード不良率は５００個の素
子についてゲート耐圧を測定し、電界強度が２〜８ＭＶ
／ｃｍの範囲にある素子の割合を示している。また測定
方法としては、０．５×０．５ｍｍ2 のシリコン層３上
に２５ｎｍ厚のゲート酸化膜を形成したＭＯＳデバイス
を作製し、このＭＯＳデバイスのゲート酸化膜に電圧を
印加して、漏れ電流を測定する。この漏れ電流が２５０
ｎＡになる電圧を破壊耐圧とする。The B-mode failure rate shown in Table 1 was obtained by measuring the gate breakdown voltage of 500 elements and finding that the electric field strength was 2 to 8 MV.
The ratio of the element in the range of / cm is shown. As a measurement method, a MOS device in which a gate oxide film having a thickness of 25 nm is formed on a silicon layer 3 of 0.5 × 0.5 mm 2 is manufactured, and a voltage is applied to the gate oxide film of the MOS device. Measure the current. This leakage current is 250
The voltage that becomes nA is defined as the breakdown voltage.
【００１７】シリコン基板の酸素濃度が１．４×１０18
ｃｍ-3の場合、半導体素子形成後のシリコン層中の欠陥
密度は５．０×１０5 ｃｍ-3でＢモード不良率は９０％
以上であった。また、酸素濃度が１．５×１０18ｃｍ-3
の場合、欠陥密度は２倍となり、Ｂモード不良率は０％
となり、Ｃモード（良品率）は１００％となった。その
ため、シリコン基板中の酸素濃度は１．５×１０18ｃｍ
-3以上が望ましい このように、この発明のＳＯＩ基板
を用いると、半導体素子の信頼性が向上し、また良品率
が高くなり、量産性も向上する。The oxygen concentration of the silicon substrate is 1.4 × 10 18
cm -3 , the defect density in the silicon layer after forming the semiconductor element is 5.0 × 10 5 cm -3 , and the B-mode defect rate is 90%.
That was all. Further, when the oxygen concentration is 1.5 × 10 18 cm −3
, The defect density is doubled and the B-mode defect rate is 0%
And the C mode (non-defective rate) was 100%. Therefore, the oxygen concentration in the silicon substrate is 1.5 × 10 18 cm
-3 As the above is desired, the use of SOI substrate of the present invention improves the reliability of the semiconductor device, also increases the yield rate is also improved mass productivity.
【００１８】図３はこの発明のＳＯＩ基板を用いた半導
体装置の要部断面図で、同図（ａ）は自己分離型の半導
体装置、同図（ｂ）は誘電体分離型の半導体装置であ
る。同図（ａ）において、ＳＯＩ基板１００のシリコン
層３にｐチャネルＭＯＳＦＥＴ２１とｎチャネルＭＯＳ
ＦＥＴ２２が形成されている。これらのｐチャネルＭＯ
ＳＦＥＴ２１およびｎチャネルＭＯＳＦＥＴ２２を他の
素子から分離する方法は、所定の距離を離すことで互い
が分離される自己分離型である。同図（ｂ）において、
ＳＯＩ基板１００のシリコン層３に、素子間を分離する
分離領域２６が誘電体で形成される誘電体分離構造で、
この分離されたシリコン層３ａにｐチャネルＭＯＳＦＥ
Ｔ２１およびｎチャネルＭＯＳＦＥＴ２２が形成され、
他の素子から分離される。尚、２３は素子間を分離し、
耐圧を確保するフィールド酸化膜、２４は層間絶縁膜、
２５は素子分離のための分離領域にポリシリコンなどが
充填される充填層、２６は素子間を分離する分離領域で
ある。FIGS. 3A and 3B are cross-sectional views of main parts of a semiconductor device using an SOI substrate according to the present invention. FIG. 3A is a self-separation type semiconductor device, and FIG. 3B is a dielectric separation type semiconductor device. is there. In FIG. 1A, a p-channel MOSFET 21 and an n-channel MOS
An FET 22 is formed. These p-channel MOs
The method of separating the SFET 21 and the n-channel MOSFET 22 from other elements is a self-isolation type in which the SFET 21 and the n-channel MOSFET 22 are separated from each other by a predetermined distance. In FIG.
In the silicon layer 3 of the SOI substrate 100, a dielectric isolation structure in which an isolation region 26 for isolating elements is formed of a dielectric,
A p-channel MOSFE is formed on the separated silicon layer 3a.
T21 and n-channel MOSFET 22 are formed,
Isolated from other elements. 23 separates the elements,
A field oxide film for securing a withstand voltage, 24 an interlayer insulating film,
Reference numeral 25 denotes a filling layer in which an isolation region for element isolation is filled with polysilicon or the like, and reference numeral 26 denotes an isolation region for isolating elements.
【００１９】この例では形成される素子をｐチャネルＭ
ＯＳＦＥＴ２１およびｎチャネルＭＯＳＦＥＴ２２を例
としたが、他に、バイポーラトランジスタや高耐圧素
子、およびこれらの素子の組合せて、このＳＯＩ基板１
００に形成してもよい。In this example, the element to be formed is a p-channel M
Although the OSFET 21 and the n-channel MOSFET 22 are taken as examples, the SOI substrate 1 may be replaced with a bipolar transistor, a high breakdown voltage element, or a combination of these elements.
00 may be formed.
【００２０】[0020]
【発明の効果】この発明によれば、ＳＯＩ基板を製作す
る過程で、シリコン基板の酸素濃度を１．５×１０18ｃ
ｍ-3以上とし、シリコン層を絶縁層を介して結合する前
に、６００℃から９００℃、１０分以上の熱処理を施す
ことで、シリコン層に形成される半導体素子の接合リー
クを減少させ、ゲート耐圧の劣化を防止できる。そのこ
とによって、半導体素子の信頼性は向上し、また、量産
性も向上できる。According to the present invention, in the process of manufacturing an SOI substrate, the oxygen concentration of the silicon substrate is set to 1.5 × 10 18 c
m −3 or more, and before the silicon layer is bonded via the insulating layer, a heat treatment is performed at 600 ° C. to 900 ° C. for 10 minutes or more to reduce junction leakage of a semiconductor element formed in the silicon layer. Deterioration of gate breakdown voltage can be prevented. Thereby, the reliability of the semiconductor element is improved, and the mass productivity can be improved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】この発明の第１実施例のＳＯＩ基板の要部断面
図FIG. 1 is a sectional view of a main part of an SOI substrate according to a first embodiment of the present invention;
【図２】この発明の第２実施例のＳＯＩ基板の製造工程
で、同図（ａ）から同図（ｃ）は工程順に示した要部工
程断面図FIGS. 2A to 2C are cross-sectional views of a main part process in a manufacturing order of a SOI substrate according to a second embodiment of the present invention shown in the order of steps; FIGS.
【図３】この発明のＳＯＩ基板を用いた半導体装置の要
部断面図で、同図（ａ）は自己分離型の半導体装置、同
図（ｂ）は誘電体分離型の半導体装置を示した図FIGS. 3A and 3B are main-portion cross-sectional views of a semiconductor device using an SOI substrate according to the present invention, wherein FIG. 3A shows a self-separation type semiconductor device and FIG. 3B shows a dielectric separation type semiconductor device; Figure
１ シリコン基板 ２、７ 絶縁層 ３、３ａ シリコン層 ４ 欠陥層 ５、６ 無欠陥層 ８ 第２のシリコン基板 １１ 析出核 １２ 結晶欠陥 １３ 研磨部 ２１ ｐチャネルＭＯＳＦＥＴ ２２ ｎチャネルＭＯＳＦＥＴ ２３ フィールド酸化膜 ２４ 層間絶縁膜 Reference Signs List 1 silicon substrate 2, 7 insulating layer 3, 3a silicon layer 4 defect layer 5, 6 defect-free layer 8 second silicon substrate 11 precipitation nucleus 12 crystal defect 13 polishing part 21 p-channel MOSFET 22 n-channel MOSFET 23 field oxide film 24 Interlayer insulating film
Claims (3)
層を形成したＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕ
ｌａｔｏｒ）基板において、シリコン基板の酸素濃度が
１．５×１０18ｃｍ-3以上であることを特徴とするＳＯ
Ｉ基板。An SOI (Silicon On Insu) in which a silicon layer is formed on a silicon substrate via an insulating layer.
a silicon substrate, wherein the silicon substrate has an oxygen concentration of 1.5 × 10 18 cm −3 or more.
I substrate.
℃の範囲で、所定の時間熱処理する工程と、前記工程の
後で、前記シリコン基板上に前記絶縁層を形成する工程
と、前記絶縁層上に前記シリコン層を形成する工程を含
むことを特徴とするＳＯＩ基板の製造方法。2. The method according to claim 1, wherein said silicon substrate is heated to a temperature of 600.degree.
A step of performing a heat treatment within a range of ° C. for a predetermined time, a step of forming the insulating layer on the silicon substrate after the step, and a step of forming the silicon layer on the insulating layer. SOI substrate manufacturing method.
特徴とする請求項２に記載のＳＯＩ基板の製造方法。3. The method according to claim 2, wherein the predetermined time is 10 minutes or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19687598A JP2000031439A (en) | 1998-07-13 | 1998-07-13 | Soi substrate and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19687598A JP2000031439A (en) | 1998-07-13 | 1998-07-13 | Soi substrate and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000031439A true JP2000031439A (en) | 2000-01-28 |
Family
ID=16365114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19687598A Withdrawn JP2000031439A (en) | 1998-07-13 | 1998-07-13 | Soi substrate and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000031439A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2838865A1 (en) * | 2002-04-23 | 2003-10-24 | Soitec Silicon On Insulator | Fabrication of a substrate comprising a useful layer on a support having high resistivity includes thermal treatment to precipitate interstitial oxygen in the substrate base |
| JP2004363495A (en) * | 2003-06-06 | 2004-12-24 | Toshiba Corp | Semiconductor substrate |
| WO2005024918A1 (en) * | 2003-09-08 | 2005-03-17 | Sumco Corporation | Soi wafer and its manufacturing method |
| US7615467B2 (en) * | 2004-12-02 | 2009-11-10 | Sumco Corporation | Method for manufacturing SOI wafer |
| CN111261576A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Method for forming silicon-on-insulator structure |
| US11393772B2 (en) * | 2018-09-26 | 2022-07-19 | Shanghai Simgui Technology Co., Ltd. | Bonding method for semiconductor substrate, and bonded semiconductor substrate |
| US12040221B2 (en) | 2022-01-19 | 2024-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication method of metal-free SOI wafer |
-
1998
- 1998-07-13 JP JP19687598A patent/JP2000031439A/en not_active Withdrawn
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7586154B2 (en) | 2002-04-23 | 2009-09-08 | S.O.I.Tec Silicon On Insulator Technologies | Method for fabricating a substrate with useful layer on high resistivity support |
| WO2003092041A2 (en) * | 2002-04-23 | 2003-11-06 | S.O.I.Tec Silicon On Insulator Technologies | Method for fabricating a soi substrate a high resistivity support substrate |
| WO2003092041A3 (en) * | 2002-04-23 | 2003-12-24 | Soitec Silicon On Insulator | Method for fabricating a soi substrate a high resistivity support substrate |
| FR2838865A1 (en) * | 2002-04-23 | 2003-10-24 | Soitec Silicon On Insulator | Fabrication of a substrate comprising a useful layer on a support having high resistivity includes thermal treatment to precipitate interstitial oxygen in the substrate base |
| US7268060B2 (en) | 2002-04-23 | 2007-09-11 | S.O.I.Tec Silicon On Insulator Technologies | Method for fabricating a substrate with useful layer on high resistivity support |
| JP2004363495A (en) * | 2003-06-06 | 2004-12-24 | Toshiba Corp | Semiconductor substrate |
| JP4515719B2 (en) * | 2003-06-06 | 2010-08-04 | 株式会社東芝 | Semiconductor substrate |
| WO2005024918A1 (en) * | 2003-09-08 | 2005-03-17 | Sumco Corporation | Soi wafer and its manufacturing method |
| US7544583B2 (en) | 2003-09-08 | 2009-06-09 | Sumco Corporation | SOI wafer and its manufacturing method |
| JPWO2005024918A1 (en) * | 2003-09-08 | 2007-11-08 | 株式会社Sumco | SOI wafer and manufacturing method thereof |
| EP1667209A4 (en) * | 2003-09-08 | 2009-12-30 | Sumco Corp | Soi wafer and its manufacturing method |
| EP1667209A1 (en) * | 2003-09-08 | 2006-06-07 | SUMCO Corporation | Soi wafer and its manufacturing method |
| JP4552857B2 (en) * | 2003-09-08 | 2010-09-29 | 株式会社Ｓｕｍｃｏ | SOI wafer and manufacturing method thereof |
| US7615467B2 (en) * | 2004-12-02 | 2009-11-10 | Sumco Corporation | Method for manufacturing SOI wafer |
| US11393772B2 (en) * | 2018-09-26 | 2022-07-19 | Shanghai Simgui Technology Co., Ltd. | Bonding method for semiconductor substrate, and bonded semiconductor substrate |
| CN111261576A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Method for forming silicon-on-insulator structure |
| US12040221B2 (en) | 2022-01-19 | 2024-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication method of metal-free SOI wafer |
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