JP3274638B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon On Insulator) comprising a single crystal semiconductor layer formed on an insulating substrate or a semiconductor substrate via an insulating layer.
The present invention relates to a method for manufacturing a semiconductor device using a substrate.

[0002]

2. Description of the Related Art In semiconductor integrated circuits, demands for miniaturization and higher densification are increasing, such as the continuous increase in capacity of DRAMs and the promotion of system-on-silicon for realization of multifunctional integration. In accordance with the demands of such an era, design rules have been steadily miniaturized, and the era of quarter micron (the minimum mask exposure width is 0.25 μm or less) is approaching. However, in the quarter micron era, the required power supply voltage of electronic devices was 2.5.
Since the voltage becomes V or less, it is necessary to lower the threshold voltage of the transistor than before. For this reason, SOI, SOS
MOS device having a (silicon on saphire) structure, and an integrated LSI
Is the next generation VL with its excellent sub-threshold characteristics, low parasitic capacitance, complete isolation between devices, and alpha ray resistance.
It is drawing attention as a candidate for SI.

[0005] Here, a conventional SOI structure N-channel MOSFET will be described with reference to FIGS. First, a buried oxide film 2 and a single crystal semiconductor layer 3 are formed on a semiconductor substrate 1, and the average thickness of the single crystal semiconductor layer 3 is 10
A 0 nm SOI structure wafer is formed. An oxide film 4 is formed on the single crystal semiconductor layer 3 by CVD (Ch) by chemical vapor deposition.
A nitride film 5 is formed on the entire surface (FIG. 5A). Subsequently, the oxide film 4 and the CVD nitride film 5 in a region to be an element isolation region are removed by using a lithography technique and an etching technique (FIG. 5B). Further, a field oxide film 6 for element isolation is formed by steam oxidation at a temperature of 1000 ° C. (FIG. 5C). Next, normal MO
Similarly to the SFET process, after removing the oxide film 4 and the CVD nitride film 5, an oxide film 7 is grown on the single crystal semiconductor layer 3, and first, boron difluoride (I) is used as an ion implantation 20 for adjusting a threshold voltage. BF ₂ ⁺ ) is ion-implanted into the single crystal semiconductor layer 3. Subsequently, phosphorus (P ⁺ ) is implanted into the single crystal semiconductor layer 3 as an ion implantation 20 for adjusting the threshold voltage for suppressing the variation of the threshold voltage due to the variation in the thickness of the single crystal semiconductor layer 3 (FIG. d)). Thereafter, the oxide film 7 is removed, and a new gate oxide film 8 is grown on the single crystal semiconductor layer 3.
An N-type polysilicon gate electrode 9 is formed on the gate oxide film 8, and a sidewall oxide film 10 is formed on the side wall of the gate electrode 9 (FIG. 6A). After this,
A protective oxide film 11 is grown by oxidizing the entire surface of the semiconductor substrate 1, and an N ⁺ diffusion layer 12 serving as a source and a drain of an N-channel MOSFET is formed by ion implantation through this oxide film.
T is completed (FIG. 6B).

[0004]

However, the above-described conventional device isolation method has a problem inherent to SOI. That is, in the step of forming the field oxide film 6 for element isolation, there is a problem that uniform oxidation is hindered by the presence of the buried oxide layer 2. Although the volume of silicon is approximately doubled by the formation of the silicon oxide film, a stress is generated around the field oxide film 6 in the step of forming the field oxide film 6 for element isolation due to the volume expansion. In particular, in a normal silicon wafer, the single crystal semiconductor layer exists below the element isolation oxide film, but in the SOI structure, the single crystal semiconductor layer does not exist below the element isolation oxide film. Due to the presence, a large stress is applied to the single crystal semiconductor layer in a region sandwiched between the field oxide film 6 and the buried oxide layer 2. In a region where a large stress is applied, the growth of the silicon oxide film is suppressed, and the single crystal semiconductor layer 13 that is not oxidized remains below the side wall of the field oxide film 6. In the not oxidized single-crystal semiconductor layer 13, the source, N ⁺ impurity of the N ⁺ diffusion layer 12 of the drain is not sufficiently diffused,
A low concentration diffusion layer 14 having a low impurity concentration is formed (FIG. 6).
(B)).

As a result, the low concentration diffusion layer 14
The interposition between the source and the drain of the OSFET causes a punch-through between the source and the drain of the adjacent MOSFET when a power supply voltage is applied, which causes a breakdown voltage failure.

If a thick oxide film is formed in the step of forming field oxide film 6, oxidation does not progress in the depth direction, but the surface of single crystal semiconductor layer 3 near field oxide film 6 where relatively no stress is applied is formed. In the region, the oxidation easily proceeded, and the single crystal semiconductor layer 3 became thin (FIG. 5C). When the N ⁺ diffusion layer 12 serving as the source and the drain of the MOSFET is formed thereon as shown in FIG. 6B, the thin single crystal semiconductor layer 15 has a current extraction resistance during transistor operation because the diffusion layer is thin. Increase
This causes the transistor characteristics to deteriorate.

An object of the present invention is to prevent the low-concentration diffusion layer 14 below the side wall of the field oxide film 6 and the thin single crystal semiconductor layer 15 near the field oxide film 6 from being buried. The purpose is to reduce the stress existing in the single crystal semiconductor layer 13 near the layer 2.

[0008]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film on an insulating substrate or a semiconductor substrate, and a step of forming a single-crystal semiconductor on the first insulating film. Forming a layer, forming a second insulating film on the semiconductor layer, removing a predetermined region of the second insulating film and forming the first insulating film on the semiconductor layer below the predetermined region. Forming a device isolation region that insulates and separates the semiconductor layer in a shape connected to a film, wherein the single-crystal semiconductor layer has a thickness of 50 to 60 nm; Using the opened second insulating film as a mask, silicon ions are implanted into a part of the semiconductor layer at an implantation energy of 20 to 30 KeV and a dose of 1 × 10 ^{16 to} 1 × 10 ¹⁷ / cm ² buried oxide film of the semiconductor layer. Reach Implanting a so that, characterized by comprising a step of oxidizing the ion implanted regions.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a first embodiment of the present invention,
This will be described with reference to FIGS. 1A to 1D and FIGS. 2A and 2B. First, a buried oxide film 2 and a single crystal semiconductor layer 3 are formed on a semiconductor substrate 1, and an SOI structure wafer having an average thickness of the single crystal semiconductor layer 3 of 50 nm is formed. On this single crystal semiconductor layer 3, an oxide film 4 and a CVD (C
Chemical Vapor Deposition (referred to below) is formed on the entire surface of the nitride film 5 (FIG. 1A).
Subsequently, the oxide film 4 and the CVD nitride film 5 in a region to be an element isolation region are removed by using a lithography technique and an etching technique (FIG. 1B). Further, silicon ions 18 are implanted into the entire surface of the semiconductor substrate 1 to amorphize the silicon layer to form an amorphous semiconductor layer 16 (FIG. 1C).

FIG. 4 shows the dependency of the oxidation rate on the amount of silicon ions implanted in the amorphous semiconductor layer into which silicon ions have been implanted. Silicon ion dose of 1 × 1
It can be seen that the oxide film growth rate increases when the value exceeds 0 ¹⁶ / cm ² . The implantation energy of the silicon ions 18 is set at 20 considering the thickness of the single crystal semiconductor layer 3 of 50 nm.
KeV is preferred.

In this embodiment, the implantation amount of the silicon ions 18 at which this effect is obtained coincides with the implantation amount at which the single crystal semiconductor layer 3 can be made amorphous. Here, silicon ion 1
In the implantation of 8, the implantation angle is smaller than the angle perpendicular to the main surface of the semiconductor substrate 1 and by rotating ion implantation, so that the stress around the amorphous semiconductor layer 16 can be further reduced.

Further, a field oxide film 6 for element isolation is formed by oxidation at 1000 ° C. in a steam atmosphere (FIG. 1D). Thereafter, the oxide film 4 and the CVD nitride film 5 are removed in the same manner as in the prior art, an oxide film is grown on the entire surface of the semiconductor substrate 1, and boron difluoride (BF ₂ ⁺ ) for adjusting the threshold voltage is set. Phosphorus (P ⁺ ) for suppressing voltage variation is ion-implanted into the single-crystal semiconductor layer 3 to form the gate oxide film 8, the gate electrode 9, and the sidewall oxide film 10 (FIG. 2A), and the protective oxide is formed. Film 11, N-channel type MO
When the N ⁺ diffusion layer 12 serving as the source and drain of the SFET is formed, an N-channel MOSFET having an SOI structure is completed (FIG. 2B).

Next, in a second embodiment of the present invention, in order to make the single crystal semiconductor layer 3 amorphous in the first embodiment,
Arsenic ion implantation is adopted instead of silicon ion implantation. Except for this step, the second embodiment is the same as the first embodiment and will not be described.

As shown in FIG. 1B, after removing the oxide film 4 and the CVD nitride film 5 in a region to be an element isolation region, arsenic ions 19 are implanted as shown in FIG. An arsenic-added semiconductor layer 17 is formed on the semiconductor layer 3. Here, the dependence of the oxidation rate on the arsenic ion implantation amount in the step of forming the field oxide film 6 after the arsenic ion implantation is shown in FIG. It can be seen that when the dose exceeds 5 × 10 ¹⁴ / cm ² , the oxide film growth rate increases. In this embodiment, the first
The effect of increasing the growth rate of the oxide film at a lower dose than that of the embodiment is obtained. This is because arsenic has a higher atomic mass than silicon, so that arsenic is more likely to make the single crystal semiconductor layer more amorphous when ion-implanted into the single crystal semiconductor layer. It has the property of promoting oxidation in the layer. As in the first embodiment, the arsenic ions 19 are implanted at a shallower angle than perpendicular to the main surface of the semiconductor substrate 1 and by rotating ion implantation to reduce the stress around the arsenic-added semiconductor layer 17. Can be more relaxed. Subsequently, a field oxide film 6 for element isolation is formed by steam oxidation at a temperature of 1000 ° C. (FIG. 3B). After this, Figure 2
2 (a) and FIG. 2 (b), the SOI structure N-channel type M
The OSFET is completed.

In the embodiment of the present invention, silicon ions and arsenic ions are used to make the single crystal semiconductor layer amorphous, but ions such as germanium may be used, and the present invention is not limited to these. Needless to say, there is no.

[0016]

As described above, silicon or arsenic is ion-implanted in advance into the single crystal semiconductor layer 3 on which the field oxide film 6 for element isolation is formed, and the single crystal semiconductor layer 3 is made amorphous. Amorphous semiconductor layer 1 before field oxidation
The stress of the single crystal semiconductor layer 3 near 6 can be optimized, and the field oxide film 6 following this process can be formed stably and with good reproducibility. That is, the oxidation of the field oxide film 6 progresses in a state where the stress in the single crystal semiconductor layer 3 in the vicinity of the buried oxide film 2 is relaxed, and the field oxide film 6 is connected to the buried oxide film 2.
Further, with the progress of oxidation in the vertical direction, the field oxide film 6
Since the lateral oxidation to the surface of the single crystal semiconductor layer 3 in the vicinity is suppressed, the low concentration diffusion layer 12 is generated due to the separation between the field oxide film 6 and the buried oxide film 2 and the field oxide film 6 is formed. The generation of the thin single-crystal semiconductor layer 15 due to the rate-growth in the surface region of the single-crystal semiconductor layer 3 is not observed.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, the contact resistance and the breakdown voltage between elements are set to optimized values, and a stable MOSFET with good reproducibility can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device illustrating a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a step subsequent to FIG.

FIG. 3 is a cross-sectional view of a semiconductor device illustrating main steps of a second embodiment of the present invention.

FIG. 4 is a graph showing dose dependence of an oxide film growth rate in an amorphous semiconductor layer in the first and second embodiments of the present invention.

FIG. 5 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 6 is a sectional view showing a step after FIG. 5;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 buried oxide film 3 single-crystal semiconductor layer 4 oxide film 5 CVD nitride film 6 field oxide film 7 oxide film 8 gate oxide film 9 gate electrode 10 sidewall oxide film 11 protective oxide film 12 N ⁺ diffusion layer 13 not oxidized Single-crystal semiconductor layer 14 Low-concentration diffusion layer 15 Thin single-crystal semiconductor layer 16 Amorphous semiconductor layer 17 Arsenic-doped semiconductor layer 18 Silicon ion 19 Arsenic ion 20 Ion for adjusting threshold voltage

Claims (1)

(57) [Claims] A step of forming a first insulating film on an insulating substrate or a semiconductor substrate; a step of forming a single crystal semiconductor layer on the first insulating film; Forming an insulating film, and removing a predetermined region of the second insulating film to insulate and separate the semiconductor layer from the semiconductor layer below the predetermined region so as to be connected to the first insulating film. the method of manufacturing a semiconductor device comprising the steps of forming an element isolation region, wherein a is 50 to 60nm thickness of the single crystal semiconductor layer, and, the semiconductor layer a second insulating film which is the opening as a mask Partially implanted silicon ions with an energy of 20
To 30 KeV, dose amount 1 × 10 ^{16 to} 1 × 10
^A method for manufacturing a semiconductor device, comprising: a step of implanting a concentration of ¹⁷ / cm ² to reach a buried oxide film of the semiconductor layer; and a step of oxidizing the ion-implanted region.