JP2005286141A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device where elements different in characteristics are loaded together on the same substrate. <P>SOLUTION: Protection layers 30 and 32 covering the first region of a semiconductor layer 10 are formed on the semiconductor layer 10 arranged on an insulating layer 8. Film thickness of the semiconductor layer 10 in a region which is not covered with the protection layer 32 is thinned, the protection layer 32 is removed and an element separating region is formed in the semiconductor layer 10. Thus, a first semiconductor layer 10A is formed in the first region R1, and a second semiconductor layer 10B whose film thickness is smaller than the first semiconductor layer 10A is formed in a second region R2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device having a MIS (Metal Insulator Silicon) transistor provided in a semiconductor layer on an insulating layer.

  With the recent high integration of semiconductor devices, SOC (System On Chip) is attracting attention. For this reason, development of technology for mounting various devices having different breakdown voltages on the same substrate has been performed. In recent years, a semiconductor device using a semiconductor layer (hereinafter also referred to as an “SOI (Silicon on Insulator) layer”) provided over an insulating layer has attracted attention in order to realize low power consumption and high-speed operability. ing. Such a MOS transistor provided in an SOI layer may be provided in a thinned SOI layer in order to realize operability with low power consumption. Therefore, in a place where a certain level of breakdown voltage is required, a sufficient breakdown voltage may not be ensured depending on the film thickness of the SOI layer. Therefore, in the case of forming a circuit that requires a certain withstand voltage such as a power supply portion or an I / O portion, it may be formed in combination with a MOS transistor or the like provided in a bulk semiconductor layer.

Further, even in a circuit in which a digital circuit and an analog circuit are mixedly mounted, the digital circuit is configured with a MOS transistor capable of realizing an operation with low power consumption, and the analog circuit is configured with a MOS transistor capable of sufficiently securing a withstand voltage. It is desirable.
JP-A-10-335589

  As described above, the semiconductor device disclosed in Patent Document 1 can be exemplified as a method of mounting a plurality of MOS transistors having different capabilities on the same substrate. In the semiconductor device described in Patent Document 1, a digital circuit block portion and an analog circuit block portion on the same SOI substrate are mounted together. That is, a plurality of MOS transistors having different capabilities are formed. However, in this semiconductor device, the element isolation region that isolates the MOS transistors provided in the SOI layer does not reach the insulating layer. For this reason, the structure is the same as that of the MOS transistor provided in the bulk semiconductor layer, and the effect of using the SOI layer may not be sufficiently exhibited.

  The present invention provides a method for manufacturing a semiconductor device in which elements having different characteristics are mixedly mounted on the same substrate.

In the method for manufacturing a semiconductor device of the present invention, a protective layer covering the first region of the semiconductor layer is formed above the semiconductor layer provided on the insulating layer,
Reduce the thickness of the semiconductor layer in the second region not covered by the protective layer,
Removing the protective layer;
By forming an element isolation region in the semiconductor layer, a first semiconductor layer portion is formed in the first region, and a thickness of the semiconductor layer in the second region is larger than that of the first semiconductor layer portion. Forming a small second semiconductor layer portion.

  According to the method for manufacturing a semiconductor device of the present invention, a semiconductor layer having a plurality of regions having different thicknesses can be formed on the same insulating layer. Thereafter, an element isolation region is formed so that the semiconductor layer is separated into regions having different film thicknesses, whereby a plurality of MIS transistors are formed, and the semiconductor layers have different film thicknesses. And a 2nd semiconductor layer part can be formed. As a result, MIS transistors can be separately formed in a semiconductor layer having an appropriate film thickness according to the characteristics of MIS transistors provided on the same substrate. For example, the digital circuit and the analog circuit are formed by forming the MIS transistor constituting the digital circuit in the second semiconductor layer portion where the film thickness of the semiconductor layer is small and forming the MIS transistor constituting the analog circuit in the first semiconductor layer portion. Even if the semiconductor device is embedded, a semiconductor device having the advantage of the SOI layer can be manufactured.

  In the present invention, forming the B layer above the specific A layer means that the B layer is formed on the A layer via another layer, in addition to the case where the B layer is formed directly on the A layer. It means to include the case of forming.

  The method for manufacturing a semiconductor device of the present invention can further take the following aspects.

  In the method of manufacturing a semiconductor device of the present invention, the thinning can be performed by forming an insulating layer by a selective thermal oxidation method above the semiconductor layer in the second region. According to this aspect, the protective layer can be formed by a so-called selective thermal oxidation method in which only the semiconductor layer in the second region is oxidized using a nitride film or the like. Therefore, semiconductor layers having different thicknesses can be formed in the first region and the second region by a simple process.

  In the method for manufacturing a semiconductor device according to the present invention, the thinning can be performed by etching the semiconductor layer in the second region. According to this aspect, by etching the semiconductor layer in the second region using the protective layer as a mask, semiconductor layers having different film thicknesses in the first region and the second region can be formed separately by a simple process.

  In the semiconductor device manufacturing method of the present invention, the first semiconductor layer portion and the second semiconductor layer portion may be formed in an island shape above the insulating layer. According to this aspect, the island-shaped first semiconductor layer portion and the second semiconductor layer portion can be formed on the insulating layer by the mesa type element isolation method.

  In the method for manufacturing a semiconductor device according to the present invention, the element isolation region may be formed by removing a semiconductor layer including a boundary portion between the first region and the second region. According to this aspect, each of the first semiconductor layer portion and the second semiconductor layer portion can be formed to have a semiconductor layer having a uniform thickness. For example, when the semiconductor layer in the second region is thinned by the selective thermal oxidation method, a bird's beak portion is generated at the boundary between the first region and the second region. However, according to this aspect, since such a bird's beak part is removed and element isolation is performed, a semiconductor layer part having a uniform film thickness can be formed in each semiconductor layer part.

In the method for manufacturing a semiconductor device of the present invention,
Forming a first MIS transistor in the first semiconductor layer portion;
Forming a second MIS transistor in the second semiconductor layer portion. According to this aspect, it is possible to manufacture a semiconductor device in which MIS transistors are formed in a plurality of semiconductor layer portions provided on the same insulating layer and having different semiconductor layer thicknesses. As a result, a plurality of MIS transistors having different withstand voltages can be formed in a semiconductor layer having a thickness suitable for each application.

  Embodiments of the present invention will be described below. First, the structure of a semiconductor device obtained by the manufacturing method of the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a semiconductor device obtained by the manufacturing method of the present embodiment.

  As shown in FIG. 1, the semiconductor device obtained by the manufacturing method of the present embodiment has a first semiconductor layer portion 10 </ b> A in the first region R <b> 1 on the insulating layer 8 provided on the support substrate 6. In the second region R2, the second semiconductor layer portion 10B is provided. The first semiconductor layer portion 10A and the second semiconductor layer portion 10B are island-shaped semiconductor layers, and the thicknesses of the semiconductor layers are different. In the present embodiment, the case where the thickness of the first semiconductor layer portion 10A is larger than that of the second semiconductor layer portion 10B is taken as an example. The film thickness of the semiconductor layer of the first semiconductor layer portion 10A can be, for example, 80 to 200 nm, and the film thickness of the semiconductor layer of the second semiconductor layer portion 10B can be, for example, 10 to 80 nm. MIS transistors 100A and 100B are provided in the first semiconductor layer portion 10A and the second semiconductor layer portion 10B, respectively.

  The MIS transistor 100A includes a gate insulating layer 20a provided on the first semiconductor layer portion 10A, a gate electrode 22a provided on the gate insulating layer 20a, and a sidewall insulation provided on a side surface of the gate electrode 22a. Layer 24a. In the first semiconductor layer portion 10A, a source region and a drain region (hereinafter referred to as “source / drain region”) 26a are provided on the side of the sidewall insulating layer 24a. An LDD region 28a is provided between the source / drain region 26a and the channel region (semiconductor layer region under the gate insulating layer 20a).

  Similar to the MIS transistor 100A, the MIS transistor 100B includes a gate insulating layer 20b provided on the second semiconductor layer portion 10B, a gate electrode 22b provided on the gate insulating layer 20b, and a side surface of the gate electrode 22b. And a sidewall insulating layer 24b provided. In the second semiconductor layer portion 10B, source / drain regions 26b are provided on the side of the sidewall insulating layer 24b. An LDD region 28b is provided between the source / drain region 26b and the channel region (semiconductor layer region below the gate insulating layer 20b).

  The MIS transistor 100B is a fully depleted device in which a neutral region does not exist in the body region 12 which is a region other than the source / drain region 26a in the second semiconductor layer portion 10B. On the other hand, the MIS transistor 100A can be a partially depleted device in which a neutral region exists in the body region 12. The MIS transistor 100A can realize high-speed operability with low power consumption, and the MIS transistor 100B has a first semiconductor layer portion in which the thickness of the semiconductor layer is larger than that of the second semiconductor layer portion 10B. Since it is formed in 10A, a breakdown voltage can be secured.

  The semiconductor device formed by the manufacturing method of the semiconductor device of the present embodiment has the first semiconductor layer portion 10A and the second semiconductor layer portion 10B having different semiconductor layer thicknesses on the same insulating layer 8. become. For this reason, when elements having different capabilities and characteristics are provided on the same substrate, they can be separately formed into semiconductor layer portions having film thicknesses suitable for the respective elements. For example, a partially depleted MIS transistor 100A in which a desired breakdown voltage is secured is formed in the first semiconductor layer portion 10A, and the second semiconductor layer portion 10B is completely required to have low power consumption and high-speed operability. A depletion type MIS transistor 100B is formed. As described above, a semiconductor device having MIS transistors with different characteristics on the same substrate while having the advantage of using the SOI layer can be provided.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 2 to 6 are cross-sectional views schematically showing manufacturing steps according to the method for manufacturing the semiconductor device of the present embodiment.

  (1) First, as shown in FIG. 2, an SOI substrate in which an insulating layer 8 and a semiconductor layer 10 are provided on a support substrate 6 is prepared. As an example of the SOI substrate, a substrate in which an insulating layer 8 and a semiconductor layer 10 are stacked on a support substrate 6 is used. A substrate, a laser annealing substrate, or the like can be used. As the semiconductor layer 10, for example, Si, Si—Ge, GaAs, InP, GaP, GaN, or the like can be used. The film thickness of the semiconductor layer 10 is preferably the film thickness of the largest semiconductor layer part among the island-shaped semiconductor layer parts formed on the same insulating layer 8 in a later step. It can be 80-200 nm.

  Next, as shown in FIG. 2, a thermal oxide film 30a is formed on the semiconductor layer 10, and a nitride film 32a is formed on the thermal oxide film 30a. The nitride film 32a serves as a mask when performing selective thermal oxidation. A mask layer M1 having an opening in the second region R2 is formed on the nitride film 32a. As mask layer M1, for example, a resist layer can be used.

  (2) Next, as shown in FIG. 3, using the mask layer M1 as a mask, the thermal oxide film 30a and the nitride film 32a are removed, and the thermal oxide film 30 and the nitride film 32 covering the first region R1 are formed. As a method for removing the thermal oxide film 30 and the nitride film 32, a known etching technique can be used. Thereby, in the second region R2, the semiconductor layer 10 is exposed. The nitride film 32 becomes an oxidation resistant mask (protective layer) in the subsequent oxidation process.

  (3) Next, as shown in FIG. 4, the semiconductor layer 10 is oxidized. As a result, the semiconductor layer 10 in the second region R2 is oxidized to form the thermal oxide film 30b. By this step, semiconductor layers having different thicknesses of the semiconductor layer 10 can be formed in the second region R2 and the first region R1.

  (4) Next, as shown in FIG. 5, the thermal oxide film 30b and the nitride film 32 are removed. The removal of the thermal oxide film 30b and the nitride film 32 can be performed by a known etching technique.

  (5) Next, as shown in FIG. 6, an element isolation region 14 is formed in the semiconductor layer 10. The element isolation region 14 is formed by forming a mask layer (not shown) in a predetermined region of the semiconductor layer 10 and etching the semiconductor layer 10 until the insulating layer 8 is exposed using the mask layer as a mask. The removal of the semiconductor layer 10 can be performed by a known etching technique. The mask layer is formed so as to have an opening above the region including the boundary between the second region R2 and the first region R1. That is, the element isolation region 14 is formed by removing the semiconductor layer 10 including the boundary between the second region R2 and the first region R1. As described above, when the semiconductor layer 10 having a different film thickness is formed in the second region R2 and the first region R1 using the selective thermal oxidation method, a bird's beak is formed at the boundary between the second region R2 and the first region R1. Parts are generated. In the bird's beak portion, the semiconductor layer 10 has a gentle inclination and does not have a uniform film thickness and cannot have a flat surface. Due to the non-uniform thickness of the semiconductor layer 10, the source region and the drain region may be formed with different depths, resulting in variations in characteristics. In addition, when various elements are formed on a surface where flatness is impaired, there is a problem that a mask shift occurs in various patterning processes such as formation of the gate electrode 22 and wiring. However, according to the manufacturing method of the present embodiment, such a problem can be avoided because the non-uniform thickness portion is removed. Further, by performing mesa-type element isolation, it is not necessary to perform a step of embedding an insulating layer after forming a trench as in the STI method, and the element isolation region 14 can be formed in a simple and satisfactory process. .

  (6) Next, as shown in FIG. 1, MIS transistors 100A and 100B are formed in the first semiconductor layer portion 10A and the second semiconductor layer portion 10B. An example of a method for forming the MIS transistor 100A and the MIS transistor 100B will be described.

  First, gate insulating layers 20a and 20b are formed in the first semiconductor layer portion 10A and the second semiconductor layer portion 10B. The gate insulating layers 20a and 20b can be formed in separate steps so as to have an appropriate film thickness according to the driving voltages of the MIS transistors 100A and 100B. In the manufacturing method of the present embodiment, the thickness of the gate insulating layer 20a is determined by the withstand voltage of the MIS transistors 100A and 100B, but is 1 to 10 nm, for example, and the thickness of the gate insulating layer 20b is 10 It can be formed to be ˜100 nm. Examples of a method for forming the gate insulating layers 20a and 20b having different thicknesses include the following methods. A thermal oxide film (not shown) that becomes a part of the gate insulating layer 20b is formed on the first semiconductor layer portion 10A and the second semiconductor layer portion 10B, and this thermal oxide film is formed on the second semiconductor layer portion 10B. The gate insulating layer 20b in the other region is removed so as to remain only on the top. Thereafter, a thermal oxide film (not shown) is again formed on the first semiconductor layer portion 10A and the second semiconductor layer portion 10B. As a result, a gate insulating layer 20b is formed on the second semiconductor layer portion 10B by laminating a thermal oxide film formed in a plurality of steps. On the first semiconductor layer portion 10A, one gate insulating layer 20b is formed. A gate insulating layer 20a made of a thermal oxide film formed in the process is formed.

  Next, gate electrodes 22a and 22b are formed on the gate insulating layer 20a and the gate insulating layer 20b. The gate electrodes 22a and 22b can be formed in the same process. The gate electrodes 22a and 22b are formed by forming a conductive layer (not shown) and patterning the conductive layer. As the conductive layer, for example, a polycrystalline silicon layer can be used.

  Next, using the gate electrodes 22a and 22b as masks, impurities of a predetermined conductivity type are introduced into the first semiconductor layer portion 10A and the second semiconductor layer portion 10B to form LDD regions 28a and 28b. The impurity concentration of the LDD regions 28a and 28b is formed so as to be smaller than that of the source / drain regions 26a and 26b formed in a later step.

  Next, sidewall insulating layers 24a and 24b are formed on the side surfaces of the gate electrodes 22a and 22b. The sidewall insulating layers 24a and 24b are formed by forming an insulating layer (not shown) so as to cover the first semiconductor layer portion 10A and the second semiconductor layer portion 10B, and performing anisotropic etching on the insulating layer. It is done by applying. As the insulating layer, for example, an oxide film, a nitride layer, or a laminated film thereof can be used.

  Next, an impurity of a predetermined conductivity type is introduced into the semiconductor layer on the side of the sidewall insulating layers 24a and 24b to form the source / drain regions 26a and 26b. In the formation of the source / drain regions 26a and 26b, if necessary, diffusion treatment such as heat treatment may be performed after introducing impurities of a predetermined conductivity type. The source / drain regions 26a and 26b may be formed in separate steps. In that case, it can be formed as follows. First, the first semiconductor layer portion 10A (or the second semiconductor layer portion 10B) is covered with a mask layer such as a resist layer, and impurities are introduced into a predetermined region of the second semiconductor layer portion 10B (or the first semiconductor layer portion 10A). Then, the mask layer is removed. Thereafter, the second semiconductor layer portion 10B is covered with a mask layer, impurities are introduced into a predetermined region of the first semiconductor layer portion 10A, and then the mask layer is removed. Thereafter, when the diffusion treatment of the introduced impurity is performed, it can be performed in the same process.

  Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

(Modification)
Next, a modification of the semiconductor device manufacturing method of the present embodiment will be described with reference to FIGS. This modification is an example in which the method of thinning the semiconductor layer 10 in the second region R2 is different from the above-described embodiment. In the following description, detailed description of steps common to the above-described embodiment is omitted. 7 and 8 are cross-sectional views schematically showing one process of a method for manufacturing a semiconductor device according to a modification.

  (1) First, an SOI substrate (see FIG. 2) is prepared as in the above-described embodiment. Next, a thermal oxide film (not shown) is formed on the entire surface of the semiconductor layer 10, and a mask layer M2 having an opening in the second region R2 is formed on the thermal oxide film. For example, a resist layer is used as the mask layer M2. Thereafter, the thermal oxide film 30 is formed by patterning the thermal oxide film using the mask layer M2 as a mask, as shown in FIG. As a result, the semiconductor layer 10 in the second region R2 is exposed. Note that the thermal oxide film formed on the semiconductor layer 10 is provided in order to prevent damage to the semiconductor layer 10 due to direct contact between the mask layer such as a resist layer and the semiconductor layer 10.

  Next, the semiconductor layer 10 is etched using the mask layer M2 as a mask. By this etching, in the semiconductor layer 10, the film thickness can be made different between the second region R2 and the first region R1. Thereafter, the mask layer M2 is removed by a known method.

  By this etching, an etching damage layer 34 may be formed on the surface of the semiconductor layer 10 exposed to the etching process as shown in FIG.

  (2) Next, as shown in FIG. 8, the semiconductor layer 10 is subjected to thermal oxidation treatment. This thermal oxidation treatment is performed until a thermal oxide film 36 having a thickness sufficient to capture the etching damage layer 34 is formed. Thereafter, by removing the thermal oxide film 36, as shown in FIG. 5, the semiconductor layers 10 having different film thicknesses can be formed in the second region R2 and the first region R1.

  (3) Next, the first semiconductor layer portion 10A and the second semiconductor layer portion 10B are formed in the same manner as in step (5) of the above-described embodiment. Next, in the same manner as in the step (6), the MIS transistor 100A is formed in the first semiconductor layer portion 10A, and the MIS transistor 100B is formed in the second semiconductor layer portion 10B. Through the above steps, the semiconductor device shown in FIG. 1 can be manufactured by the semiconductor device manufacturing method according to the modification.

  According to the manufacturing method of the semiconductor device of the present embodiment and the modification, the first region R1 and the second region R2 having different thicknesses of the semiconductor layer 10 can be formed on the same insulating layer 8. After that, by forming the element isolation region 14 so that the semiconductor layer 10 is separated for each of the first region R1 and the second region R2, a region where a plurality of MIS transistors are formed, The first semiconductor layer portion 10A and the second semiconductor layer portion 10B having different film thicknesses can be formed. As a result, MIS transistors can be separately formed in a semiconductor layer having an appropriate film thickness according to the characteristics of MIS transistors provided on the same substrate. For example, the MIS transistor constituting the digital circuit is formed in the second semiconductor layer portion 10B having a small semiconductor layer thickness, and the MIS transistor constituting the analog circuit is formed in the first semiconductor layer portion 10A. Even a semiconductor device in which an analog circuit is mixed can be manufactured with the advantage of an SOI layer.

  Note that the method for manufacturing a semiconductor device of the present invention is not limited to the above-described embodiment, and can be modified within the scope of the gist of the present invention. For example, although the case where the LDD region 28 is provided has been described in the present embodiment, the present invention is not limited to this and may not be provided. Further, a silicide layer may be provided on the gate electrodes 22a and 22b and the source / drain regions 26a and 26b. In the present embodiment, the case where there are two types of regions (the first region R1 and the second region R2) with different thicknesses of the semiconductor layer is illustrated, but the present invention is not limited to this, and three or more types of regions are included. You may have.

Sectional drawing which shows typically the semiconductor device obtained by the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment. Sectional drawing which shows typically 1 process of the manufacturing method of this Embodiment.

Explanation of symbols

  6 support substrate, 8 insulating layer, 10 semiconductor layer, 10A first semiconductor layer portion, 10B second semiconductor layer portion, 12 body region, 14 element isolation region, 20a, b gate insulating layer, 22a, b gate electrode, 24a, b side wall insulating layer, 26a, b source / drain region, 28a, b LDD region, 100A, B MIS transistor

Claims (6)

Forming a protective layer covering the first region of the semiconductor layer above the semiconductor layer provided on the insulating layer;
Reduce the thickness of the semiconductor layer in the second region not covered by the protective layer,
Removing the protective layer;
By forming an element isolation region in the semiconductor layer, a first semiconductor layer portion is formed in the first region, and a thickness of the semiconductor layer in the second region is larger than that of the first semiconductor layer portion. Forming a small second semiconductor layer portion. In claim 1,
The thinning is performed by forming an insulating layer by a selective thermal oxidation method above the semiconductor layer in the second region. In claim 1,
The method of manufacturing a semiconductor device, wherein the thinning is performed by etching the semiconductor layer in the second region. In any one of Claims 1-3,
The method for manufacturing a semiconductor device, wherein the first semiconductor layer portion and the second semiconductor layer portion are formed in an island shape above the insulating layer. In any one of Claims 1-4,
The element isolation region is formed by removing a semiconductor layer including a boundary portion between the first region and the second region. In any one of Claims 1-5,
Forming a first MIS transistor in the first semiconductor layer portion;
Forming a second MIS transistor in the second semiconductor layer portion.

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