US7585736B2 - Method of manufacturing semiconductor device with regard to film thickness of gate oxide film - Google Patents
Method of manufacturing semiconductor device with regard to film thickness of gate oxide film Download PDFInfo
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- US7585736B2 US7585736B2 US11/723,092 US72309207A US7585736B2 US 7585736 B2 US7585736 B2 US 7585736B2 US 72309207 A US72309207 A US 72309207A US 7585736 B2 US7585736 B2 US 7585736B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 56
- 150000004767 nitrides Chemical class 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 42
- 238000001312 dry etching Methods 0.000 claims description 29
- 239000000126 substance Substances 0.000 claims description 28
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010408 film Substances 0.000 description 222
- 239000010409 thin film Substances 0.000 description 45
- 238000007796 conventional method Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000009545 invasion Effects 0.000 description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Definitions
- the present invention relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a semiconductor device with regard to a film thickness of a gate oxide film.
- JP-P2005-5668A discloses a method of manufacturing a dual gate oxide film. This conventional technique will be described below.
- FIGS. 1A to 1C and FIGS. 2A to 2C are sectional views showing the method of manufacturing the dual gate oxide film, in this conventional technique.
- the left side indicates the region where the transistor having the thick gate oxide film is formed (hereafter, referred to as the thick film Tr region), and the right side indicates the region where the transistor having the thin gate oxide film is formed (hereafter, referred to as the thin film Tr region).
- an isolation region (STI: Shallow Trench Isolation) 110 is firstly formed in a silicon substrate 101 .
- STI Shallow Trench Isolation
- the surface of the silicon substrate 101 is oxidized to form a first gate oxide film 102 such that the first gate oxide film 102 covers the surface of the silicon substrate 101 .
- a lithography operation is used to mask the thick film Tr region with a resist 103 , and the resist 103 is patterned so as to open only the thin film Tr region.
- the first gate oxide film 102 in the thin film Tr region is wet-etched by using an acidic chemical solution. Consequently, the first gate oxide film 102 in the thin film Tr region is removed.
- the chemical solution invades the interface between the resist 103 and the first gate oxide film 102 .
- an end 120 of the first gate oxide film 102 in the thick film Tr region is partially etched.
- the resist 103 is removed.
- the end 120 of the first gate oxide film 102 in the thick film Tr region becomes thinner towards the thin film Tr region, in the boundary between the thick film Tr region and the thin film Tr region.
- a second gate oxide film 104 is formed. Consequently, the gate oxide film having the thin film thickness, which is constituted by only the second gate oxide film 104 , can be formed in the thin film Tr region.
- the gate oxide film having the thick film thickness in which the first gate oxide film 102 and the second gate oxide film 104 are laminated, can be formed in the thick film Tr region.
- the film thickness becomes thin.
- this forbidden region since the transistor cannot be formed in this region P, this is defined as a forbidden region where the placement of the transistors is forbidden when a circuit is designed.
- this forbidden region exhibits the severe influence as the new subject of the miniaturization.
- the technique is desired which can reduce the forbidden region in the boundary between the thin film Tr region and the thick film Tr region.
- the technique is desired which can attain the miniaturization of the semiconductor circuit efficiently without any waste of regions in a semiconductor chip.
- JP-P2005-129711A discloses a semiconductor device and a method of manufacturing the same.
- This method of manufacturing the semiconductor device includes: a step of forming a bottom oxide film on a semiconductor substrate of a memory transistor formation region and a peripheral circuit transistor formation region; a step of forming a nitride film on the bottom oxide film; a step of forming a top oxide film on the nitride film; a step of removing the top oxide film, the nitride film and the bottom oxide film in the peripheral circuit transistor formation region to expose the surface of the semiconductor substrate in the peripheral circuit transistor formation region; a step f executing a heat treatment in the atmosphere having nitrogen and oxygen in each of the semiconductor substrate of the peripheral circuit transistor formation region and the top oxide film of the memory transistor formation region; and a step of forming a gate insulating film on the semiconductor substrate in the peripheral circuit transistor formation region.
- An object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the forbidden region in the boundary between the thin film Tr region and the thick film Tr region.
- Another object of the present invention is to provide a method of manufacturing a semiconductor device that can attain the miniaturization of the semiconductor device efficiently without any waste of regions in a semiconductor chip.
- the present invention provides a method of manufacturing a semiconductor device comprising: (a) forming a first insulating film and a nitride film on a semiconductor substrate in this order; (b) removing said first insulating film and said nitride film in a first region while leaving said first insulating film and said nitride film in a second region; (c) forming a second insulating film on said semiconductor substrate in said first region, wherein a thickness of said second insulating film is different from that of said first insulating film, and a third insulating film is formed on said nitride film in said second region along with the formation of said second insulating film; and (d) removing said third insulating film and said nitride film in said second region.
- said step (d) may include: removing said third insulating film by using a chemical solution which dissolves said third insulating film rather than said nitride film; and removing said nitride film by using a chemical solution which dissolves said nitride film rather than said second insulating film.
- said step (d) may include: removing said third insulating film and said nitride film in said second region by a dry-etching method.
- step (d) may further include: executing a heat treatment of said semiconductor substrate in an atmosphere having nitrogen and oxygen after said removing by the dry-etching method.
- said step (b) may include: removing said first insulating film and said nitride film in said first region by a dry-etching method.
- said step (b) may further include: executing a heat treatment of said semiconductor substrate in an atmosphere having nitrogen and oxygen after said removing by the dry-etching method.
- said step (d) may include: removing said third insulating film by using a chemical solution which dissolves said third insulating film rather than said nitride film; and removing said nitride film by using a chemical solution which dissolves said nitride film rather than said second insulating film
- said step (d) may include: removing said third insulating film and said nitride film in said second region by a dry-etching method.
- said step (d) may further include: executing a heat treatment of said semiconductor substrate in an atmosphere having nitrogen and oxygen after said removing by the dry-etching method.
- said first insulating film may be one of a silicon oxide film and a silicon oxynitride film.
- Said second insulating film may be one of a silicon oxide film and a silicon oxynitride film.
- Said nitride film may be a silicon nitride film.
- said step (b) may include: removing said first insulating film and said nitride film in said first region by a dry-etching method.
- said step (b) may further include: executing a heat treatment of said semiconductor substrate in an atmosphere having nitrogen and oxygen after said removing by the dry-etching method.
- said step (c) may include: executing an oxidation of said semiconductor substrate.
- Said second insulating film may be composed of an oxide film formed by said heat treatment and an oxide film formed by said oxidation on said semiconductor substrate.
- Said third insulating film may be composed of an oxide film formed by said heat treatment and an oxide film formed by said oxidation film on said nitride film.
- said step (d) may include: removing said third insulating film by using a chemical solution which dissolves said third insulating film rather than said nitride film; and removing said nitride film by using a chemical solution which dissolves said nitride film rather than said second insulating film.
- said step (d) may include: removing said third insulating film and said nitride film in said second region by a dry-etching method.
- said step (d) may further include: executing a heat treatment of said semiconductor substrate in an atmosphere having nitrogen and oxygen after said removing by the dry-etching method.
- the method of manufacturing a semiconductor device may further include: (e) forming a first gate of a first transistor at a predetermined position in said first region, and a second gate of a second transistor at a predetermined position in said second region; and (f) forming a source and a drain of said first transistor with respect to said first gate in a self-alignment manner, and a source and a drain of said second transistor with respect to said second gate in a self-alignment manner.
- FIGS. 1A to 1C are sectional views showing a method of manufacturing a dual gate oxide film of a conventional technique
- FIGS. 2A to 2C are sectional views showing a method of manufacturing a dual gate oxide film of a conventional technique
- FIG. 3 is a sectional view showing a semiconductor device that is manufactured in an embodiment of a method of manufacturing a semiconductor device according to the present invention
- FIGS. 4A to 4C are sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.
- FIGS. 5A to 5C are sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.
- FIGS. 6A to 6C are sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.
- FIG. 3 is a sectional view showing one example of the semiconductor device that is manufactured in the embodiment of the method of manufacturing the semiconductor device according to the present invention
- a semiconductor device 20 has a thick film Tr region (the left side of the drawing) and a thin film Tr region (the right side of the drawing).
- the thick film Tr region is a region where thick film gate transistors are formed.
- the thick film gate transistor has the gate oxide film of a thick film thickness.
- the thin film Tr region is a region where thin film gate transistors are formed.
- the thin film gate transistor has the gate oxide film of a thin film thickness.
- a thick film gate transistor 19 is formed between isolation regions (STI) 10 installed on a semiconductor substrate 1 .
- a thin film gate transistor 18 is formed between the isolation regions 10 installed on the semiconductor substrate 1 .
- the thick film gate transistor 19 includes a source/drain region 17 a , a source/drain region 17 b , a thick gate oxide film 5 and a gate 16 .
- the source/drain region 17 a and the source/drain region 17 b are formed at a predetermined interval on the upper surface of the semiconductor substrate 1 .
- the thick gate oxide film 5 is formed on the semiconductor substrate 1 between the source/drain region 17 a and the source/drain region 17 b (a channel region), and has a relatively thick film thickness.
- the thick gate oxide film 5 includes a first oxide film 5 a and a second oxide film 5 b .
- the gate 16 is formed on the thick gate oxide film 5 .
- the thin film gate transistor 18 includes a source/drain region 7 a , a source/drain region 7 b , a thin gate oxide film 2 and a gate 6 .
- the source/drain region 7 a and the source/drain region 7 b are formed at a predetermined interval on the upper surface of the semiconductor substrate 1 .
- the thin gate oxide film 2 is formed on the semiconductor substrate 1 between the source/drain region 7 a and the source/drain region 7 b (a channel region), and has a relatively thin film thickness.
- the gate 6 is formed on the thin gate oxide film 2 .
- the thick film gate transistor 19 and the thin film gate transistor 18 shown in FIG. 3 are indicated as examples. The present invention is not limited to these examples. If the transistor (including a memory cell) having the gate oxide film of the thick film thickness is formed in the thick film Tr region and if the transistor (including a memory cell) having the gate oxide film of the thin film thickness is formed in the thin film Tr region, the structure of each transistor does not matter.
- FIGS. 4A to 4C , FIGS. 5A to 5C and FIGS. 6A to 6C are sectional views showing the embodiment of the method of manufacturing the semiconductor device according to the present invention.
- the case of manufacturing the semiconductor device 20 shown in FIG. 3 will be explained below.
- the isolation regions (STI: Shallow Trench: Isolation) 10 are firstly formed on the semiconductor substrate 1 .
- the semiconductor substrate 1 after the isolation is cleaned by a cleaning process.
- the thin gate oxide film 2 is formed by an oxidizing process so as to cover the surface of the semiconductor substrate 1 .
- the thin gate oxide film 2 has a film thickness of, for example, 3 nm and is exemplified as a silicon oxide film.
- the oxidization is executed by an ISSG (In Situ Steam Generation) method, for example, at 1050 degrees Celsius and H 2 :5% atmosphere. After that, as shown in FIG.
- ISSG In Situ Steam Generation
- a nitride film 3 having a film thickness of about 15 nm is formed by a CVD method so as to cover the surface of the thin gate oxide film 2 .
- the nitride film 3 is exemplified as a silicon nitride film.
- a resist 4 is patterned by a lithography process such that the thin film Tr region is masked with the resist 4 while the thick film Tr region is not masked.
- the nitride film 3 and the thin gate oxide film 2 in the thick film Tr region are etched by a dry-etching method.
- the dry etching is executed, for example, under etching gas: Ar+CF 4 . Since the dry-etching method is used, as compared with the conventional method that removes the oxide film by using the chemical solution, it is possible to exactly form the boundary between the thin film Tr region and the thick film Tr region.
- the nitride film 3 is used as the hard mask and the dry-etching method is further used, it is possible to protect the irregularity in the boundary shape that is caused by the invasion of the chemical solution. Consequently, the improper boundary is not generated whose film thickness is improper such as the end 120 shown in FIG. 2B , and there is no bad influence on the subsequent processes.
- the resist 4 in the thin film Tr region is removed.
- annealing is executed in the mixed atmosphere of nitrogen and oxygen.
- the thin first oxide film 5 a is formed on the surface of the semiconductor substrate 1 in the thick film Tr region.
- the oxide film 5 a ′ is formed on the surface of the nitride film 3 in the thin film Tr region.
- the film thickness of the first oxide film 5 a is, for example, 0.3 nm, and the first oxide film 5 a is exemplified as the silicon oxide film.
- the film thickness of the oxide film 5 a ′ is thinner than that of the first oxide film 5 a , and the oxide film 5 a ′ is exemplified as the silicon oxide film.
- a thick second oxide film 5 b is formed by the oxidizing process so as to cover the surface of the thermal first oxide film 5 a .
- the second oxide film 5 b has a film thickness of, for example, 5.5 nm, and is exemplified as the silicon oxide film.
- the oxidization is executed by the ISSG method, for example, at 1050 degrees Celsius, H 2 :5% atmosphere. Consequently, the thick gate oxide film 5 is formed in the thick film Tr region.
- the thin thermal first oxide film 5 a and the thick second oxide film 5 b are laminated in this order.
- a thin oxide film 5 b ′ is formed on the thin oxide film 5 a ′.
- the thin oxide films 5 b ′ and 5 a ′ on the nitride film 3 in the thin film Tr region is firstly wet-etched by using an acid chemical solution. This leads to remove the oxide films 5 b ′ and 5 a ′ on the nitride film 3 in the thin film Tr region.
- the first and second oxide films 5 a and 5 b in the thick film Tr region are wet-etched just a little, which does not cause any problem.
- the nitride film 3 in the thin film Tr region is removed by using the chemical solution which reacts with only a nitride film without reacting with an oxide film.
- Such chemical solution is exemplified as a high temperature phosphoric acid.
- the thick film Tr region the thick gate oxide film 5 is formed on the surface of the silicon substrate 1 .
- the thin gate oxide film 2 is formed on the surface of the silicon substrate 1 .
- the oxide films 5 b ′ and 5 a ′ are removed by using the chemical solution which reacts with an oxide film rather than a nitride film, and the nitride film 3 in the thin film Tr region is removed by using the chemical solution which reacts with only a nitride film without reacting with an oxide film.
- the improper boundary whose film thickness is improper such as the end 120 shown in FIG. 2B , is not generated.
- the resist patterning process, the dry-etching process and the annealing process shown in FIGS. 5A , 5 B and 5 c may be used as the processes for removing the oxide films 5 a ′ and 5 b ′ and the nitride film 3 in the thin film Tr region.
- the chemical solution since the chemical solution is not used at all, the dimensional control can be executed further accurately.
- a metal film is formed by using a sputtering method so as to cover a surface of the thick gate oxide film 5 in the thick film Tr region and a surface of the thin gate oxide film 2 in the thin film Tr region.
- the metal film and the thick gate oxide film 5 are patterned by the lithography and dry-etching processes so as to form the gate of the thick film gate transistor 19 at the predetermined position in the thick film Tr region.
- the metal film and the thin gate oxide film 2 are patterned by the lithography and dry-etching processes so as to form the gate of the thin film gate transistor 18 at the predetermined position in the thin film Tr region.
- ion implantation is executed in a self-alignment manner so as to form the source/drain regions (diffusion layers) 17 a and 17 b of the thick film gate transistor 19 and the source/drain regions (diffusion layers) 7 a and 7 b oft the thin film gate transistor 18 .
- the thick film gate transistor 19 is formed in the thick film Tr region
- the thin film gate transistor 18 is formed in the thin film Tr region.
- the gate oxide films having the film thicknesses different from each other can be formed on the same substrate. That is, although the conventional technique uses the chemical solution and performs the wet-etching and partially removes the oxide film, the present invention uses the nitride film as the hard mask and further uses the dry-etching and partially removes the oxide film. Consequently, it is possible to protect the invasion of the chemical solution in the boundary the between the thick film Tr region and the thin film Tr region and also possible to avoid the improper situation of the film thickness in the boundary.
- the side-etching caused by the chemical solution is not substantially generated in the boundary between the thin film Tr region and the thick film Tr region.
- the side-etching caused by the chemical solution is not substantially generated in the boundary between the thin film Tr region and the thick film Tr region.
- the dimension control becomes easy in the processes of manufacturing the semiconductor device.
- At least one of the thin gate oxide film 2 and the thick gate oxide film 5 may be silicon oxynitride film.
- the present invention it is possible to reduce the forbidden region in the boundary between the thin film Tr region and the thick film Tr region. And, the miniaturization of the semiconductor device can be attained efficiently without any waste of regions in a semiconductor chip.
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- Manufacturing & Machinery (AREA)
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Abstract
Description
Claims (17)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2006072048 | 2006-03-16 | ||
JP2006-072048 | 2006-03-16 | ||
JP2007014254A JP2007281425A (en) | 2006-03-16 | 2007-01-24 | Method for manufacturing semiconductor device |
JP2007-014254 | 2007-01-24 |
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US20070218666A1 US20070218666A1 (en) | 2007-09-20 |
US7585736B2 true US7585736B2 (en) | 2009-09-08 |
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US11/723,092 Expired - Fee Related US7585736B2 (en) | 2006-03-16 | 2007-03-16 | Method of manufacturing semiconductor device with regard to film thickness of gate oxide film |
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JP (1) | JP2007281425A (en) |
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KR100910462B1 (en) * | 2007-09-07 | 2009-08-04 | 주식회사 동부하이텍 | Semiconductor device and method for fabricating the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1197383A (en) | 1997-09-11 | 1999-04-09 | Lg Semicon Co Ltd | Deposition of electrode protective film in semiconductor device |
JP2001308198A (en) | 2000-04-27 | 2001-11-02 | Ricoh Co Ltd | Manufacturing method of semiconductor device |
US6468867B1 (en) * | 2001-07-30 | 2002-10-22 | Macronix International Co., Ltd. | Method for forming the partial salicide |
JP2005005668A (en) | 2003-06-13 | 2005-01-06 | Hynix Semiconductor Inc | Manufacturing method of dualgate oxide |
JP2005129711A (en) | 2003-10-23 | 2005-05-19 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
JP2005286141A (en) | 2004-03-30 | 2005-10-13 | Seiko Epson Corp | Manufacturing method of semiconductor device |
US20050239248A1 (en) * | 2004-04-22 | 2005-10-27 | Lee Seok K | Method for manufacturing nonvolatile memory device |
US6979623B2 (en) * | 2003-12-17 | 2005-12-27 | Texas Instruments Incorporated | Method for fabricating split gate transistor device having high-k dielectrics |
-
2007
- 2007-01-24 JP JP2007014254A patent/JP2007281425A/en active Pending
- 2007-03-16 US US11/723,092 patent/US7585736B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1197383A (en) | 1997-09-11 | 1999-04-09 | Lg Semicon Co Ltd | Deposition of electrode protective film in semiconductor device |
JP2001308198A (en) | 2000-04-27 | 2001-11-02 | Ricoh Co Ltd | Manufacturing method of semiconductor device |
US6468867B1 (en) * | 2001-07-30 | 2002-10-22 | Macronix International Co., Ltd. | Method for forming the partial salicide |
JP2005005668A (en) | 2003-06-13 | 2005-01-06 | Hynix Semiconductor Inc | Manufacturing method of dualgate oxide |
JP2005129711A (en) | 2003-10-23 | 2005-05-19 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
US6979623B2 (en) * | 2003-12-17 | 2005-12-27 | Texas Instruments Incorporated | Method for fabricating split gate transistor device having high-k dielectrics |
JP2005286141A (en) | 2004-03-30 | 2005-10-13 | Seiko Epson Corp | Manufacturing method of semiconductor device |
US20050239248A1 (en) * | 2004-04-22 | 2005-10-27 | Lee Seok K | Method for manufacturing nonvolatile memory device |
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Publication number | Publication date |
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JP2007281425A (en) | 2007-10-25 |
US20070218666A1 (en) | 2007-09-20 |
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