JPS62193260A - Manufacture of composite semiconductor device - Google Patents

Abstract

PURPOSE:To monolithically integrate the functional element, utilizing the base semiconductor substrate, and other functional element to be formed on a laminated semiconductor substrate by a method wherein a semiconductor substrates, showing the same conductivity type but having a difference in density of impurities contained, are adhered. CONSTITUTION:The first and the second silicon oxide layers 3 and 4 are coated on the surface of an N<+> type silicon semiconductor substrate 1 and an N<-> type semiconductor substrate 2, they are polished and closely contacted in the clean atmospheric air leaving the moisture adsorbed on the mirror-faced surface of an insulator as it is. Then, an oxide layer is provided on the surface of a composite semiconductor substrate, an etching is performed only on the part where a power element is expected to be formed, and the first semiconductor substrate 1 is exposed. Grooves 7... to be used for trench isolation are formed on the second semiconductor substrate 1 provided on a recessed part 6 by performing an RIE (reactive ion etching) method, an oxide layer 8 is coated on the grooves 7..., and a polycrystalline silicon layer 9 is deposited thereon. Then, a flat surface is formed by performing an RIE method, a new layer is formed on the whole surface of the substrate, a power MOSFET (metal oxide semiconductor field effect transistor) is formed on said epitaxially grown layer, and besides, a C/MOS and a small signal are formed on the second substrate 2.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a composite semiconductor device, and particularly to a method for manufacturing a composite semiconductor device, which is obtained by bonding a plurality of semiconductor substrates (referred to as Ishitoshi bonding, the technical content of which will be described later). It is suitable for a composite semiconductor device that effectively utilizes element isolation technology on a composite semiconductor substrate and includes a high breakdown voltage Ic and a power element.

(Technical Background of the Invention) Conventionally, collector junctions of diodes, bipolar transistors, etc., and drain junctions of double-diffused (103) FETs, etc., are used with the PN junction in a reverse bias state, but the series resistance generated at that time is In order to reduce the number of conductivity, a laminated structure is used in which an N- type semiconductor substrate is formed using an N0 conductivity type semiconductor substrate as a base, and impurities of the opposite conductivity type are introduced into this N- type semiconductor substrate to form a semiconductor element. It is common to form

Furthermore, the underlying N+ type semiconductor substrate is made sufficiently thick to improve breakdown voltage and regional strength.

By keeping a sufficient distance between the bottom of the PN junction obtained by introducing this impurity and the N0 type semiconductor substrate, "Reach Th
It is common to prevent the breakdown phenomenon caused by "rough".

The so-called epitaxy cell growth method is used to obtain the above-mentioned layered structure, but when there is a difference in the concentration of impurities contained in the underlying semiconductor substrate, outward diffusion (A) of the impurities contained in the underlying semiconductor substrate is used.
The reality is that strict concentration control cannot be achieved not only in the boundary area but also in the boundary area due to IJtOdiffusion.

However, a bonding technique for integrating semiconductor substrates with different concentrations of impurities has been developed, and the applicant has already filed an application for this technique. That is, by closely adhering the mirror surfaces of semiconductor substrates that are somewhat damp, a composite semiconductor substrate can be obtained which has sufficient mechanical strength and can be handled as a single semiconductor substrate.

It is assumed that a crystal slightly different from the original crystal (on the BU) is formed on this adhesion surface, but it does not become a thermal or electrical barrier, and moreover, it has a PN junction formed on this composite semiconductor substrate. It has also been confirmed that the functional elements can sufficiently exhibit the necessary electrical characteristics. This bonding technique is not limited to bonding silicon semiconductor substrates together, but can also be applied to bonding silicon oxide bonds attached to the surface of this silicon semiconductor substrate.

(Problems in the background art) In recent years, the breakdown voltage characteristics required of semiconductor devices have tended to increase, and this trend has become noticeable recently, and there is also a strong demand for monolithic integration of multiple functional devices. This is the current situation.

With regard to this breakdown voltage characteristic, the resistance is small due to the N-type semiconductor substrate laminated on top of the N-type semiconductor substrate as the base during the above-described laminated structure, and the entire base substrate can be regarded as an electrode. Moreover, since the end of the PN junction formed on the N-type semiconductor substrate is exposed on the surface of the N-type semiconductor substrate, the electric field to the curved part formed from the vicinity of this end is applied to the N-junction that continues from this curved part. The electric field is larger than the electric field for a flat portion substantially along the surface of the type semiconductor substrate, and is one of the factors that prevents the high breakdown voltage required for semiconductor devices.

In order to form this layered structure, the epitaxial method has to be adopted as mentioned above, and ReachThrough
To avoid the gh phenomenon, the thickness of the deposited layer is increased,
There is also a field limiting type in which the depletion layer extends in the direction along the surface of the semiconductor substrate and a field plate type in which the junction electrode is extended on an insulator that protects the PN junction end, but these are not preferred for improving the degree of integration.

Furthermore, this method is difficult to adopt in the case of a composite semiconductor device in which a plurality of functional elements are monolithically integrated, since effective integration is essential. This composite semiconductor device requires isolation technology, and in addition to requiring a bias circuit to apply a reverse bias in PN junction isolation, the P+ diffusion reservoir is grounded to increase the potential of the island region and electrically connect this island region. This creates a complicated circuit, and it also has the disadvantage that it is likely to generate unnatural elements.

On the other hand, the insulator separation method has the advantage of not requiring this bias circuit, but it is economically disadvantageous because it uses thick polycrystalline silicon as the substrate, and one side of the resulting substrate is insulated. It is made up of objects and cannot be used as a current path.

[Purpose of the invention]

The present invention skillfully applies element isolation technology to a composite semiconductor substrate using bonding technology, and is a novel method that monolithically integrates functional elements using this underlying semiconductor substrate and other functional elements formed on the laminated semiconductor substrates. The present invention provides a method for manufacturing a complex semiconductor device.

[Summary of the Invention] In order to achieve the above object, in the present invention, an insulating layer deposited on the surface of a semiconductor substrate having the same conductivity type but different impurity concentrations is mirror-finished, and the mirror-finished surfaces are slightly moistened. A composite semiconductor substrate is obtained in which the bidirectional conductive substrates are integrated by the bonding layer. The semiconductor substrate constituting this substrate with a low concentration of impurities is selectively etched to expose the underlying semiconductor substrate with a high concentration of impurities.
A method was adopted in which a groove for trench rsOIatiOn was provided, and a power element was formed in the epitaxial cell layer provided on the exposed semiconductor substrate, and a functional element was formed by the groove for trench l5olation and the island region obtained from the insulator.

[Embodiments of the invention]

The present invention will be described in detail with reference to FIGS. 1 a-e to 2 a-f. First, the joining technique will be explained.

Specific resistance 5-6.5Ω・cm as a semiconductor substrate for bonding
An N-type silicon semiconductor substrate 1 having a resistivity of 2 to 5 Ω·cm and an N-type semiconductor substrate 2 having a resistivity of 2 to 5 Ω·cm are prepared.
The first and second silicon oxide layers 3 and 4 having a thickness of about 0,000 Å are coated and polished to form first and second mirror surfaces with a roughness of 500 Å or less. Depending on the surface condition of the polishing process, oils and fats may be removed in a pretreatment process. Next, it is washed with clean water for several minutes, and dehydration treatment such as spinner treatment is performed at air temperature to remove excess moisture while leaving the moisture assumed to have been adsorbed on the mirror surface of the insulating layer intact. However, avoid heating and drying at temperatures above 100°C, where most of this adsorbed moisture will evaporate.

The silicon semiconductor substrates that have undergone this treatment are placed in a clean atmosphere of class 1 or lower, for example, and are closely bonded to each other with substantially no foreign matter (dust) intervening between the mirror surfaces to form a composite semiconductor substrate. . Furthermore, this composite semiconductor substrate is
The bonding strength can also be increased by heat treatment at a temperature of 1000'C or higher, preferably 1000'C to 12000C. As the atmosphere during the bonding process, in addition to the air, oxygen or a mixed atmosphere of both can be used, and a similar atmosphere is also used to increase the bonding strength17.

By the way, in this bonding process, polar groups are formed by the water washing process on the mirror surface, and the bonding caused by this causes B
Since a bonding layer 5 that is somewhat different from the ulk structure is obtained, it is assumed that a composite semiconductor substrate in which the amphiphilic conductive substrate is integrated can be obtained, and it is necessary that the functional element formed here has been verified to have the desired semiconductor characteristics. .

Furthermore, since the boundary of the bonding layer 5 formed on this composite semiconductor substrate may change depending on the applied heat load, the bonding layer in the present invention has the same conductivity type and has a different concentration of impurities. This term does not only mean sharply dividing the boundaries of semiconductor substrates in a certain laminated structure, but also includes the above-mentioned fluctuation state.

A cross-sectional view of the composite semiconductor substrate after the bonding process is completed is shown in FIG. 1a.

In this composite semiconductor substrate, the N+ type first semiconductor substrate 1 has a thickness of approximately 530 mm, and the N- type semiconductor substrate 2 laminated thereon is polished and formed to a thickness of approximately 20 mm after the bonding process.

Next, an oxide layer is provided on the surface of this composite semiconductor substrate, and only the positions where the power elements are to be formed are covered with known PEP (Pho).
to Engraving Process). That is, after a part of this oxide film is removed, the second semiconductor substrate is further etched, and the reaction stops when the second oxide layer is reached, but due to the HFff1 principle, the first and second oxide layers are etched. Also, the bonding layer 5 is dissolved away to expose the first semiconductor substrate 1. As a result, a recessed portion 6 is obtained as shown in FIGS.

Next, a trench l is formed in the second semiconductor substrate 2 provided with this recess 6.
The grooves 7 for 5olation are formed by a known RIE method, and as is clear from the purpose of this method, they reach the second oxide layer 4, and the cross section thereof is shown in FIG. However, in an example in which a bipolar transistor having a buried layer is installed in the second semiconductor substrate 2, a trench is formed up to the buried layer.

In the case of installing this bipolar transistor, an N+ region is provided in the second semiconductor substrate by ion implantation prior to the bonding process, and then the bonding process is performed through the oxide layer coating and mirror polishing process as described above. do.

Subsequently, the process moves to an oxidation step. As described above, a power element is formed in the recess 6, but an oxide mask is provided here in order to deposit an epitaxial growth layer, and an oxide layer 8 is coated in the trench l5olation groove 7. This cross section is shown in Figure 1. In order to distinguish this oxide layer from other oxide layers, it will be referred to as a third oxide layer 8 from now on. Of course, the oxide layer deposited on the surface of the second semiconductor substrate 2 is also generically referred to.

A polycrystalline silicon layer 9 is deposited to a thickness of about 25 μm in a reduced pressure atmosphere of 1 torr on the surface of the composite semiconductor substrate on which the recesses 6 and grooves 7 have been formed, and the recesses 6 have a specific resistance of 40 to 50Ω.
'cm surface concentration about 1014 atoms/CC (7)
While growing the epitaxial growth layer, the trenches 7 are filled with oxide. This groove is about 20JJI deep! !
However, since the mean free path of silicon gas in this reduced pressure atmosphere is several hundreds -, sufficient burial is possible. A diagram of this deposited state is shown in FIG. 1C, and a state in which the epitaxial layer has grown is shown in FIG. 1D.

Next, after coating this composite semiconductor substrate with 0FPR800 (a positive resist manufactured by Tokyo Ohka Co., Ltd.), a so-called etch-back is performed by the RIE method to form a flat surface. This RIE
The conditions are BCA36SCCM α and 23SCCM
Si Cf1q 18SCC14 Pressure 15 Pass Force P
Then, a new oxide layer is formed over the entire surface of the composite semiconductor substrate, which will serve as a lid for the epitaxial growth layer made of polycrystalline silicon. Prior to this, the third oxide layer 8 previously deposited after this planarization step is dissolved away.

The state in which this new oxide layer has been deposited is shown in the cross-sectional view of FIG. 2a. The steps for forming a power HO3FET on this epitaxial growth layer, and further forming a C/MO3 and a small signal underlayer on the second semiconductor substrate 2 will be described below.

Cap of epitaxial growth layer, ie CapOxidat
A part of the oxide film 10 formed flat by ion is removed by a known PEP process to reduce the thickness. This is because B is ion-implanted, P-Wel 1 layer 11, power H
This method is used to adjust the implantation depth in order to form the guard ring 11 and base contact for the O3FET, and it is the usual method to perform the SlumDinO process after ion implantation.

The surface concentration of the P-Wel1 layer and the like formed by this ion implantation process is about 1017 atoms/CIi.

Next, there is an oxide film 1 existing at the planned position for forming the gate of the C/803 element and the planned position for forming the gate of the power HO3FET.
0 is removed by a known PEP process to form a gate oxide film 1.
After providing 1.12.13, B is separately implanted through the gate oxide film 11.12 in order to control vth of the N channel and P channel of the C/HO3 element.

After that, after depositing the polycrystalline silicon layer 14, C, D, E (Che
The portions of the gate oxide films 11 to 13 other than those that will become the electrodes 14, 15, and 16 are removed by a mical ()ry etching) method. Figure 2 shows a cross-sectional view before C, D, and E patterning, and here the Po1ySi layer 1
The resist layer necessary for patterning No. 4 is described.

Here, the most important part of IO3FET is P-b.
In forming the ody part, a resist is applied as an implant mask except for the gate oxide film 13 on which the gate electrode 16 is laminated and the oxide film on the position where the small signal transistor is to be formed, and then B is ion-implanted. In this case p −b
The surface area of the ody part 7 is approximately 1016 atoms/Cl
That of 1tP base 18 is 1017 atoIIls/
A conventional reannealing process is performed to achieve a CIi level.

A cross-sectional view after this step is shown in FIG. 2G, and the process proceeds to the formation of the source region 19 as shown in FIG. 2d. Since this source region 19 is formed by P ion implantation, a small signal NP
Emitter 20C/803 of N transistor Source and drain regions 21 formed in N channel MO3.
22. Channel stopper 23 and back gate 24 provided in the P-channel MO3 region, and further NPNI-
Collector contact 25 of transistor, and also power HO
3FET channel stoppers 26 and 27 are formed at the same time. This P surface concentration is approximately 1020 atoms/C
It is necessary in l11. Further, an N+ region 28 is provided in the n region adjacent to the second oxide layer 4 to function as a channel stopper.

Next, as shown in FIG.
A P1 area is formed. That is, a channel stopper 29, a back gate 30 .
Source and drain regions 3 of P-channel MO3
1.32, NPN transistor base contact 33
Set up.

After forming each of these regions, annealing treatment is repeatedly performed at 1100° C. in an N2 atmosphere. This is done by assuming that the sum of emitter grounded currents jq in the NPNI transistor is 11 constants.

Subsequently, 5,000 and-button CVI membranes, BPSG
After laminating 8,000 people and 1,000 people of p3G in this order, phosphorus oxychloride was deposited at 900°C to perform phosphorus book ring, and openings were formed using a known PEP process to form Afl-3.
Perform sintering of the i layer. Finally, one level of P (plasma) layer 32 is coated as a surface stabilizing layer, and Nch,
A composite semiconductor device consisting of a 07MO3 consisting of a MOS, a PC/OS, an NPN small signal transistor, and a Power) iosFET was obtained, and this is shown in FIG.

(Effects of the Invention) In the composite semiconductor device according to the present invention, small signal transistors and C/)! O3 element and power 1-103FET as an element that utilizes the vertical direction
Form into seven norimics. Therefore, by adopting a method to obtain a composite semiconductor substrate by bonding mirror surfaces formed on insulators covering the surfaces of semiconductor substrates having the same conductivity type and different impurity levels, outward diffusion in the necessary stacked structure can be achieved. Ensured concentration control.

On the other hand, this insulating layer is used to form an essential island region, and an insulating layer is also provided in the trench l5olation vortex. Previous) For small functional devices, base) A part of the substrate (composite semiconductor because there are different types) was removed, an epitaxial layer was grown, and at the same time an insulator was buried in the trench l5olation vortex. . For this purpose, we adopted a reduced pressure epitaxial method to achieve embedding in the groove.

In this way, the present invention employs a method that minimizes the epitaxial method and polishing step, which are expensive steps in forming the functional element, to reduce the product cost.

[Brief explanation of drawings]

Figures 1 a to d are cross-sectional views showing the steps of the present invention, and Figures 2 a to d.
Similarly, f is a sectional view showing the device manufacturing process according to the present invention.

Claims (1)

[Claims] A first insulating layer covering the surface of a first semiconductor substrate having a certain impurity concentration is provided with a first mirror surface, and a second insulating layer having a lower impurity concentration and covering the surface of a second semiconductor substrate of the same conductivity type. A composite semiconductor substrate is obtained in which a second mirror surface is formed on and a bonding layer is formed by closely contacting both mirror surfaces, and the composite semiconductor substrate is bonded to the second semiconductor substrate and the adjacent first and second insulating layer portions. At the same time as removing the layer portion to expose the first semiconductor substrate, forming a separation groove from the surface of the second semiconductor substrate to the second insulating layer, and depositing a third insulating layer on the wall surface of the separation groove. , a power element utilizing the first semiconductor substrate is provided in an epitaxial growth layer obtained by depositing a polycrystalline silicon layer under reduced pressure on the separation trench and the exposed surface of the first semiconductor substrate;
A method for manufacturing a composite semiconductor substrate, characterized in that a functional element is provided in an island region of the second semiconductor substrate obtained by a second insulating layer.