JP2007110029A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device where a NAND cell unit is built on a partial SOI substrate and its manufacturing method. <P>SOLUTION: This semiconductor memory device consists of a semiconductor substrate, a semiconductor layer which has been formed on the above semiconductor substrate via an insulating film and has been made contact to the above semiconductor substrate via an opening created on the above insulating film, a number of electrically rewritable non-volatile memory cells which have been formed on the above semiconductor substrate and have been connected in series, and a NAND cell unit with a first selective gate transistor and a second selective gate transistor placed at both ends. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device configured using electrically rewritable nonvolatile memory cells, and more particularly to an EEPROM having a NAND cell unit formed on a partial SOI substrate.

  A NAND flash memory is known as one of the EEPROMs. Since the NAND flash memory includes a plurality of electrically rewritable nonvolatile memory cells connected in series to form a NAND cell unit, the unit cell area is smaller than that of the NOR type, and the capacity can be easily increased.

  Since the NAND flash memory uses the FN tunnel current for data writing, it consumes less current than the NOR type using hot carrier injection. For this reason, it is possible to increase the capacity of a page to be written at the same time, thereby enabling a substantially high-speed data writing.

In order to further reduce the cell size of the NAND flash memory, it is necessary to reduce the element isolation region. However, miniaturization of the element isolation region brings about a decrease in breakdown voltage between cells. In order to realize cell miniaturization without causing a reduction in breakdown voltage, a technique of forming a memory cell array composed of NAND cell units on an SOI (Silicon On Insulator) substrate is effective. Such a technique has already been proposed (see, for example, Patent Document 1).
JP 2000-174241 A

  An object of the present invention is to provide a semiconductor memory device in which a NAND cell unit is formed on a partial SOI substrate, and a manufacturing method thereof.

A semiconductor memory device according to one embodiment of the present invention includes:
A semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate via an insulating film and in contact with the semiconductor substrate via an opening opened in the insulating film;
A plurality of series-connected electrically rewritable nonvolatile memory cells formed in the semiconductor layer; and a NAND cell unit including first and second select gate transistors disposed at both ends thereof.

A method of manufacturing a semiconductor memory device according to another aspect of the present invention includes:
Forming an insulating film on the single crystal semiconductor substrate;
Forming an opening in the insulating film;
Depositing an amorphous or polycrystalline semiconductor layer in contact with the semiconductor substrate through the opening on the insulating film in which the opening is formed;
Performing a crystallization annealing process on the semiconductor layer;
Forming a NAND cell unit comprising a plurality of electrically rewritable non-volatile memory cells connected in series and select gate transistors disposed at both ends thereof in the semiconductor layer.

  According to the present invention, it is possible to provide a semiconductor memory device in which a NAND cell unit is formed on a partial SOI substrate and a manufacturing method thereof.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a plan view of a memory cell array of a NAND flash memory according to an embodiment, FIG. 2 is a cross-sectional view in the bit line (BL) direction (II ′ cross-sectional view in FIG. 1), and FIG. FIG. 4 is a sectional view taken along the selection gate line (SGD) (II-II ′ sectional view of FIG. 1), and FIG. 4 is a sectional view taken along the word line (WL) (III-III ′ sectional view of FIG. 1). .

  The element substrate is an SOI (Silicon On Insulator) substrate having a silicon layer 3 formed by being separated by a silicon oxide film 2 on a single crystal silicon substrate 1. The silicon layer 3 is not completely electrically separated from the silicon substrate 1 and is connected to the silicon substrate 1 through an opening 4 opened in the oxide film 2. In this sense, the SOI substrate of this embodiment is hereinafter referred to as a “partial SOI substrate”.

  In the memory cell array region, the silicon substrate 1 has a well structure in which an n-type well 1b is formed in a p-type silicon substrate 1a and a p-type well 1c is further formed in the n-type well 1b.

  The silicon layer 3 is obtained by (re) crystallizing an n-type polycrystalline silicon layer or an amorphous silicon layer deposited on the oxide film 2 by annealing. In the crystallization annealing, crystallization proceeds using the substrate crystal exposed in the opening 4 as a seed. The film thickness of the silicon layer 3 is, for example, 1 nm or more, and the gate length of the memory cell is 3 L or less. The thickness of the oxide film 2 is, for example, 1 nm or more and 4 L or less. The total film thickness of the silicon layer 3 and the oxide film 2 may be about the gate length L.

  As shown in FIGS. 3 and 4, the silicon layer 3 in which the p-type diffusion layer 31 is partially formed is partitioned as a striped element formation region 14 separated from each other by the element isolation insulating film 12. A floating gate 6 is formed on the silicon layer 3 as a charge storage layer via a tunnel oxide film 5, and a control gate 8 is formed on the floating gate 6 via an inter-gate insulating film 7. The floating gate 6 is separated for each memory cell, and the control gate 8 is formed as a word line WL (WL0 to WL15) that is continuous in one direction and is common to a plurality of memory cells. Here, a polycrystalline silicon film is used as the floating gate, but an insulating charge storage layer can also be used.

  FIG. 5 shows an equivalent circuit of the memory cell array. Select gate transistors SG1 and SG2 are arranged at both ends of a plurality of series-connected memory cells M0 to M15 constituting the NAND cell unit NU. The gates of these selection gate transistors SG1 and SG2 are in a state in which the stacked films of gate wiring material films such as polycrystalline silicon, which are the same as the floating gate 6 and the control gate 8, are in contact with each other. The selection gate lines SGD and SGS are formed in parallel with the word lines WL.

The memory cell array is covered with an interlayer insulating film 9, and a bit line (BL) 11 is formed thereon. A common source line (CELSRC) 10s for commonly connecting the sources of the NAND cell units is embedded in the interlayer insulating film 9, and for example, a bit line contact plug 10d is embedded with the same conductive material. The bit line 11 is connected to the drain region (n ⁺ type diffusion layer 32) through the bit line contact plug 10d.

  The silicon layer 3 is n-type, and the plurality of memory cells constituting the NAND cell unit use the n-type silicon layer 3 as a channel body and source / drain as it is without forming a source / drain diffusion layer. Thus, adjacent cells are formed to share the source / drain. Therefore, the memory cell is formed as a depletion (D) type n-channel transistor in a built-in state.

In this embodiment, the select gate transistor regions at both ends of the NAND cell unit are positioned on the opening 4 that becomes the nucleus of crystal growth of the silicon layer 3. In this region, a p-type layer 31 is formed in order to make the selection gate transistors SG1 and SG2 an enhancement (E) type in which the gates are cut off at 0V. Further, immediately below the bit line contact plug 10d and the source line 10s (that is, the drain region of the selection gate transistor SG1 and the source region of the selection gate transistor SG2), the n ⁺ type diffusion layer 32 is provided in order to improve the contact therebetween. Is forming.

  Next, a manufacturing process of the flash memory according to the embodiment will be described with reference to FIGS. 6 to 9 show the manufacturing process in the I-I 'cross section of FIG. As shown in FIG. 6, a silicon oxide film 2 is formed on a silicon substrate 1, and an opening 4 is opened at the selection gate transistor formation position. At this stage, the openings 4 are formed in a stripe shape continuous in a direction perpendicular to the paper surface of FIG.

  Subsequently, as shown in FIG. 7, an n-type silicon layer 3 is formed on the oxide film 2. Specifically, after depositing a polycrystalline silicon layer or an amorphous silicon layer, crystallization annealing is performed, and solid phase growth is performed using the substrate crystal exposed in the opening 4 as a seed, so that a high-quality crystalline silicon layer 3 is formed. Get. After the crystallization annealing, a planarization process may be performed to smooth the surface of the crystalline silicon layer 3.

  Next, as shown in FIG. 8, a p-type layer 31 is formed by performing ion implantation at a position where a selection gate transistor is formed later, that is, at a position of the opening 4.

  Next, as shown in FIG. 9, after forming a tunnel oxide film 5 on the silicon layer 3, a first-layer polycrystalline silicon film 60 for forming a floating gate is deposited. 10 and 11 show the structures taken along the lines II-II ′ and III-III ′ of FIG. 1 in this step, respectively.

  Next, as shown in FIGS. 12 and 13 (cross sections corresponding to FIGS. 10 and 11 respectively), the depth reaching the oxide film 2 from the polycrystalline silicon film 60 (actually, the p-type well of the substrate 1). An element isolation trench 13 having a depth of 1 c) is formed by RIE, and the element isolation insulating film 12 is embedded in the element isolation trench 13.

  In this element isolation step, the n-type silicon layer 3 is patterned as a plurality of stripe-shaped element formation regions 14 that are continuous in the bit line direction and separated from each other in the word line direction. At the same time, the polycrystalline silicon film 60 serving as a floating gate is patterned as the same stripe-shaped polycrystalline silicon film 60 a as the element formation region 14.

  Subsequently, as shown in FIGS. 14 to 16, after the intergate insulating film 7 is formed, a second-layer polycrystalline silicon film 80 for forming a control gate is deposited. At this time, as shown in FIGS. 14 and 15, an opening 81 is opened in the inter-gate insulating film 7 on the cell region on the selection gate line, and the second-layer polycrystalline silicon film 80 is replaced with the first-layer polycrystalline silicon film 60a. Contact with.

Then, as shown in FIG. 17, the second layer polycrystalline silicon film 80 to the first layer polycrystalline silicon film 60a are etched by RIE to form word lines 8 and select gate lines 8d and 8s. As a result, the first-layer polycrystalline silicon film 60 remains only in each memory cell region and transistor region as the floating gate 6 and the select gate portions 6d and 6s. Thereafter, ions are implanted into contact positions of the bit line and the source line to form the n ⁺ -type layer 32.

  After that, as shown in FIGS. 2 to 4, a first interlayer insulating film 9a is deposited, a contact hole is opened in this, and a common source line 10s and a bit line contact 10d are embedded. Next, a second interlayer insulating film 9b is deposited, a bit line contact hole is opened, and a bit line 11 is formed.

  As is apparent from the above description of the manufacturing process, if the opening 4 formed in the oxide film 2 is disposed immediately below the selection gate lines SGD, SGS, the later p-type diffusion layer 31, the word line WL, and the selection gate line are arranged. In the formation process of SGD and SGS, it is necessary to align with the opening 4. This is because they are not self-aligned.

  The alignment mark forming process for that purpose will be described with reference to FIGS. FIG. 18 shows a process of forming the opening 4 in the oxide film 2 using the mask material 101 in the cell array region. At the same time in this step, a mark opening 4a is formed in the oxide film 2 in an appropriate mark region around the wafer.

  Thereafter, as shown in FIG. 19, the memory cell array region is covered with a resist 102, and the silicon substrate is etched through the opening 4a in the mark region to form the mark recess 4b. Thereafter, as shown in FIG. 20, the resist 102 and the mask material 101 are removed.

  Thus, by forming the mark recesses 4b around the well, mask alignment in the subsequent process becomes possible.

  Next, the operation of the flash memory of this embodiment will be described. As described above, the memory cell is a depletion (D) type (erased state) in a built-in state, and in a narrow sense write, an electron is injected into the floating gate and the threshold is positive (E) type state. Say to be. For example, data “0” is set when the threshold is positive.

  Data erasure refers to releasing electrons from the floating gate to bring the threshold value into a negative state (D type state), and this erase state is referred to as data “1”. Thereby, binary storage is performed. Multi-value storage can be performed by further controlling the write threshold state to a plurality of threshold distributions. The operation of binary storage will be described below.

  FIG. 21 shows a bias relationship at the time of erasing data. In the equivalent circuit shown in FIG. 5, data erasure is performed using one block BLK defined as a set of NAND cell units sharing the word lines WL0 to WL15 as an erasure unit.

  As shown in FIG. 21, the selection gate lines SGD and SGS, the bit line BL and the common source line CELSRC of the selected block are set in a floating state, all the word lines WL0 to WL15 of the selected block are set to 0 V, and positive erasing is performed on the well terminal CPWEL. A voltage Vera is applied. The well terminal CPWEL is a terminal commonly connected to the p-type well 1c and the n-type well 1b. The erase voltage Vera is a voltage boosted to a value of 15V to 24V higher than the power supply voltage Vcc by a normal booster circuit.

  Under this bias condition, the PN junction between the n-type silicon layer 3 in the cell array region and the p-type layer 31 immediately below the select gate line is forward-biased. Therefore, the n-type silicon layer 3 is charged to the erase voltage Vera from the p-type well 1 c through the p-type layer 31 on the opening 4. As a result, in the memory cell of the selected block, a large electric field is applied between the floating gate and the channel, electrons in the floating gate are emitted by the FN tunnel current, and the threshold value is in an erased state (data “1” state).

  At this time, the n-type silicon layer 3 is charged to Vera even in the non-selected block. However, in the non-selected block, the floating gate potential is raised by capacitive coupling by keeping the word line floating, and erasing is not performed.

  FIG. 22 shows a bias relationship at the time of data writing. Data writing is performed on a page-by-page basis with a set of memory cells arranged along a word line as one page or two pages. FIG. 22 shows a case where the word line WL1 is selected.

  The well terminal CPWEL is set to 0 V (or a small negative voltage), the write voltage Vpgm boosted to 15 to 20 V is applied to the selected word line WL1, and the positive intermediate voltage Vm lower than the write voltage Vpgm is applied to the remaining unselected word lines. Then, Vdd is applied to the selection gate line SGD on the bit line side, and 0 V is applied to the source line side selection gate line SGS. The source line CELSRC gives 0V or an appropriate positive voltage.

  Prior to the application of the above write bias voltage, 0 V (“0” write) and Vdd (“1” write) are applied to the bit line BL in accordance with the write data. As a result, 0V is applied to the NAND cell channel to which “0” is written. In the case of writing “1”, the selection gate transistor SG1 is turned off when the source (the side opposite to the bit line) is charged to Vdd−Vth (Vth is the threshold value of the selection gate transistor), and the NAND cell channel is floating. become.

  In this state, when the write voltage Vpgm and the intermediate voltage Vm are applied, electrons are injected into the floating gate by the FN tunnel current in the “0” write selection cell. That is, data with a positive threshold value “0” is written. In the “1” write cell, the potential of the floating channel rises due to capacitive coupling, and electron injection does not occur. That is, the “1” data state is maintained.

  FIG. 23 shows a bias relationship at the time of data reading. Data reading is also performed in units of pages. FIG. 23 shows a case where the word line WL1 is selected.

  The common source line CELSRC is set to 0 V, and the bit line BL is charged in advance to a predetermined positive voltage VBL and kept in a floating state. The well terminal CPWEL is set to 0 V (or a small negative voltage), a read voltage Vr (for example, 0 V) is applied to the selected word line WL1, and a read path that can turn on the cells to the remaining unselected word lines regardless of cell data. The read pass voltage Vread is also applied to the selection gate lines SGD and SGS.

  Thus, the selected cell is not turned on if the data is “0”, and the bit line BL is not discharged. If the selected cell is “1”, it is turned on and the bit line BL is discharged. Therefore, after the bit line discharge operation for a certain time, data can be read by detecting the voltage of the bit line BL with the sense amplifier.

  According to this embodiment, a partial SOI substrate is used instead of an SOI substrate having a silicon layer completely separated from the substrate. Although this partial SOI substrate requires a crystallization annealing step, it can be obtained at a lower cost than a normal SOI substrate. By selecting the thickness of the silicon layer, element isolation is easy, and a fine cell structure that cannot be obtained by a normal bulk type can be realized.

  Further, when a NAND flash memory is manufactured using a normal SOI substrate, special measures are required to apply an erase voltage to the channel body of the NAND cell unit. On the other hand, in the case of this embodiment, the silicon layer serving as the channel body is in contact with the silicon substrate through the opening opened in the oxide film. Therefore, an erase voltage for batch erasure can be applied to the channel body of the NAND cell unit via the substrate, and reliable erasure becomes possible.

  24 to 27 are cross-sectional views corresponding to FIG. 2 in other embodiments. In FIG. 2, an opening 4 is opened in the oxide film 2 under the selection gate lines (SGD, SGS) 8d, 8s on the bit line side and the source line side. On the other hand, FIG. 24 shows an example in which the opening 4 is opened only directly below the source line side select gate line (SGS) 8s. FIG. 25 shows an example in which the opening 4 is opened only immediately below the bit line side select gate line (SGD) 8d.

In FIG. 26, the opening 4 is opened in the oxide film 2 in the region of the n ⁺ type diffusion layer 32 of the bit line (BL) contact and the source line (CELSRC) contact. In this case, when the erase voltage Vera is applied to the p-type layer 1c of the substrate, the PN junction between the n ⁺ -type diffusion layer 32 and the p-type diffusion layer 31 becomes a reverse bias. However, it is possible to give a necessary positive voltage to the channel body of the NAND cell unit by setting the value of the erase voltage Vera and the impurity concentration of each diffusion layer.

Specifically, if the PN junction between the n ⁺ -type diffusion layer 32 and the p-type diffusion layer 31 breaks down and impact ionization occurs in the p-type diffusion layer 31, the generated electrons and holes Of these, holes flow to the n-type channel body of the NAND cell unit and are accumulated therein. As a result, the channel body can be boosted to a positive voltage necessary for the erase operation.

In FIG. 26, the opening 4 is formed in the oxide film 2 in the region of the n ⁺ type diffusion layer 32 of both the bit line (BL) contact and the source line (CELSRC) contact, but only one of them may be formed.

  FIG. 27 shows an example in which an opening 4 is formed in the oxide film 2 immediately below an appropriate memory cell in the NAND cell unit. Also in this case, since the channel body of the NAND cell unit is charged by the erase voltage Vera applied from the p-type layer 1c, the same erase operation as in the previous embodiment is possible.

FIG. 28 shows an example in which the opening 4 is opened so as to straddle the n ⁺ -type diffusion layer 32 and the p-type diffusion layer 31 in the contact portion. Although not shown in the drawing, the opening 4 may be opened so as to straddle the p-type diffusion layer 31 and the n-type silicon layer 3.

Next, device simulation data will be described. The device conditions are as follows: the line L / space S of the stripe-shaped element formation region is L / S = 80 nm / 80 nm, the word line width is W = 80 nm, and the selection gate line width is LSG = 100 nm. The impurity concentration of the p-type well is PSUB = 1E18 cm ⁻³ , and the impurity concentration of the p-type layer under the selection gate line is PSGC = 1E16 cm ⁻³ .

  The silicon layer thickness of the partial SOI substrate was selected in the range of TSOI = 10 to 80 nm, and the thickness of the isolation oxide film was selected in the range of TBOX = 20 to 80 nm. The tunnel oxide film thickness is TOX = 8 nm. There are five memory cells in the NAND cell unit.

  First, a simulation of an erasing operation in which 0 V is applied to a word line and 20 V is applied to a p-type well in a structure in which an opening is provided under a selection gate line (SG) and a structure in which an opening is provided under a bit line contact (CB). The results will be explained.

FIGS. 29A and 29B show simulation conditions for each structure. Here, the source voltage and the drain voltage are voltages of the n ⁺ type layer 32 with which the source line CELSRC and the bit line BL are in contact, respectively. In the actual erase operation of the device, the source line CELSRC and the bit line BL are floating, so that the n ⁺ -type layer 32 becomes a voltage determined by the voltage applied to the p-type well 1c. The simulation is performed under the condition of applying the source and drain voltages as shown in FIG.

In the case of a structure having an opening under the selection gate line SG, the source and drain voltages are set to the p-type well voltage because the p-type diffusion layer 31 and the n ⁺ -type diffusion layer 32 under the selection gate line are forward-biased. Same 20V. In the case of a structure having an opening under the bit line contact CB, since the p-type diffusion layer 31 is sandwiched between the n ⁺ -type layer 32 and the n-type silicon layer 3, the source and drain voltages are 19V is selected as the voltage obtained by reducing the p-type well voltage 20V by the built-in voltage of the PN junction.

  The applied voltage from time 0 to 10 μsec is changed linearly with respect to time. That is, the voltage of the p-type well changes at 2 V / μsec from 0 to 10 μsec and finally rises to 20 V. There is no change in applied voltage between 10 μsec and 100 μsec.

  FIG. 30 and FIG. 31 show the time variation of the in-device potential distribution for an example in which openings are opened under the selection gate line SG and the contact CB for the above erase voltage application. The potential indicated by the contour line is actually the result of obtaining the vacuum level (that is, the case of the p-type layer with the externally applied voltage of 0 V is set to about −5 eV in consideration of the work function). That is, the time change of the potential of the p-type well and the channel body portion (n-type silicon layer) is written in with respect to 0V.

  That is, the channel body is about 4 V at 2 μsec, about 12 V at 6 μsec, and 20 V and 19 V at 10 μsec, respectively. In FIG. 30, the level difference is shown between the channel body and the p-type well because the vacuum level is displayed as described above, and the actual potential is 10 μsec. 20V. On the contrary, in the case of FIG. 31, the channel body and the p-type well are displayed so that there is no level difference. However, as an actual potential, when 20V is applied to the p-type well, the channel body Is 19V, the same as the source and drain.

  From the above simulation results, it is confirmed that a certain erasing electric field is applied between the channel body and the floating gate, both in the case of having an opening under the selection gate and in the case of having an opening under the bit line contact, and erasing is possible. .

  FIG. 32 shows the result of evaluating the read characteristics of the NAND cell unit for an example in which an opening is opened under the select gate line SG. Here, for a combination of (3 × 3) with TSOI = 10, 40, 80 nm and TBOX = 20, 40, 60 nm, the read current (bit line current) ID of the selected cell and the impurity concentration NSOI of the n-type silicon layer The p-type well voltage VSUB is shown as a parameter.

The drain voltage is VD = 0.7V, the floating gate voltage of the non-selected cell is 2.5V, and the floating gate voltage of the selected cell is 0V. The impurity concentration of the p-type well is PSUB = 1E18 cm ⁻³ .

  FIG. 33 further shows the read cell current ID (−0.5 V) when the floating gate voltage of the selected cell is switched to VFG = −0.5, −0.2, 0.0, 0.2, 0.5 V. , ID (−0.2 V), ID (0.0 V), ID (0.2 V), ID (0.5 V) are obtained, and the on / off current ratio of the read selected cell ID (0.2 V) / ID (−0) .2 V) and ID (0.5 V) / ID (−0.5 V). The impurity concentration NSOI of the n-type silicon layer is adjusted so that the drain current ID becomes 0.1 μA when the floating gate of the selected cell is 0V.

  From the results of FIGS. 32 and 33, it can be seen that reading is possible based on the on / off current ratio of the cell, and that the optimum conditions for the reading characteristics can be selected for each part size, each part impurity concentration, etc. of the device.

  34 and 35 show simulation results under substantially the same conditions for an example in which an opening is formed immediately below the bit line contact CB. In FIG. 34, for a combination of (3 × 3) with TSOI = 10, 40, and 80 nm and TBOX = 20, 60, and 80 nm, the relationship between the drain current (bit line current) ID and the impurity concentration NSOI of the n-type silicon layer. Is shown using the p-type well voltage VSUB as a parameter. Other conditions are the same as in FIG.

  FIG. 35 shows the on / off current ratios ID (0.2 V) / ID (−0.2 V) and ID (0.5 V) / ID (−0.5 V) of the read selected cell under substantially the same conditions as in FIG. The obtained results are shown.

  FIG. 36 shows that the drain current (ie, bit line current) ITH is 0.1 μA when the threshold voltage VTH = −0.5 V, 0 V, and 0.5 V when the opening is opened under the selection gate line SG. This is a result of simulation calculation of the device conditions. The value of ITH is slightly deviated from 0.1 μA, which indicates an error resulting from the condition search. It is presumed that substantially the same result can be obtained even when the opening is opened under the bit line contact CB.

  “SF” is the S coefficient in each threshold state (unit: mV / dec.), “ION” is the drain current (unit: A) when the floating gate voltage is equivalent to the threshold voltage +2.5 V “TSOI / L” is a value obtained by normalizing the SOI film thickness by the gate length L, and “TBOX / L” is a value obtained by normalizing the BOX film thickness by the gate length L. Other items are the same as those in FIGS. 33 and 35.

  37 to 41 show the calculation results of FIG. 36 on the xy coordinates of the x-axis TSOI / L and the y-axis TBOX / L.

  FIG. 37 shows the case where L = S = W = 20 nm and VTH = −0.5V. Symbols such as circles (◯), triangles (Δ), etc. are the calculation results of FIG. 36, and it is indicated that the operation is possible if the combination of TBOX and TSOI indicated by these symbols.

  FIG. 37 shows a curve y = 8.7 / x, and the calculation result shows that there was a combination of TBOX and TSOI operable below this curve.

  FIG. 38 shows the case where L = S = W = 20 nm and VTH = 0V, and the curve indicating the operable range is y = 2.55 / x.

  FIG. 39 shows the case where L = S = W = 80 nm and VTH = −0.5 V, and the curve indicating the operable range is y = 8.0 / x.

  FIG. 40 shows the case where L = S = W = 80 nm and VTH = 0 V, and the curve indicating the operable range is y = 0.74 / x.

  FIG. 41 shows the case where L = S = W = 80 nm and VTH = 0.5 V, and the curve indicating the operable range is y = 0.125 / x.

  The results of FIGS. 37-41 can be explained as follows. The negative substrate bias VSUB functions to suppress the drain current via the BOX film and the SOI film. When the BOX film thickness is increased, capacitive coupling of VSUB to the SOI film is reduced, and the drain current suppressing effect is reduced. Even if the BOX film is thin, if the SOI film thickness is increased, the drain current suppressing effect of VSUB is also lowered.

  The outside of the approximated curve of the hyperbola shown in FIG. 37-41 shows the expected drain current in the appropriate VSUB range (0V to -2V) as a result of the BOX film thickness becoming too large or the SOI film thickness becoming too large. Cannot be obtained, and therefore the desired threshold state cannot be obtained.

  As described above, it has become clear from the simulation results that reading is possible both when the opening is opened under the selection gate line SG and when the opening is opened under the bit line contact CB. Comparing the read characteristics of the two, it can be said that when the opening is opened under the selection gate line SG, the dependency on the well voltage VSUB is larger, and therefore the degree of freedom for trimming and the like is greater.

  The present invention can be implemented with various modifications as listed below.

  (a) The p-type and n-type in the above embodiments can be reversed, and the memory cell can be a p-type transistor.

  (b) The opening 4 below the selection gate does not necessarily need to coincide with the selection gate as shown in FIG. As shown in FIG. 42, the opening 4 may be opened in a state shifted from the selection gate.

  (C) In the embodiment, the silicon layer 3 is an n-type and the memory cell is a D-type transistor. On the other hand, as shown in FIG. 43, the silicon layer 3 can be p-type, the channel region of the memory cell can be p-type, and the source and drain regions can be n-type layer 3a. In this case, at the time of erasing, a hole current can be supplied from the opening 4 to the entire NAND cell channel through the p-type layer 31 below the selection gate by the erasing voltage Vera. Therefore, collective erasure is possible as in the above embodiment.

  (D) As a method for obtaining the crystalline silicon layer 3, vapor phase growth can be combined. As shown in FIG. 44, the epitaxial layer 40 is first formed in the opening part by the vapor phase growth in the board | substrate 1 with which the opening 4 was opened. Thereafter, similarly to the above embodiment, amorphous silicon or polycrystalline silicon is deposited, and crystallization annealing is performed.

  Thereby, crystallization is performed using the vapor phase epitaxial layer 40 as a seed, and a high-quality crystalline silicon layer 3 can be obtained.

(E) As a method for manufacturing a partial SOI substrate, a SIMOX (Separation by Implanted Oxygen) method can be used as follows. As shown in FIG. 45, a thermal oxide film 201 is formed on the silicon substrate 1. Next, as shown in FIG. 46, a resist 202 is patterned on the thermal oxide film 201 by ordinary lithography. In this state, for example, oxygen ions ( ¹⁶ O ⁺ ) are implanted at a dose of 4 × 10 ¹⁷ cm ⁻² at 140 keV to selectively form the oxygen ion implanted layer 203. Thereafter, for example, annealing is performed at 1300 ° C. for 6 hours in an N ₂ atmosphere to form the oxide film 2 as shown in FIG. Thereafter, As and B are ion-implanted under appropriate conditions to form an n-type silicon layer 3 on the oxide film 2 as shown in FIG. 48, and the same partial SOI substrate as in the previous embodiment. Is obtained.

  (F) Read conditions different from those described with reference to FIG. 23 can be used. For example, as shown in FIG. 49, the pass voltage Vread2 applied to the word lines on both sides of the selected cell (selected word line, WL1 in the figure) is set lower than the pass voltage Vread of the other word lines. For example, Vread = 5V and Vread2 = 4V can be set.

1 is a plan view of a memory cell array of a NAND flash memory according to an embodiment of the present invention. It is I-I 'sectional drawing of FIG. It is II-II 'sectional drawing of FIG. FIG. 3 is a cross-sectional view taken along the line III-III ′ of FIG. 3 is an equivalent circuit of the memory cell array. It is I-I 'sectional drawing which shows the pre-processing process for the partial SOI substrate formation in the embodiment. It is I-I 'sectional drawing which shows the manufacturing process of the partial SOI substrate. It is I-I 'sectional drawing which shows the p type diffused layer formation process in the selection gate transistor area | region. It is I-I 'sectional drawing which shows a 1st gate material film formation process. It is II-II 'sectional drawing which shows the 1st gate material film formation process. It is III-III 'sectional drawing which shows the 1st gate material film formation process. It is II-II sectional drawing which shows an element isolation process. It is III-III 'sectional drawing which shows the same element separation process. It is I-I 'sectional drawing which shows a 2nd gate material film formation process. It is II-II 'sectional drawing which shows the 2nd gate material film formation process. It is III-III 'sectional drawing which shows the 2nd gate material film formation process. It is I-I 'sectional drawing which shows a word line and control gate line patterning process. It is a figure which shows the oxide film etching process for alignment mark formation. It is a figure which shows the silicon etching process of the alignment mark. It is a figure which shows the completion state of the alignment mark. It is a figure which shows the bias relationship at the time of erasure | elimination of the flash memory of embodiment. It is a figure which shows the bias relationship at the time of the write-in of the flash memory. It is a figure which shows the bias relationship at the time of reading of the flash memory. It is I-I 'sectional drawing of the example which opened the oxide film opening only under the source line side selection gate line. It is I-I 'sectional drawing of the example which opened the oxide film opening only under the bit-line side selection gate line. It is I-I 'sectional drawing of the example which opened the oxide film opening under the contact of a bit line and a source line. It is I-I 'sectional drawing of the example which opened the oxide film opening under the memory cell. FIG. 10 is a cross-sectional view taken along the line I-I ′ of an example in which an oxide film opening is opened from under a bit line and source line contact to under a selection gate line. It is a figure which shows the simulation conditions of erase operation. It is a figure which shows the potential change at the time of erasing voltage application in the cell array structure which opened the oxide film opening under the selection gate line. It is a figure which shows the potential change at the time of the erase voltage application in the cell array structure which opened the oxide film opening under the bit line contact. It is a figure which shows the relationship between a read cell current and a silicon layer impurity concentration by the relationship between the combination of a silicon thickness and an oxide film thickness about the cell array structure which opened the oxide film opening under the selection gate line. It is a figure which similarly shows the on-off current ratio of a read cell. It is a figure which shows the relationship between a read cell current and a silicon layer impurity concentration by the relationship between the combination of silicon thickness and an oxide film thickness about the cell array structure which opened the oxide film opening under the bit line contact. It is a figure which similarly shows the on-off current ratio of a read cell. It is a figure which shows the result of having calculated the device conditions which drain current ITH becomes 1 microampere. FIG. 37 is a diagram showing an operable range on the two-axis coordinates of TBOX / L and TSOI / L when L = S = W = 20 nm and VTH = −0.5 V based on the results of FIG. Similarly, it is a diagram showing an operable range when L = S = W = 20 nm and VTH = 0V. Similarly, it is a diagram showing an operable range when L = S = W = 80 nm and VTH = −0.5V. Similarly, it is a diagram showing an operable range when L = S = W = 80 nm and VTH = 0V. Similarly, it is a diagram showing an operable range when L = S = W = 80 nm and VTH = 0.5V. FIG. 3 is a cross-sectional view corresponding to FIG. 2 of a memory cell array according to another embodiment. FIG. 3 is a cross-sectional view corresponding to FIG. 2 of a memory cell array according to another embodiment. It is sectional drawing for demonstrating the manufacturing method of the partial SOI substrate by other embodiment. It is sectional drawing for demonstrating the manufacturing method of the partial SOI substrate by a SIMOX method. It is sectional drawing for demonstrating the manufacturing method of the partial SOI substrate by the SIMOX method similarly. It is sectional drawing for demonstrating the manufacturing method of the partial SOI substrate by the SIMOX method similarly. It is sectional drawing for demonstrating the manufacturing method of the partial SOI substrate by the SIMOX method similarly. It is a figure which shows the read-out conditions of the flash memory of other embodiment corresponding to FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Single crystal silicon substrate, 1a ... p-type silicon substrate, 1b ... n-type well, 1c ... p-type well, 2 ... oxide film, 3 ... n-type silicon layer, 4 ... opening, 5 ... tunnel oxide film, 6 ... Floating gate, 7... Intergate insulating film, 8... Control gate (word line), 6 d, 8 d, 6 s and 8 s... Selection gate line, 9. isolation insulating film, 13 ... isolation trench, 14 ... device forming region, 31 ... p-type diffusion layer, 32 ... ^{n +} -type diffusion layer.

Claims (7)

A semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate through an insulating film and in contact with the semiconductor substrate through an opening formed in the insulating film;
A plurality of series-connected electrically rewritable nonvolatile memory cells formed in the semiconductor layer, and a NAND cell unit including first and second selection gate transistors disposed at both ends thereof. A semiconductor memory device. The semiconductor layer is an n-type silicon layer;
The plurality of memory cells constituting the NAND cell unit are configured as n-channel transistors in which the n-type silicon layer is a channel body and a source / drain, and a charge storage layer and a control gate are stacked on the channel body.
2. The semiconductor memory device according to claim 1, wherein each of the first and second select gate transistors is configured as an n-channel transistor having a p-type diffusion layer formed in a channel body region thereof. 2. The semiconductor memory device according to claim 1, wherein the opening of the insulating film is formed below at least one of the first and second select gate transistors. A bit line and a source line respectively contacting the drain region of the first select gate transistor and the source region of the second select gate transistor;
2. The semiconductor memory device according to claim 1, wherein the opening of the insulating film is formed below at least one of a drain region of the first select gate transistor and a source region of the second select gate transistor. . 2. The semiconductor memory device according to claim 1, wherein the opening of the insulating film is formed under at least one of the plurality of memory cells. The semiconductor layer is partitioned into a plurality of stripe-shaped element formation regions by an element isolation insulating film embedded at a depth reaching the insulating film, and a corresponding memory cell of a NAND cell unit formed in each element formation region. The control gate and the gates of the first and second selection gate transistors are formed to be continuous across the plurality of element formation regions to be word lines and first and second selection gate lines, respectively. The semiconductor memory device according to claim 1. Forming an insulating film on the single crystal semiconductor substrate;
Forming an opening in the insulating film;
Depositing an amorphous or polycrystalline semiconductor layer in contact with the semiconductor substrate through the opening on the insulating film in which the opening is formed;
Performing a crystallization annealing process on the semiconductor layer;
Forming a NAND cell unit comprising a plurality of series-connected electrically rewritable non-volatile memory cells and select gate transistors disposed at both ends thereof in the semiconductor layer. Device manufacturing method.

Images