JP2011192898A - Semiconductor memory device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an influence of impurities in a channel region of a select transistor on a memory cell transistor by setting a threshold voltage of the select transistor to a predetermined value. <P>SOLUTION: A semiconductor memory device includes memory cell transistors MC0 to MC15, and select transistors ST1 and ST2, wherein dummy cell transistors DC0 and DC1 which are not used as memory elements are provided between the select transistors and memory cell transistors. Gate electrodes 13 of the select transistors have a first conductive layer and a second conductive layer, which are electrically connected by connection parts 16. Impurity concentrations of channel regions of the select transistors are higher than those of channel regions of the memory cell transistors. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, in particular, a nonvolatile semiconductor memory device such as a NAND flash memory, and a manufacturing method thereof.

  In a NAND flash memory, a memory cell transistor having a floating gate (FG) for accumulating charges and a control gate (CG) stacked on the floating gate via an inter-gate dielectric (IPD). Are used as memory elements. A plurality of memory cell transistors are connected in series to constitute a NAND cell unit. One end of the NAND cell unit is connected to the bit line via the selection transistor, and the other end is connected to the source line via the selection transistor.

  In the conventional manufacturing method, after forming the gate electrodes of the memory cell transistor and the selection transistor, if necessary, ion implantation is performed through a protective film made of, for example, a silicon oxide film, so that channel regions of the memory cell transistor and the selection transistor are obtained. And source / drain regions are formed. Next, in order to ensure the current interruption characteristics of the selection transistor, impurities are introduced into the semiconductor substrate located under the gate of the selection transistor by oblique ion implantation (see, for example, Patent Document 1). Thus, channel control for adjusting the threshold voltage of the selection transistor is performed.

  However, with the progress of miniaturization of semiconductor processes, it has become difficult to introduce a sufficient amount of impurities into the silicon substrate under the gate of the select transistor by the above method. Therefore, there is a problem that a predetermined threshold voltage cannot be obtained. Further, in order to avoid this problem, when the amount of ions to be implanted is increased, ions are also implanted into the source / drain regions, resulting in a change in the characteristics of the memory cell transistor.

JP 2007-165543 A

  The present invention provides a semiconductor memory device capable of setting the threshold voltage of a select transistor to a predetermined value and reducing the influence of impurities in the channel region of the select transistor on the memory cell transistor as much as possible, and a method for manufacturing the same. To do.

According to one aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell unit having a plurality of memory cell transistors connected in series; and a selection transistor connected in series to the memory cell unit,
The memory cell transistor includes a first gate insulating film formed on a semiconductor substrate, a charge storage layer provided on the first gate insulating film, and an inter-gate insulating film provided on the charge storage layer And a first gate electrode having a control gate provided on the inter-gate insulating film, and a first conductivity type impurity formed in the semiconductor substrate under the first gate electrode. A first channel region including a concentration; and a first source / drain region of a second conductivity type formed in the semiconductor substrate so as to sandwich the first channel region,
The selection transistor includes a second gate insulating film containing the first conductivity type impurity in at least a part of the region, a first conductive layer provided on the second gate insulating film, and the first transistor A connection portion that is provided on the conductive layer and is located immediately above at least a part of the region containing the impurity of the first conductivity type in the second gate insulating film, and the connection portion A second gate electrode having a second conductive layer electrically connected to the conductive layer; and the semiconductor substrate under the second gate electrode, wherein the impurity of the first conductivity type is formed. A second channel region having a second concentration higher than the first concentration and a second channel region of the second conductivity type formed in the semiconductor substrate so as to sandwich the second channel region. A source / drain region,
A semiconductor memory device is provided in which the memory cell transistor adjacent to the selection transistor is a dummy cell transistor controlled as a dummy cell.

According to another aspect of the present invention, a first conductivity type impurity is implanted into a surface of a semiconductor substrate to a first concentration, a gate insulating film is formed on the surface of the semiconductor substrate, and a first insulating film is formed on the gate insulating film. 1 is formed, an element isolation region is formed in the semiconductor substrate and the gate insulating film, an inter-gate insulating film is formed on the element isolation region and the first conductive layer, and the gate A mask material having an opening exposing at least a part of the surface of the inter-layer insulating film is formed on the inter-gate insulating film, and the first conductivity type is formed in the semiconductor substrate through the opening of the mask material. Are implanted at a second concentration higher than the first concentration, the inter-gate insulating film exposed in the opening of the mask material is removed, and a second conductive layer is formed on the inter-gate insulating film. Through the region from which the inter-gate insulating film has been removed. Forming a stacked gate electrode by patterning the first conductive layer, the inter-gate insulating film, and the second conductive layer. Then, a method for manufacturing a semiconductor memory device is provided in which a source / drain region is formed by implanting an impurity of a second conductivity type into the semiconductor substrate around the stacked gate electrode.

  According to the present invention, the threshold voltage of the selection transistor is set to a predetermined value, and the influence of impurities in the channel region of the selection transistor on the memory cell transistor can be reduced as much as possible.

1 is a block diagram of a NAND flash memory according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a part of the memory cell array according to the embodiment of the present invention. 3 is a plan view of a part of the memory cell array according to the embodiment of the present invention. FIG. FIG. 10 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 5 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 4. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 6 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 5. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 7 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 6. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 8 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 7. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 9 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 8. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 10 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 9. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 11 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 10. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 12 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 11. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 13 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 12. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 14 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 13. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 15 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 14. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. FIG. 16 is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention continued from FIG. 15. (A) is sectional drawing which follows the X1-X2 line of FIG. 3, (b) is sectional drawing which follows the X3-X4 line of FIG. It is a figure which shows the bias conditions in each operation mode of memory. It is a figure which shows distribution of the threshold voltage of the memory cell transistor corresponding to data "0" and data "1", respectively.

  Hereinafter, a semiconductor memory device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings. In each figure, the same numerals are given to the component which has an equivalent function.

  FIG. 1 is a block diagram of a NAND flash memory according to the present embodiment. The memory cell array 101 has a configuration in which a plurality of NAND cell units in which electrically rewritable nonvolatile memory cells are connected in series are arranged.

  The sense amplifier / data latch 102 includes a sense amplifier that senses data on the bit line BL of the memory cell array 101 and a data latch that holds write data.

  The column decoder 103 selects the bit line BL of the memory cell array 101. The row decoder / word line driver 105 selects and drives a word line.

  A row address and a column address are supplied to the column decoder 103 and the row decoder / word line driver 105 via the I / O buffer 104 and the address register 106, respectively. Data transmission / reception is performed between the bit line BL and the external I / O terminal via the I / O buffer 104.

  The control circuit 107 performs sequence control for performing memory operations such as data writing, reading, and erasing.

  Under the control of the control circuit 107, the high voltage generation circuit 108 generates a high voltage necessary for writing and erasing data according to the operation mode, and supplies the memory cell array 101 and the row decoder / word line driver 105 with the high voltage. Supply.

  FIG. 2 is a circuit diagram showing a part of the memory cell array 101. The NAND cell unit NCU has 16 memory cell transistors (MC0 to MC15) and two dummy cell transistors (DC0, DC1). The memory cell transistors (MC0 to MC15) and the dummy cell transistors (DC0, DC1) have a floating gate and a control gate. In the present embodiment, 16 memory cell transistors constitute a NAND cell unit. However, the present embodiment is not limited to this number.

  As shown in FIG. 2, a select transistor ST1 is provided between one end of the NAND cell unit NCU and the bit line BL, and a select transistor ST2 is provided between the other end and the source line SL. As shown in FIG. 2, the dummy cell transistor DC0 is provided between the memory cell transistor MC0 and the selection transistor ST1, and the dummy cell transistor DC1 is provided between the memory cell transistor MC15 and the selection transistor ST2. These dummy cell transistors DC0 and DC1 are not used as elements for storing data.

  As shown in FIG. 2, the gate electrodes of the memory cell transistors MC0 to MC15 are connected to word lines WL0 to WL15, respectively. Each word line WL is shared with the gate electrodes of a plurality of memory cell transistors arranged in that direction. The gate electrodes of the select transistors ST1, ST2 are connected to select gate lines SGD, SGS, respectively. The gate electrodes of the dummy cell transistors DC0 and DC1 are connected to word lines (dummy word lines) DWL0 and DWL1 of the dummy cell transistors, respectively.

  Next, the planar structure of the semiconductor memory device according to this embodiment will be described with reference to FIG. FIG. 3 is a plan view of a part of the memory cell array 101 described above.

  As shown in FIG. 3, a plurality of active regions 21, 21,... Are provided in parallel in a stripe shape. Source / drain regions are formed in the active region 21. Each memory cell transistor MC0, MC1,..., MC15 shares a source / drain region between adjacent memory cell transistors.

  An element isolation region 22 is provided between the active regions 21 and 21. Word lines WL0, WL1,..., WL15 (gate electrodes 7, 7,...) Are provided in parallel to the stripe shape so as to be orthogonal to the stripe-shaped active region 21.

  Then, a pair of dummy word lines DWL0, DWL1 (gate electrodes 7 ′, 7 ′) are provided so as to sandwich the word lines WL0, WL1,..., WL15 (gate electrodes 7, 7,...). Yes. Further, word lines SGD and SGS (gate electrodes 13 and 13) of a pair of selection transistors ST1 and ST2 are provided so as to sandwich the dummy word lines DWL0 and DWL1.

As shown in FIG. 3, impurities are implanted into the region 20 in the semiconductor substrate. A part of this region 20 functions as a channel region of the memory cell transistor.
As shown in FIG. 3, the gate structure of the select transistors ST1 and ST2 is provided with an opening 16 (Etching Inter-poly: EI) described later as a part of the gate structure. Impurities are implanted into the silicon substrate from the openings 16, and the regions into which the impurities are implanted function as channel regions of the select transistors ST1 and ST2. Note that the impurity concentration of the channel regions of the select transistors ST1, ST2 is different from that of the memory cell transistor. As a result, the threshold voltage of the selection transistor can be made higher than that of the memory cell transistor, and the current interruption characteristic necessary for the selection transistor can be ensured.

  Next, a method for manufacturing the NAND flash memory according to the present embodiment will be described with reference to FIGS. 4A to 4B to 16A and 16B are process cross-sectional views illustrating the manufacturing process of the NAND flash memory according to the present embodiment. 4-16, (a) is sectional drawing which follows the X1-X2 line in FIG. 3, (b) is sectional drawing which follows a X3-X4 line.

(1) First, as shown in FIGS. 4A and 4B, a sacrificial silicon oxide film 30 is formed on a semiconductor substrate 1, for example, a p-type silicon substrate. The sacrificial silicon oxide film 30 is for protecting the surface of the semiconductor substrate 1 from damage caused by ion implantation. In some cases, after the sacrificial silicon oxide film 30 is formed, impurities are introduced into the semiconductor substrate 1 by ion implantation. Then, the introduced impurity is activated to form a p-type well or a double well including an n-type well and a p-type well.

(2) Next, ion implantation is performed on the surface of the semiconductor substrate 1 or, if a well is formed, on the surface of the well. Thereby, as shown in FIGS. 4A and 4B, an ion implantation layer 31 is formed. Impurities introduced by ion implantation depend on the conductivity types of the memory cell transistor and the select transistor. For example, when the conductivity of the transistor is n-type, p-type impurities such as boron (B) are introduced. This ion implantation is performed for channel control of the memory cell transistor and the selection transistor, and is called channel ion implantation. Channel ion implantation is performed simultaneously on the entire region where the memory cell transistor and select transistor are to be formed. The ion implantation layer 31 becomes the channel diffusion layers 11 and 18 of the memory cell transistor and the dummy cell transistor.

(3) Next, as shown in FIGS. 5A and 5B, after the sacrificial silicon oxide film 30 is peeled off, the gate insulating film 6 is formed on the semiconductor substrate 1. Subsequently, the floating gate electrode layer 32 is formed on the gate insulating film 6. Since the floating gate electrode layer 32 needs to be conductive, for example, polycrystalline silicon previously doped with phosphorus (P) or the like is used. Of course, impurities such as phosphorus may be ion-implanted after depositing undoped polycrystalline silicon.

(4) Next, as shown in FIGS. 5A and 5B, a mask material 33 such as a silicon nitride film (Si ₃ N ₄ ) is formed on the floating gate electrode layer 32. This mask material 33 is used to form an element isolation region.

(5) Next, a resist (not shown) is applied onto the mask material 33, and the resist is patterned according to the pattern of the element isolation region by a photolithography technique. Then, the mask material 33 is etched using the patterned resist as a mask. Then, using the patterned mask material 33 as a mask, the floating gate electrode layer 32, the gate insulating film 6, and the semiconductor substrate 1 are etched. This etching is usually performed using RIE (Reactive Ion Etching). Thereby, a groove (not shown) for an element isolation region reaching the semiconductor substrate 1 from the surface of the mask material 33 is formed.

(6) Next, the side surface and the bottom surface of the trench for the element isolation region are oxidized at a high temperature to form a silicon thermal oxide film.

(7) Next, as shown in FIG. 6B, an element isolation silicon oxide film 34 is deposited in the element isolation region trench by, for example, a CVD (Chemical Vapor Deposition) method. At this time, for example, an HDP-CVD (High Density Plasma-CVD) method is used as the CVD method.

(8) Next, as shown in FIGS. 6A and 6B, the deposited silicon oxide film 34 is flattened so that the upper surface of the mask material 33 and the upper surface of the silicon oxide film 34 coincide with each other. . This planarization step usually uses a CMP (Chemical Mechanical Polishing) method, but may be performed using an etch back method. Note that when planarization is performed by the CMP method, the silicon nitride film as the mask material 33 becomes a CMP stopper film.

(9) Next, the silicon oxide film 34 is annealed. As a result, the silicon oxide film 34 is densified and its crystallinity is brought close to that of the silicon thermal oxide film, thereby forming a high-quality silicon oxide film. The structure shown in FIGS. 6A and 6B is obtained through the above process.

(10) Next, as shown in FIGS. 7A and 7B, the mask material 33 is removed. Then, the upper surface of the silicon oxide film 34 is retracted by using the RIE method or wet etching. Thereby, as shown in FIG. 7B, the element isolation region 22 is completed.

(11) Next, as shown in FIGS. 8A and 8B, an inter-gate insulating film 35 (IPD film) is deposited on the exposed surface of the element isolation region 22 and the floating gate electrode layer 32. To do. As the inter-gate insulating film 35, for example, an ONO (Oxide-Nitride-Oxide) film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked is used.

(12) Next, as shown in FIGS. 9A and 9B, a mask material 36 is deposited on the inter-gate insulating film 35. As the material of the mask material 36, for example, polycrystalline silicon or a silicon oxide film can be used.

(13) Next, as shown in FIGS. 10A and 10B, a resist 37 is applied on the mask material 36. Then, a portion of the resist 37 corresponding to at least part of the region to be the channel region of the selection transistor is removed by photolithography. As a result, an opening 38 as shown in FIGS. 10A and 10B is formed. In the step of forming the opening 38, for example, a DUV (Deep Ultraviolet) lithography method is employed. According to this method, since the short wavelength light source is used, the opening 38 can be formed at a predetermined position with high accuracy.

(14) Next, as can be seen from FIGS. 11A and 11B, the mask material 36 located immediately below the opening 38 is removed by etching using the resist 37 having the opening 38 as a mask. . As can be seen from FIG. 11A, as a result of this step, the inter-gate insulating film 35 is exposed at the bottom of the opening 38.

(15) Next, as shown in FIGS. 12A and 12B, impurities are ion-implanted using the mask material 36 processed in the previous step as a mask. Thereby, impurities are introduced into the semiconductor substrate 1 in the region to be the channel region of the selection transistor, and the channel diffusion layer 19 is formed. In this ion implantation step, impurities are introduced into the semiconductor substrate 1 through the intergate insulating film 35, the floating gate electrode layer 32, and the gate insulating film 6. The type of impurity depends on the conductivity type of the selection transistor, but boron can be used for the n-channel, and phosphorus can be used for the p-channel. The reason why the ion implantation is performed while leaving the resist 37 in this step is that the resist 37 can be used as a mask material for ion implantation.

  Note that the thickness of the mask material 36 and the acceleration energy of the ions implanted are adjusted so that the ions are sufficiently attenuated in the mask material 36 and the ions passing through the opening 38 reach the semiconductor substrate 1. . Therefore, the ion implantation in this step does not affect the region where the memory cell transistor is to be formed.

(16) Next, as can be seen from FIGS. 13A and 13B, after removing the resist 37, the inter-gate insulating film 35 exposed at the bottom of the opening 38 is removed by etching.

  The ion implantation for forming the channel diffusion layer 19 described with reference to FIGS. 12A and 12B may be performed after the inter-gate insulating film 35 is etched in this step. However, when ion implantation is performed with the inter-gate insulating film 35 left, the inter-gate insulating film 35 functions as a protective film for the floating gate electrode layer 32, so that the surface of the floating gate electrode layer 32 is contaminated. There is an advantage that it can be prevented.

(17) Next, as can be seen from FIGS. 14A and 14B, the mask material 36 is removed. Then, a control gate electrode material 39 is formed on the floating gate electrode layer 32 and the inter-gate insulating film 35. At this time, the control gate electrode material 39 embedded in the opening 38 becomes the connection portion 16 that electrically connects the floating gate electrode layer 32 and the control gate electrode material 39. The control gate electrode material 39 includes, for example, a polycrystalline silicon film and a metal silicide film such as WSi (Tungsten Silicide). Of course, only the polycrystalline silicon film may be used without using the metal silicide film. The memory cell transistor formation region may be a multilayer structure including a polycrystalline silicon film and a metal silicide film, and the selection transistor formation region may be a structure including only a polycrystalline silicon film.

(18) Next, the control gate electrode material 39, the inter-gate insulating film 35, and the floating gate electrode layer 32 are patterned using photolithography and anisotropic etching such as RIE. As a result, as shown in FIGS. 15A and 15B, gate electrodes 7 and 7 ′ of the memory cell transistor and the dummy cell transistor including the charge storage layer 8, the intergate insulating film 9, and the control gate 10 are formed. The Further, the gate electrodes 13 of the select transistors ST1 and ST2 including the conductive layer 14, the intergate insulating film 15, and the conductive 17 are completed.

  In the steps shown in FIGS. 14A and 14B, when the control gate electrode material 39 is formed as a polycrystalline silicon film, after performing patterning in this step, the salicide (Salicide: Self-Aligned Silicide) is formed. ) May be used to form a silicide film.

(19) Thereafter, as can be seen from FIGS. 16A and 16B, impurities are ion-implanted into the semiconductor substrate 1 using the gate electrodes 7, 7 ′, 13 having a stacked gate structure as a mask. Thereafter, activation annealing is performed to form source / drain regions 4, 5, and 12 in the semiconductor substrate 1. As can be seen from FIGS. 15A and 16A, the impurities in the channel diffusion layer 19 are diffused during the activation annealing, so that the channel diffusion layer 19 spreads until reaching the source / drain region 5. .

  The structure shown in FIGS. 16A and 16B is completed through the above steps. As shown in FIGS. 16A and 16B, a memory cell transistor 2, a dummy cell transistor 2 ′, and a selection transistor 3 are provided on the semiconductor substrate 1. The memory cell transistor 2 has source / drain regions 4 and 4 provided in the semiconductor substrate 1. The memory cell transistor 2 has a gate electrode 7 provided on the semiconductor substrate 1 between the source / drain regions 4 and 4 with a gate insulating film 6 interposed therebetween. The gate electrode 7 is formed on the charge storage layer (floating gate) 8 directly formed on the gate insulating film 6, the inter-gate insulating film 9 formed on the charge storage layer 8, and the inter-gate insulating film 9. A control gate 10 is provided. A channel diffusion layer 11 is formed near the surface of the semiconductor substrate 1 between the source / drain regions 4 and 4.

  The dummy cell transistor 2 ′ includes source / drain regions 4 and 5 provided in the semiconductor substrate 1 and a gate electrode provided on the semiconductor substrate 1 between the source / drain regions 4 and 5 with a gate insulating film 6 interposed therebetween. 7 '. The gate electrode 7 ′ has the same configuration as the gate electrode 7. A channel diffusion layer 18 is formed near the surface of the semiconductor substrate 1 between the source / drain regions 4 and 5.

  As shown in FIGS. 16A and 16B, the select transistor 3 is provided adjacent to the dummy cell transistor 2 '. The selection transistor 3 has source / drain regions 5 and 12 provided in the semiconductor substrate 1. Of these, the source / drain region 5 is shared by the dummy cell transistor 2 ′ and the selection transistor 3. The select transistor 3 has a gate electrode 13 provided on the semiconductor substrate 1 between the source / drain regions 5 and 12 with a gate insulating film 6 interposed therebetween. The gate electrode 13 includes a conductive layer 14 formed on the gate insulating film 6, an intergate insulating film 15 formed on the conductive layer 14, a conductive layer 17 formed on the intergate insulating film 15, and a conductive layer 14. And a connecting portion 16 for electrically connecting the conductive layer 17 to each other. As can be seen from this configuration, the select transistor 3 functions in the same manner as a general MOSFET.

  Further, in the vicinity of the surface of the semiconductor substrate 1 between the source / drain regions 5, 12, the channel diffusion layer 19 reaches the source / drain regions 5, 12 and includes at least a region immediately below the connection portion 16. Is formed. The channel diffusion layer 19 has a higher impurity concentration than the channel diffusion layers 11 and 18 and is formed deeper than the channel diffusion layers 11 and 18. Thereby, the short channel effect can be suppressed in the select transistor 3.

  According to the above manufacturing method, the memory cell transistor 2 and the dummy cell transistor 2 ′ are covered with the mask material 36 when performing ion implantation for forming the channel region of the selection transistor 3. For this reason, impurities are not implanted into regions where the memory cell transistor 2 and the dummy cell transistor 2 'are to be formed. Therefore, the channel control of the selection transistor 3 can be performed independently of the memory cell transistor 2 and the dummy cell transistor 2 '.

  However, with the progress of miniaturization of the semiconductor process, the distance between the select transistor 3 and the adjacent dummy cell transistor 2 'becomes smaller and smaller. For this reason, the impurities introduced into the channel region of the selection transistor 3 through the opening 38 are diffused by the activation annealing in the subsequent stage, so that the source / drain diffusion layer 5 shared by the selection transistor 3 and the dummy cell transistor 2 ′ is formed. Will reach. As a result, the impurity profile of the source / drain diffusion layer 5 changes, and the electrical characteristics of the dummy cell transistor 2 ′ adjacent to the selection transistor 3 are different from those of the memory cell transistor 2.

  That is, the conductivity types of the source / drain region 5 and the channel diffusion layer 19 are different, but the channel diffusion layer 19 of the selection transistor 3 extends to the source / drain region 5 by activation annealing, so that the source / drain region 5 The carrier concentration of is lower than that of the source / drain region 4. As a result, the electrical characteristics of the dummy cell transistor 2 ′ adjacent to the selection transistor 3 are different from those of the memory cell transistor 2.

  Therefore, in the present embodiment, as described below, the dummy cell transistor 2 ′, which is a memory cell transistor adjacent to the selection transistor 3, is controlled as a dummy cell that is not used as a data storage element. As a result, the influence of the channel diffusion layer 19 of the selection transistor 3 on the memory cell transistor 2 can be reduced.

  Next, an example of a control method of the NAND flash memory having the dummy cell transistor 2 'will be described.

  FIG. 17 shows bias conditions when performing various memory operations (data read, erase, write). Here, a high threshold voltage state (write state) in which electrons are stored in the floating gate (charge storage layer 8) is defined as data “0”. On the other hand, a state where the threshold voltage is lower than the writing state (erasing state) is defined as data “1”. FIG. 18 shows threshold voltage distributions of the memory cell transistors corresponding to data “0” and data “1”, respectively.

  Data reading is performed as follows. First, the potential Vbl of the bit line BL is set to 0. Precharge to 5V. Thereafter, a read voltage Vr capable of discriminating the distribution of threshold voltages of data “0” and “1” shown in FIG. 18 is applied to the selected word line among the word lines WL0 to WL15, and the remaining unselected word lines The dummy word lines DWL0, 1 are supplied with a pass voltage Vread that turns on the transistor regardless of the data “0”, “1”. For example, the power supply voltage Vcc (or an appropriate intermediate voltage higher than Vcc) is applied to the selection gate lines SGD and SGS. Thereby, the potential of the bit line is lowered when the selected memory cell is on, and the potential of the bit line is maintained when the selected memory cell is off. Thereby, ON / OFF of the selected memory cell can be detected from the potential of the bit line, and data can be determined.

  Data erasing in the selected block is performed by erasing the voltage Vera (for example, p-type well) on the semiconductor substrate 1 (or the p-type well) in a state where the bit line BL and the selection gate lines SGD and SGS are in a floating state and all word lines WL are set to 0V. 18V) is applied. At this time, the dummy word lines DWL0 and DWL1 are also set to 0 V similarly to the word line WL. As a result, electrons are emitted from the floating gate (charge storage layer 8) of the memory cell transistor in the selected block, and data is erased.

  Data writing is performed as follows. A write voltage Vpgm is applied to the selected word line, and an appropriate intermediate voltage Vpass higher than the power supply voltage Vcc is applied to the remaining unselected word lines and dummy word lines DWL0,1. However, before applying the write voltage Vpgm, the bit line side select gate line SGD is set to Vcc and the source line side select gate line SGS is set to 0 V in accordance with the write data “0”, “1”. Vss and Vcc are applied to the bit line BL to precharge the NAND cell channel. A channel to which “0” data is applied becomes Vss, and a channel to which “1” data is applied is in a floating state of Vcc−Vth (Vth is a threshold voltage of the selection transistor). In this state, by applying the write voltage Vpgm to the selected word line, electrons are injected from the channel to the floating gate in the memory cell to which “0” data is applied. In a memory cell to which “1” data is applied, the channel potential rises due to capacitive coupling, and electrons are not injected into the floating gate. Thus, the memory cell to which “0” data is applied along the selected word line is in a write state of data “0” having a high threshold voltage shown in FIG.

  According to the data control method described above, even if dummy cells are introduced for memory operations for data erasing / writing / reading, complicated operations are not necessary, and operations can be performed under operating conditions that are not different from conventional ones.

  As described above, in this embodiment, channel control of the selection transistor 3 is performed by ion implantation using the opening 38. Thereby, the threshold voltage of the selection transistor 3 can be set to a predetermined value. Furthermore, in this embodiment, the memory cell transistor (dummy cell transistor 2 ′) adjacent to the selection transistor 3 is controlled as a dummy cell. Thereby, even when the distance between the selection transistor 3 and the NAND cell unit NCU is shortened due to the progress of miniaturization of the semiconductor process, the influence of the channel diffusion layer 19 of the selection transistor 3 on the memory cell transistor 2 can be reduced. .

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the above-described embodiments. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Memory cell transistor 2 'Dummy cell transistor 3 Select transistor 4, 5, 12 Source / drain region 6 Gate insulating film 7, 7', 13 Gate electrode 8 Charge storage layer 9, 15 Inter-gate insulating film 10 Control gate 11 , 18, 19 Channel diffusion layers 14 and 17 Conductive layer 16 Connection portion 20 Region 21 Active region 22 Element isolation region 30 Sacrificial silicon film 31 Ion implantation layer 32 Floating gate electrode layer 33 Mask material 34 Silicon oxide film 35 Intergate insulating film 36 Mask material 37 Resist 38 Opening 39 Control gate electrode material 101 Memory cell array 102 Sense amplifier / data latch 103 Column decoder 104 I / O buffer 105 Row decoder / word line driver 106 Address register 107 Control circuit 108 High voltage generation circuit

Claims (4)

A semiconductor memory device comprising: a memory cell unit having a plurality of memory cell transistors connected in series; and a selection transistor connected in series to the memory cell unit,
The memory cell transistor is
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode having a charge storage layer provided on the first gate insulating film, an intergate insulating film provided on the charge storage layer, and a control gate provided on the intergate insulating film When,
A first channel region formed in the semiconductor substrate under the first gate electrode and containing a first conductivity type impurity at a first concentration;
A first source / drain region of a second conductivity type formed in the semiconductor substrate so as to sandwich the first channel region,
The selection transistor is:
A second gate insulating film containing the impurity of the first conductivity type in at least a part of the region;
A first conductive layer provided on the second gate insulating film; provided on the first conductive layer; wherein the second gate insulating film includes a region containing the impurity of the first conductivity type. A second gate electrode having a connection portion located immediately above at least a part of the region, and a second conductive layer electrically connected to the first conductive layer by the connection portion;
A second channel region formed in the semiconductor substrate under the second gate electrode and containing the impurity of the first conductivity type at a second concentration higher than the first concentration;
A second source / drain region of the second conductivity type formed in the semiconductor substrate so as to sandwich the second channel region,
The semiconductor memory device, wherein the memory cell transistor adjacent to the selection transistor is a dummy cell transistor controlled as a dummy cell.   2. The semiconductor according to claim 1, wherein when erasing data of the memory cell transistor, the same bias voltage as that of the other memory cell transistor is applied to the first gate electrode of the dummy cell transistor. Storage device.   3. The semiconductor memory device according to claim 1, wherein when reading and writing data of the memory cell transistor, the same bias voltage as that of the non-selected memory cell transistor is applied to the dummy cell transistor. Injecting an impurity of the first conductivity type into the surface of the semiconductor substrate to a first concentration,
Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a first conductive layer on the gate insulating film;
Forming an isolation region in the semiconductor substrate and in the gate insulating film;
Forming an inter-gate insulating film on the element isolation region and the first conductive layer;
A mask material having an opening exposing at least a part of the surface of the inter-gate insulating film is formed on the inter-gate insulating film,
Impurities of the first conductivity type are implanted into the semiconductor substrate to a second concentration higher than the first concentration through the opening of the mask material,
Removing the inter-gate insulating film exposed in the opening of the mask material;
Forming a second conductive layer on the inter-gate insulating film so that the second conductive layer is connected to the first conductive layer through a region where the inter-gate insulating film is removed;
A patterned gate electrode is formed by patterning the first conductive layer, the intergate insulating film, and the second conductive layer,
Source / drain regions are formed by implanting a second conductivity type impurity into the semiconductor substrate around the stacked gate electrode.
A method of manufacturing a semiconductor device memory device.

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