JP2010050285A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a charge trap flash structure which can be highly integrated. <P>SOLUTION: In the semiconductor storage device 70, a gate insulation film 2, a charge accumulation film 3, a high dielectric constant insulation film 4, a gate electrode film 5, and an insulation film 6 are stacked on a first principal surface (the front surface) of a semiconductor substrate 1. The high dielectric constant insulation film 4 has a trapezoidal shape with the bottom being wider than the top. The gate electrode film 5 and the insulation film 6 are formed within the edge of the bottom of the high dielectric constant insulation film 4. The gate length of memory cell transistors MTR and the distance between the gates of the memory cell transistors MTR are set to 60 nm or below. There is no source nor drain formed between the gates of the memory cell transistors MTR. During writing and reading operations of the memory cell transistors MTR, an inverse layer 31 which has been generated serves for the source or drain. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  An electrically writable and erasable nonvolatile semiconductor memory device such as a flash memory is widely adopted as a large-capacity data storage medium such as a digital camera, a mobile terminal, a portable audio device, or a personal computer (PC). Typical non-volatile memory cell transistors used in flash memory include a stacked gate structure composed of a floating gate (FG) and a control gate (CG), and a silicon nitride film as a charge storage film. There is a charge trap type flash (CTF; also called Charge Trap Flash) structure to be used. In recent years, with the progress of miniaturization and high integration of semiconductor elements, the distance between the gates of the memory cell transistors is reduced in the flash memory having the stacked gate structure, and the capacitive coupling between the floating gates (FG) of adjacent cells. Malfunctions are likely to occur. For this reason, a memory cell transistor having a charge trap type flash structure in which malfunction is unlikely to occur has been developed (for example, see Patent Document 1).

In the memory cell transistor having a charge trap type flash structure described in Patent Document 1 and the like, the thickness of the charge storage layer is as thin as several nanometers, so that compared to a stacked gate structure using a floating gate electrode film, Malfunctions can be greatly suppressed. However, even in a memory cell transistor having a charge trap type flash structure, when the inter-cell spacing is further reduced, a dose loss of ion species to be ion-implanted for forming a diffusion layer in a semiconductor substrate between word lines of the memory cell occurs. The memory cell current decreases. If the inter-cell spacing is further reduced, if the charge storage layer is not separated from the charge storage layer of the adjacent memory cell, the charge stored in the charge storage layer of the memory cell transistor is stored in the charge storage layer of the adjacent memory cell transistor. Moving to the layer causes threshold fluctuations. In addition, when the memory cell transistor is miniaturized, the write charge is not uniformly written because the electric field is not uniformly applied to the charge storage layer at the time of writing to the memory cell transistor. There is a possibility that redistribution of the write charge occurs in the storage layer and the threshold value of the memory cell transistor fluctuates. As a result, there arises a problem that it is difficult to highly integrate a semiconductor memory device having a charge trap type flash structure.
JP 2003-78043 A

  The present invention provides a semiconductor memory device having a charge trap type flash structure that can be highly integrated.

  A semiconductor memory device according to one embodiment of the present invention includes a semiconductor substrate and a gate in which a gate insulating film, a first insulating film, a second insulating film, and a gate electrode film are stacked over the semiconductor substrate. The memory cell transistor and a gate on which the gate insulating film, the first insulating film, the second insulating film, and the gate electrode film are stacked on the semiconductor substrate. A second memory cell transistor disposed adjacent to the cell transistor, wherein the first insulating film is used as a charge storage film, and the second insulating film has a higher dielectric constant than the silicon oxide film, In the cell write operation and read operation, the semiconductor substrate is formed on the surface of the semiconductor substrate between the gate of the first memory cell transistor and the gate of the second memory cell transistor. Wherein the conductivity type of the inversion layer is formed.

  Furthermore, a semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate and a gate in which a gate insulating film, a first insulating film, a second insulating film, and a gate electrode film are stacked over the semiconductor substrate. A first memory cell transistor; and a gate on which the gate insulating film, the first insulating film, the second insulating film, and the gate electrode film are stacked on the semiconductor substrate. A second memory cell transistor disposed adjacent to the memory cell transistor; and the semiconductor substrate formed on a surface of the semiconductor substrate between a gate of the first memory cell transistor and a gate of the second memory cell transistor And the first insulating film is used as a charge storage film, the second insulating film has a dielectric constant higher than that of the silicon oxide film, and the second insulating film is used as a charge storage film. The edge film is wider at the bottom than at the top, and the first insulating film is provided inside the bottom end of the second insulating film. A portion where the first insulating film exists between the gate of the memory cell transistor and the gate of the second memory cell transistor, and the surface of the semiconductor substrate between the semiconductor layers opposite in conductivity type to the semiconductor substrate, An inversion layer opposite to the semiconductor substrate is formed, and the inversion layer and the semiconductor substrate are connected to an opposite conductivity type semiconductor layer.

  According to the present invention, a semiconductor memory device having a charge trap type flash structure that can be highly integrated can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. 1A and 1B are diagrams showing a semiconductor memory device, FIG. 1A is a circuit diagram showing the semiconductor memory device, FIG. 1B is a plan view showing the semiconductor memory device, and FIG. 2 is an AA of FIG. It is sectional drawing of the semiconductor memory device which follows a line. In this embodiment, the high dielectric constant insulating film as the block film is trapezoidal, the charge storage film and the gate insulating film are formed inside the bottom end of the high dielectric constant insulating film, and the diffusion layer serving as the source or drain is formed. Omitted.

  As shown in FIG. 1A, the semiconductor memory device 70 is provided with a plurality of unit memory cells. The plurality of unit memory cells constitute a memory cell block, and the plurality of memory cell blocks constitute a memory cell array. The semiconductor memory device 70 is a charge trap flash (CTF) memory. The charge trap flash memory may be called MONOS (Metal Oxide Nitride Oxide Silicon), SONOS (Silicon Oxide Nitride Oxide Silicon), or TANOS (TaN AlO Nitride Oxide Silicon).

  In the unit memory cell, a selection transistor STR is provided on the bit line BL side connected to a sense amplifier (not shown), a selection transistor STR is provided on the source line SL side, and a plurality of memory transistors MTR connected in cascade therebetween are provided. Provided. Bit lines BL1, BL2, and BL3 and control line SGD, word line WLn,..., Word line WL4, word line WL3, word line WL2, word line WL1, control line SGS, and source line SL cross each other. To do.

  The control line SGD is connected to the gates of the select transistors STR on the bit lines BL1 to BL3 connected to a sense amplifier (not shown). The word line WLn is connected to the control gate of the nth memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL4 is connected to the control gate of the fourth memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL3 is connected to the control gate of the third memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL2 is connected to the control gate of the second memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL1 is connected to the control gate of the first memory transistor MTR connected to the bit lines BL1 to BL3. The control line SGS is connected to the gates of the select transistors STR on the bit lines BL1 to BL3 connected to the source line SL.

  As shown in FIG. 1B, in the semiconductor memory device 70, the source line SL, the control line SGS, the word line WL1, the word line WL2, the word line WL3, the word line WL4,..., The word line WLn, the control line SGDs are spaced apart from each other in the vertical direction (in the drawing) and are arranged in parallel. Bit lines BL1 to BL3 are spaced apart from each other in the horizontal direction (in the drawing) and arranged in parallel. An element isolation region is provided between the bit lines BL to separate the bit lines BL. A source line contact SLC is provided at the intersection of the source line SL and the bit lines BL1 to BL3. A bit line contact BLC is provided on the bit line BL between the control line SGD and a sense amplifier (not shown).

  As shown in FIG. 2, the semiconductor memory device 70 includes a gate insulating film 2, a charge storage film (first insulating film) 3, a high dielectric constant on a first main surface (front surface) of a semiconductor substrate 1 made of P-type silicon. A rate insulating film (second insulating film) 4, a gate electrode film 5, and an insulating film 6 are laminated. The gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, and the gate electrode film 5 constitute the gate of the memory cell transistor.

  A gate insulating film 2 between the gates of the memory cell transistors covers the surface of the semiconductor substrate 1. The charge storage film 3 is provided inside the bottom end of the high dielectric constant insulating film 4. The high dielectric constant insulating film 4 is an insulating film having a dielectric constant higher than that of a silicon oxide film having a trapezoidal shape whose bottom is wider (tapered) than the top. Sidewall insulating films 7 are provided on both ends of the high dielectric constant insulating film 4, the gate electrode film 5, and the insulating film 6. The gate electrode film 5 and the insulating film 6 are formed inside the bottom end of the high dielectric constant insulating film 4. That is, the dimension in the channel length direction of the gate electrode film 5 and the insulating film 6 is narrower than the dimension in the channel length direction at the bottom of the high dielectric constant insulating film 4. When the gate electrode film 5 is silicided to reduce the resistance of the gate, the insulating film 6 as a gate processing mask is removed before silicidation.

Here, the gate length (word line WL width) of the memory cell transistor MTR and the gate of the memory cell transistor MTR (word line WL interval) are formed to be 60 nm or less and have a half pitch dimension. On the surface of the semiconductor substrate 1 that is P-type silicon between the gates of the memory cell transistor MTR, an N ⁺ layer that becomes the source or drain of the memory cell transistor MTR is not provided.

During writing, reading and erasing operations of the memory cell transistor MTR, a high electric field is generated between the gate of the memory cell transistor and the semiconductor substrate 1 or between the gates of the memory cell transistor, and the memory cell is generated by a fringe electric field between word lines. An inversion layer 31 is formed on the surface of the semiconductor substrate 1 which is P-type silicon between the gates of the transistor MTR. The inversion layer 31 extends to the surface of the semiconductor substrate 1 at the end of the charge storage film 3. The inversion layer 31 serve charge transfer from the source or drain layer of the control transistor STR is connected to the control transistors STR and the control line SGS is connected to the control line SDG, N ⁺ layer serving as a source or drain At least the write and read operations of the memory cell transistor are performed.

  Next, the operation of the semiconductor memory device will be described with reference to FIGS. FIG. 3 is a diagram showing the relationship of the fringe electric field during the read operation with respect to the word line WL interval of the memory cell transistor. In FIG. 3, the solid line (a) indicates the case where the high dielectric constant insulating film has a trapezoidal shape. FIG. 4 illustrates a write operation of the semiconductor memory device, FIG. 4A illustrates a memory cell block, and FIG. 4B illustrates a write operation condition when the high dielectric constant insulating film has a vertical shape. FIG. 5 illustrates a read operation of the semiconductor memory device, FIG. 5A illustrates a memory cell block, FIG. 5B illustrates a read operation condition, and FIG. 6 illustrates a semiconductor memory device. FIG. 6A is a diagram illustrating a memory cell block, and FIG. 6B is a diagram illustrating an erase operation condition.

  Here, the strength of the fringe electric field in FIG. 3 is calculated from a simulation. The fringe electric field simulation of FIG. 3 is for the worst case at the time of reading in which the adjacent word line WL is in a written state and electrons are accumulated in the charge accumulation layer. For this reason, the fringe electric field becomes stronger than the electric field applied to the tunnel insulating film of the memory cell transistor. When the memory cell transistor is in the erased state or neutral state, the electric field in the portion under the tunnel insulating film existing under the high dielectric constant film becomes stronger than the fringe electric field. The fact that the fringe electric field between the word lines WL is stronger than the tunnel electric field of the memory cell transistor is limited to the worst case reading in the writing state.

As shown in FIG. 3, the strength of the fringe electric field between the word lines during the read operation between the word lines WL of the memory cell transistor varies depending on the shape of both ends of the high dielectric constant insulating film 4 as the block film. Here, the pass voltage Vred is set to 5.5V for the unselected word line WL, and the selected word line WL is set to 0V. For example, a TEOS film having a dielectric constant comparable to that of a silicon oxide film having a relative dielectric constant of 3.9 is used as the interlayer insulating film 8 serving as a filling material between the word lines WL of the memory cell transistors, and a high dielectric constant insulation is used. The film 4 is an Al ₂ O ₃ film (alumina film) having a relative dielectric constant of about 10.

  When the end portion of the high dielectric constant insulating film 4 has a vertical shape (in the case of the broken line (b) in the figure, the taper angle is 90 °), the gate of the memory cell transistor has a substantially vertical shape, and has a trapezoidal high dielectric constant. Compared with the insulating film 4, the interval between the word lines WL of the memory cell transistors is increased. Therefore, the region where the fringe electric field is stronger than the electric field applied to the gate insulating film 5 as the tunnel oxide film in the cell writing state is limited to the relatively narrow word line WL interval.

  On the other hand, when the high dielectric constant insulating film 4 has a trapezoidal shape (in the case of the solid line (a) in the figure, the taper angle is 70 °), the gate of the memory cell transistor has a higher dielectric constant insulating film 4 portion than the other portion. The protruding shape is formed, and the interval between the bottom portions of the high dielectric constant insulating film 4 is narrowed. Therefore, the region where the fringe electric field is stronger than the electric field applied to the gate insulating film 5 as the tunnel oxide film in the cell writing state is compared with the case where the end portion of the high dielectric constant insulating film 4 is vertical. Then, it is expanded to a relatively wide interval between word lines WL. Therefore, as the taper angle of the high dielectric constant insulating film 4 is made gentler, the fringe electric field can be made stronger than the tunnel oxide film electric field, and an inversion layer can be easily formed on the surface of the semiconductor substrate 1 between the gates of the memory cell transistors.

  In the erase operation, since no n + diffusion layer is introduced, a hole accumulation layer is formed on the surface of the P-type semiconductor substrate 1, and the holes are erased by being injected into the charge accumulation layer.

  As shown in FIG. 4A, when a write operation is performed using a memory cell transistor selected by the word line WL3 and the bit line BL2 of the memory cell block as a selection transistor, as shown in FIG. When “0 (zero)” is written to the corresponding transistor, the corresponding bit line BL is set to “0 V”, and when “1” is written to the selection transistor, the corresponding bit line BL is set to the boosted high potential side power supply voltage Vdd. The source line SL is set to 0V. The control line SGD is set to a control voltage Vsg1 which is a (+) voltage, and the control voltage Vsg2 which is a (+) voltage is applied to the control line SGS to turn on the control transistor STR. The selected word line WL3 is set to the write voltage Vpgm, and the non-selected word line WL is set to the intermediate voltage Vm.

Here, the write voltage Vpgm is set to 20 V, for example, and the intermediate voltage Vm is set to 6 V, for example. Therefore, the fringe electric field between the word lines WL is as shown in FIG. 3, so that an inversion layer is formed on the surface of the semiconductor substrate 1 between the gates of the memory cell transistors, and there is no N ⁺ layer serving as the source or drain. The memory cell transistor can be written.

  As shown in FIG. 5A, when the read operation is performed using the memory cell transistor selected by the word line WL3 and the bit line BL2 of the memory cell block as a selection transistor, as shown in FIG. The bit line BL is set to the (+) voltage precharge voltage Vbl, and the source line SL is set to 0V. The control line SGD is set to a control voltage Vsg1 which is a (+) voltage, and the control voltage Vsg2 which is a (+) voltage is applied to the control line SGS to turn on the control transistor STR. The selected word line WL3 is set to 0V, and the non-selected word line WL is set to the pass voltage Vread.

Here, the pass voltage Vread is set to 5.5 V, for example. For this reason, since the fringe electric field between the word lines WL is stronger than the tunnel oxide film electric field at the time of reading of the memory cell transistor in the written state, an inversion layer is formed on the surface of the semiconductor substrate 1 between the gates of the memory cell transistor. The memory cell transistor can be read without an N ⁺ layer serving as a source or drain.

  As shown in FIG. 6A, when performing a batch erase operation on a memory cell block, as shown in FIG. 6B, the corresponding bit line BL, control line SGD, source line SL, and control line SGS are set. The semiconductor substrate 1 is set in the floating state, the erase voltage Vera is set, and the word line WL is set to 0V. When a P well layer is formed, an erase voltage Vera is applied to the P well layer.

  Here, the erase voltage Vera is set to 20 V, for example. For this reason, the information stored in the memory cell transistors of the memory cell block is erased collectively.

  Next, a method for manufacturing the semiconductor memory device will be described with reference to FIGS. 7 to 9 are cross-sectional views showing the manufacturing process of the semiconductor memory device, and FIG. 10 is a cross-sectional view showing the semiconductor memory device in which a gap is generated on the side surface of the gate.

  As shown in FIG. 7, first, a gate insulating film 2, a charge storage film (first insulating film) 3, and a high dielectric constant insulating film (second insulating film) 4 are formed on a semiconductor substrate 1 made of P-type silicon. The gate electrode film 5 and the insulating film 6 are stacked.

Here, a SiO ₂ film (silicon oxide film) having a thickness in the range of 0.5 to 10 nm is used for the gate insulating film 2 as a tunnel oxide film. Instead, the same thickness in terms of EOT (Equivalent Oxide Thickness) is used. the SiN film / SiO ₂ film laminated film (SiO ₂ is the semiconductor substrate 1 side), SiO ₂ film / SiN film / SiO ₂ of the laminated film, SiO ₂ film / high dielectric constant insulating film / SiO ₂ film laminated film of Alternatively, a laminated film of a high dielectric constant insulating film / SiO ₂ film may be used.

As the charge storage film 3, a SiN film (silicon nitride film) having a thickness in the range of 3 to 50 nm is used, but an HfAlO film may be used instead. Further, Al ₂ O ₃ film, MgO film, SrO film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, dielectric constant higher than silicon oxide film, A stacked film including a high dielectric constant insulating film such as a Y ₂ O ₃ film, a ZrSiO film, an HSiO film, or a LaAlO film may be used. In this case, the laminated film is SiN film / insulating film with high dielectric constant / SiN film, HfAlO film / insulating film with high dielectric constant / SiN film (SiN film on the gate insulating film 2 side), SiN film / insulating with high dielectric constant. Film / HfAlO film or HfAlO film / high dielectric constant insulating film / HfAlO film.

As the high dielectric constant insulating film 4 as the block film, an Al ₂ O ₃ film (alumina film) having a thickness in the range of 5 to 30 nm is used. Instead, an MgO film having a higher dielectric constant than the silicon oxide film, SrO film, SiN film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y ₂ O ₃ film, ZrSiO film, HfSiO film, LaAlO film, etc. A high dielectric constant insulating film or a laminated film thereof (including a laminated film of an Al ₂ O ₃ film (alumina film)) may be used. In that case, the laminated film is SiO ₂ film / high dielectric constant insulating film / SiO ₂ film, SiO ₂ film / high dielectric constant insulating film, high dielectric constant insulating film / SiO ₂ film, or high dielectric constant insulating film / SiO _2. Film / high dielectric constant insulating film.

As the gate electrode film 5, a P ⁺ polycrystalline silicon film and a metal silicide laminated film with a thickness of 10 to 500 nm doped with a high concentration of P-type impurities is used. Instead, P ⁺ polycrystalline silicon is used. A film or an N ⁺ polycrystalline silicon film doped with N-type impurities at a high concentration may be used. Alternatively, a metal film / polycrystalline silicon laminated film or a metal film / metal nitride laminated film may be used. In this case, the metal silicide is CoSi, NiSi, WSi, MoSi, TiSi or the like, the metal is W or the like, the metal nitride is WN, TaN, TiN or the like, and the carbide metal is TaC or the like.

The insulating film 6 is used as a mask material for gate formation. As the insulating film 6, a SiN film (silicon nitride film) is used, but an SiO ₂ film (silicon oxide film) may be used instead. When the gate electrode film 5 is silicided, the insulating film 6 is removed before silicidation.

  Next, a resist film 21 is formed by using a well-known lithography method, and the insulating film 6 is etched by, for example, RIE (Reactive Ion Etching) method using the resist film 21 as a mask.

Subsequently, as shown in FIG. 8, after removing the resist film 21, the gate electrode film 5 and the high dielectric constant insulating film 4 are etched by, for example, the RIE method using the insulating film 6 as a mask. At this time, in the RIE processing of the metal oxide film such as the insulating film 6 (Al ₂ O ₃ film), the deposit generated on the side wall surface during the etching is likely to remain as compared with the silicon, silicon oxide film, SiN film or the like. The shape of the film 6 (Al ₂ O ₃ film) is tapered.

Here, when the insulating film 6 (Al ₂ O ₃ film) is to be etched vertically and the high-frequency power in RIE, for example, is increased in order to cancel the decrease in the etching rate due to the deposit, the insulating film 6 (Al ₂ O ₃ film) The charge storage film 3 and the gate insulating film 2 immediately below are over-etched, and when the charge storage film 3 is etched, pitting (also referred to as gouging) occurs in the semiconductor substrate 1 which is P-type silicon, There is a problem that the current of the memory cell decreases.

  Then, as shown in FIG. 9, an insulating film to be the sidewall insulating film 7 is deposited on the entire surface of the semiconductor substrate 1, and the insulating film 6, the gate electrode film 5, and the high dielectric constant insulating film are formed by using, for example, the RIE method. A side wall insulating film 7 is formed at the end of 4.

  Next, using the insulating film 6 and the sidewall insulating film 7 as a mask, for example, the charge storage film 3 is etched by the RIE method to expose the side surfaces, and then, for example, the end portion of the charge storage film 3 exposed by the wet etching method is etched. Then, the charge storage film 3 is retracted inward from the high dielectric constant insulating film 4.

  The electric field applied to the charge storage film 3 during writing and erasing is reduced in a portion where the gate electrode film 5 is not placed, that is, a portion under the side wall insulating film 7. Therefore, the electric field applied to the charge storage film 3 can be improved by retracting the charge storage film 3 to the inside of the high dielectric constant insulating film 4 to the portion where the gate electrode 5 is placed. Here, the gate insulating film 2 is not removed by etching, but the end of the gate insulating film 2 between the charge storage films 3 may be etched. As a result, the inversion layer 31 formed on the surface of the semiconductor substrate 1 between the gates can be formed regardless of the film thickness variation of the gate insulating film 2.

  Subsequently, an interlayer insulating film 8 is formed so as to cover the gate side surface of the memory cell transistor. After the formation of the interlayer insulating film 8, an interlayer insulating film and a wiring layer are formed using a known technique, and the semiconductor memory device 70 as a NAND flash memory having a MONOS structure is completed.

  As shown in FIG. 10, when the interlayer insulating film 8 has a low covering capability, for example, the lower surface of the sidewall insulating film 7 and the high dielectric constant insulating film 4, the upper surface of the gate insulating film 2, and the side surface of the charge storage film 3. A gap 41 is generated in a portion surrounded by. Due to the air gap 41, the parasitic capacitance between the charge storage films 3 of the memory cell transistor can be reduced. The air gap 41 does not cause a decrease in reliability or a characteristic deterioration of the memory cell transistor.

  As described above, in the semiconductor memory device of this embodiment, the gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, the gate electrode film 5, and the insulating film are formed on the first main surface (front surface) of the semiconductor substrate 1. A film 6 is laminated. The high dielectric constant insulating film 4 has a trapezoidal shape whose bottom is wider than the top, and the gate electrode film 5 and the insulating film 6 are formed inside the bottom end of the high dielectric constant insulating film 4. The gap between the gate length of the memory cell transistor MTR and the gate of the memory cell transistor MTR is formed to be 60 nm or less. During the write and read operations of the memory cell transistor MTR, the fringe electric field between the word lines WL becomes stronger than the electric field of the gate insulating film 2 which is a tunnel oxide film, and is inverted to the surface of the semiconductor substrate 1 between the gates of the memory cell transistor MTR. Layer 31 is formed.

Therefore, the inversion layer 31 functions as a source or drain layer without performing an N ⁺ layer serving as a source or a drain, and writing and reading operations of the memory cell transistor can be performed. In addition, when the half pitch of a memory cell transistor having a diffusion layer serving as a source or drain is narrowed, a dose loss of ion implantation for forming a diffusion layer serving as a source or drain occurs and the memory cell current decreases. In the memory device 70, a decrease in memory cell current can be suppressed. Therefore, the half pitch of the memory cell transistors can be narrowed, and the semiconductor memory device 70 can be more highly integrated than before. Further, since the end portion of the high dielectric constant insulating film 4 as a block film has a trapezoidal shape with a taper, it is possible to suppress the occurrence of chipping of the semiconductor substrate 1 during gate processing and to reduce the memory cell current. Can be suppressed. Further, since the N ⁺ layer serving as the source or drain is not formed between the gates of the memory cell transistors, the manufacturing process of the semiconductor memory device 70 can be shortened.

  In this embodiment, the memory cell transistor is formed on the semiconductor substrate 1 made of P-type silicon. However, the memory cell transistor may be formed on a P well layer or an SOI (silicon on insulator) substrate. .

Next, a semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 11 is a cross-sectional view showing a semiconductor memory device. In this embodiment, an N ⁺ layer is provided on the surface of the semiconductor substrate between the gates of the memory cell transistors.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

As shown in FIG. 11, the semiconductor memory device 71 includes a gate insulating film 2, a charge storage film 3, a high dielectric constant insulating film 4, a gate electrode on the first main surface (front surface) of a semiconductor substrate 1 made of P-type silicon. A film 5 and an insulating film 6 are stacked. The gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, and the gate electrode film 5 constitute the gate of the memory cell transistor MTR. An N ⁺ layer 22 is provided on the surface of the semiconductor substrate 1 between the gates of the memory cell transistors MTR. The high dielectric constant insulating film 4 has a trapezoidal shape in which the bottom is wider (tapered) than the top. Sidewall insulating films 7 are provided on both ends of the high dielectric constant insulating film 4, the gate electrode film 5, and the insulating film 6. The gate electrode film 5 and the insulating film 6 are formed inside the bottom end of the high dielectric constant insulating film 4. That is, the dimensions of the gate electrode film 5 and the insulating film 6 are narrower than the dimensions of the bottom of the high dielectric constant insulating film 4. The charge storage film 3 is provided inside the bottom end of the high dielectric constant insulating film 4. The semiconductor memory device 71 is a charge trap flash (CTF) memory.

Here, the gate length (word line WL width) of the memory cell transistor MTR and the gate of the memory cell transistor MTR (word line WL interval) are formed to be 60 nm or less and have a half pitch dimension. During the writing operation and reading operation of the memory cell transistor MTR, the memory cell transistor gate insulating film 2 ends of the surface of the semiconductor substrate 1 is a P-type silicon and N ⁺ layer between the gate of the MTR 22 by fringe electric field between the word lines WL The inversion layer 31 is formed between the two. Electrons can be transferred by the inversion layer 31 and the N ⁺ layer 22, and writing and reading operations of the memory cell transistor MTR are performed.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIG. FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor memory device. Here, in the present embodiment, the process up to the formation of the gate of the memory cell transistor is the same as that of the first embodiment, and therefore illustration and description thereof are omitted.

As shown in FIG. 12, after forming the gate of the memory cell transistor MTR, As (arsenic) is converted into a semiconductor in the range of, for example, acceleration voltage (Vac) 1 to 50 KeV, dose amount (Qd) 1 × 10 ^{13 to} 5 × 10 ^14. Ions are implanted into the surface of the substrate 1. Since the gate insulating film 2 of the memory cell transistor MTR is formed inside the portion where the sidewall insulating film 7 is formed, the ion implantation layer is formed apart from the end of the gate insulating film 2. Note that P (phosphorus) or Sb (antimony) may be used instead of As (arsenic).

Next, high-temperature heat treatment is performed to activate and thermally diffuse the ion implantation layer, thereby forming the N ⁺ layer 22. Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

As described above, in the semiconductor memory device of this embodiment, the gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, the gate electrode film 5, and the insulating film are formed on the first main surface (front surface) of the semiconductor substrate 1. A film 6 is laminated. The high dielectric constant insulating film 4 has a trapezoidal shape whose bottom is wider than the top, and the gate electrode film 5 and the insulating film 6 are formed inside the bottom end of the high dielectric constant insulating film 4. The charge storage film 3 is provided inside the bottom end of the high dielectric constant insulating film 4. An N ⁺ layer 22 separated from the gate insulating film 2 is provided on the surface of the semiconductor substrate 1 between the gates of the memory cell transistors MTR. The gap between the gate length of the memory cell transistor MTR and the gate of the memory cell transistor MTR is formed to be 60 nm or less. During the write operation and read operation of the memory cell transistor MTR, the fringe electric field between the word lines WL is stronger than the electric field of the gate insulating film 2 that is a tunnel oxide film, and the surface of the semiconductor substrate 1 between the gates of the memory cell transistor MTR. An inversion layer 31 is formed between the end portion of the gate insulating film 2 and the N ⁺ layer 22.

For this reason, the inversion layer 31 and the N ⁺ layer 22 function as a source or drain layer, and writing and reading operations of the memory cell transistor can be performed. In addition, when the half pitch of a memory cell transistor having a diffusion layer serving as a source or drain is narrowed, a dose loss of ion implantation for forming a diffusion layer serving as a source or drain occurs and the memory cell current decreases. In the memory device 71, a decrease in memory cell current can be suppressed. Therefore, the half pitch of the memory cell transistors can be reduced, and the semiconductor memory device 71 can be more highly integrated than in the prior art. Further, since the end portion of the high dielectric constant insulating film 4 as a block film has a trapezoidal shape with a taper, it is possible to suppress the occurrence of chipping of the semiconductor substrate 1 during gate processing and to reduce the memory cell current. Can be suppressed.

  Next, a semiconductor memory device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 13 is a cross-sectional view showing a semiconductor memory device. In this embodiment, the gate structure of the memory cell transistor is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 13, the semiconductor memory device 72 includes a gate insulating film 2, a charge storage film 3, a high dielectric constant insulating film 4, a gate electrode on the first main surface (front surface) of a semiconductor substrate 1 made of P-type silicon. A film 5 and an insulating film 6 are stacked. The gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, and the gate electrode film 5 constitute the gate of the memory cell transistor MTR. The high dielectric constant insulating film 4 has a trapezoidal shape in which the bottom is wider (tapered) than the top. Sidewall insulating films 7 are provided on both ends of the high dielectric constant insulating film 4, the gate electrode film 5, and the insulating film 6. The gate electrode film 5 and the insulating film 6 are formed outside the bottom end of the high dielectric constant insulating film 4. The end of the charge storage film 3 is provided on the end of the sidewall insulating film 7. The semiconductor memory device 72 is a charge trap flash (CTF) memory.

Here, the gate length (word line WL width) of the memory cell transistor MTR and the gate of the memory cell transistor MTR (word line WL interval) are formed to be 60 nm or less and have a half pitch dimension. During the write operation and the read operation of the memory cell transistor MTR, the inversion layer 31 is formed on the surface of the semiconductor substrate 1 which is P-type silicon between the gates of the memory cell transistor MTR by a fringe electric field between the word lines WL. By the inversion layer 31, writing and reading operations of the memory cell transistor MTR are performed even if there is no N ⁺ layer serving as a source or a drain.

  In the semiconductor memory device 72 of this embodiment, unlike the first embodiment, after etching the charge storage layer 3 by RIE using the sidewall insulating film 7 as a mask, the inside of the charge storage layer 3 by wet etching or the like of the charge storage layer 3 is used. Did not go back to.

  As described above, in the semiconductor memory device of this embodiment, the gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, the gate electrode film 5, and the insulating film are formed on the first main surface (front surface) of the semiconductor substrate 1. A film 6 is laminated. The gate insulating film 2, the charge storage film 3, and the high dielectric constant insulating film 4 have a trapezoidal shape whose bottom is wider than the top. The gap between the gate length of the memory cell transistor MTR and the gate of the memory cell transistor MTR is formed to be 60 nm or less. During the write operation and the read operation of the memory cell transistor MTR, an inversion layer 31 is formed on the surface of the semiconductor substrate 1 between the gates of the memory cell transistor MTR by a fringe electric field between the word lines WL. For this reason, it has the same effect as Example 1.

  Next, a semiconductor memory device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 14 is a cross-sectional view showing a semiconductor memory device. In this embodiment, the gate structure of the memory cell transistor is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 14, the semiconductor memory device 73 includes a gate insulating film 2, a charge storage film (first insulating film) 3, a high dielectric on the first main surface (front surface) of a semiconductor substrate 1 made of P-type silicon. A rate insulating film (second insulating film) 4, a first gate electrode film 51, and a second gate electrode film 52 are stacked. The gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, the first gate electrode film 51, and the second gate electrode film 52 constitute the gate of the memory cell transistor. The semiconductor memory device 73 is a charge trap flash (CTF) memory.

On the surface of the semiconductor substrate 1, an N ⁺ layer 22 that selectively serves as a source or drain of the memory cell transistor is selectively provided. The gate insulating film 2 of the memory cell transistor covers the surface of the semiconductor substrate 1. Charge storage film 3 is viewed downward direction from the upper direction of the semiconductor substrate 1 is provided with a gate insulating film 2 so as to overlap with the N ⁺ layer 22 between the N ⁺ layer 22.

  The high dielectric constant insulating film 4 is provided on the charge storage film 3 so that the end is outside the charge storage film 3. The first gate electrode film 51 and the second gate electrode film 52 formed in a stacked manner are provided on the upper side of the central portion side of the high dielectric constant insulating film 4. The sidewall insulating film 7 is provided on the upper portion of the high dielectric constant insulating film 4 so as to cover the end portions of the first gate electrode film 51 and the second gate electrode film 52. An interlayer insulating film 8 is provided on the first main surface (front surface) of the semiconductor substrate 1 so as to cover the gate insulating film 2 and the gate of the memory cell transistor.

Here, the relationship between the charge storage film length L _{DC in} the channel length direction of the charge storage film 3 and the high dielectric constant insulating film length L _{HK in} the channel length direction of the high dielectric constant insulating film 4 is
L _HK > L _DC・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
Set to That is, the high dielectric constant insulating film 4 is formed wider than the dimension of the charge storage film 3 and larger than the dimensions of the first gate electrode film 51 and the second gate electrode film 52.

  For this reason, the electric field applied to the charge storage film 3 can be made uniform, and the threshold voltage (Vth) of the memory cell transistor due to charge movement inside the charge storage layer 3 caused by non-uniform charge writing in the charge storage film 3. ) Can be greatly suppressed. As a result, the memory cell transistors can be miniaturized (half pitch reduction), and the semiconductor memory device 73 can be highly integrated. Here, the bit line direction is shown and described, but also in the word line direction, the high dielectric constant insulating film 4 is formed wider than the dimension of the charge storage film 3, and the first gate electrode film 51, and It may be formed wider than the dimension of the second gate electrode film 52.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIGS. 15 to 19 are cross-sectional views showing the manufacturing process of the semiconductor memory device.

  As shown in FIG. 15, first, a gate insulating film 2, a charge storage film (first insulating film) 3, and a high dielectric constant insulating film (second insulating film) 4 are formed on a semiconductor substrate 1 made of P-type silicon. The first gate electrode film 51 and the second gate electrode film 52 are stacked.

Here, tantalum nitride (TaN) is used for the first gate electrode film 51. Instead, WN, TiN, TaC as a metal carbide, CoSi, NiSi, WSi as metal silicide, MoSi, TiSi or the like may be used. As the second gate electrode film 52, a P ⁺ polycrystalline silicon film doped with a high concentration of P-type impurities is used. Instead, an N ⁺ polycrystalline silicon film doped with a high concentration of N-type impurities is used. Etc. may be used.

  After the formation of the second gate electrode film 52, a resist film 53 is formed in the memory cell transistor formation region using a well-known lithography method.

  Next, as shown in FIG. 16, the first gate electrode film 51 and the second gate electrode film 52 are etched by, for example, RIE (Reactive Ion Etching) using the resist film 53 as a mask. After the RIE etching, using the resist film 53, the first gate electrode film 51, and the second gate electrode film 52 as a mask, the high dielectric constant insulating film (second insulating film) 4 and the charge storage film (first storage film) N-type impurities are ion-implanted into the surface of the semiconductor substrate 1 through the insulating film 3 and the gate insulating film 2.

Subsequently, as shown in FIG. 17, after removing the resist film 53, an ion implantation layer (not shown) is activated by, for example, heat treatment to form the N ⁺ layer 22. An insulating film is deposited on the high dielectric constant insulating film (second insulating film) 4, the first gate electrode film 51, and the second gate electrode film 52, and, for example, the entire gate is etched back to perform the first gate. Sidewall insulating films 7 are formed on the side surfaces of the electrode film 51 and the second gate electrode film 52.

Then, as shown in FIG. 18, with the sidewall insulating film 7 and the second gate electrode film 52 as a mask, a high dielectric constant insulating film (second film) on the N ⁺ layer 22 is formed by, eg, RIE (Reactive Ion Etching) method. Insulating film) 4 and charge storage film (first insulating film) 3 are etched. Here, the high dielectric constant insulating film (second insulating film) 4 is etched vertically, but it may be trapezoidal like the first embodiment.

  Next, as shown in FIG. 19, the end portion of the high dielectric constant insulating film (second insulating film) 4 is etched using, for example, a wet etching solution, so that the first gate electrode film 51 and the second gate electrode film 51 The gate electrode film 52 is made to recede to substantially the same width. Since the subsequent steps are the same as those in the first embodiment, illustration and description thereof are omitted.

As described above, in the semiconductor memory device of this embodiment, the gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, and the first gate electrode film 51 are formed on the first main surface (front surface) of the semiconductor substrate 1. And the second gate electrode film 52 are stacked. Charge storage film 3, as viewed from the lower direction from the upper direction of the semiconductor substrate 1, a gate insulating film 2 so as to overlap with the N ⁺ layer 22 between the N ⁺ layer 22 serving as a source or drain of the memory cell transistor Provided. The high dielectric constant insulating film 4 is provided on the outer side of the charge storage film 3, the first gate electrode film 51, and the second gate electrode film 52.

  Therefore, the electric field applied to the charge storage film 3 can be made uniform, and the threshold voltage (Vth) of the memory cell transistor due to charge movement inside the charge storage layer 3 caused by non-uniform charge writing in the charge storage film 3 It is possible to greatly suppress fluctuations in Therefore, the memory cell transistor can be miniaturized, and the semiconductor memory device 73 can be more highly integrated than in the past.

  Next, a semiconductor memory device according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 20 is a cross-sectional view showing a semiconductor memory device. In this embodiment, the gate structure of the memory cell transistor is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 20, the semiconductor memory device 74 includes a gate insulating film 2, a charge storage film (first insulating film) 3, a high dielectric constant on the first main surface (front surface) of a semiconductor substrate 1 made of P-type silicon. A rate insulating film (second insulating film) 4, a first gate electrode film 51, and a second gate electrode film 52 are stacked. The gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, the first gate electrode film 51, and the second gate electrode film 52 constitute the gate of the memory cell transistor. The semiconductor memory device 74 is a charge trap flash (CTF) memory.

  The charge storage film 3 is provided on the gate insulating film 2. The high dielectric constant insulating film 4 is provided on the charge storage film 3 so that the end portion is outside the charge storage film 3. The first gate electrode film 51 and the second gate electrode film 52 formed in a stacked manner are provided on the upper side of the central portion side of the high dielectric constant insulating film 4. The sidewall insulating film 7 is provided on the upper portion of the high dielectric constant insulating film 4 so as to cover the end portions of the first gate electrode film 51 and the second gate electrode film 52.

The gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, the first gate electrode film 51, the second gate electrode film 52, and the sidewall insulating film 7 have the same shape as in the fourth embodiment. , N ⁺ layer is not provided between the gate of the memory cell transistor in the semiconductor memory device 74.

  During writing, reading and erasing operations of the memory cell transistor MTR, a high electric field is generated between the gate of the memory cell transistor and the semiconductor substrate 1 or between the gates of the memory cell transistor, and the memory cell is generated by a fringe electric field between word lines. An inversion layer 31 is formed on the surface of the semiconductor substrate 1 which is P-type silicon between the gates of the transistor MTR.

  As described above, in the semiconductor memory device of this embodiment, the gate insulating film 2, the charge storage film 3, the high dielectric constant insulating film 4, and the first gate electrode film 51 are formed on the first main surface (front surface) of the semiconductor substrate 1. And the second gate electrode film 52 are stacked. The charge storage film 3 is provided on the gate insulating film 2. The high dielectric constant insulating film 4 is provided on the outer side of the charge storage film 3, the first gate electrode film 51, and the second gate electrode film 52. During the write and read operations of the memory cell transistor, the inversion layer 31 is formed on the surface of the semiconductor substrate 1 between the gates of the memory cell transistor MTR by a fringe electric field between the word lines WL.

Therefore, the inversion layer 31 functions as a source or drain layer without performing an N ⁺ layer serving as a source or a drain, and writing and reading operations of the memory cell transistor can be performed. In addition, when the half pitch of a memory cell transistor having a diffusion layer serving as a source or drain is narrowed, a dose loss of ion implantation for forming a diffusion layer serving as a source or drain occurs and the memory cell current decreases. In the memory device 74, a decrease in memory cell current can be suppressed. Further, the electric field applied to the charge storage film 3 can be made uniform, and the threshold voltage (Vth) of the memory cell transistor due to charge movement inside the charge storage layer 3 caused by non-uniform charge being written to the charge storage film 3. It is possible to greatly suppress fluctuations in Therefore, the memory cell transistor can be miniaturized and the semiconductor memory device 74 can be more highly integrated than in the past.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A semiconductor substrate, a first memory cell transistor having a gate on which a gate insulating film, a first insulating film, a second insulating film, and a gate electrode film are formed over the semiconductor substrate; A gate on which a gate insulating film, the first insulating film, the second insulating film, and the gate electrode film are stacked is formed on a semiconductor substrate, and is disposed adjacent to the first memory cell transistor. A first memory cell transistor is connected in cascade between the bit line and the source line, the gate of the memory cell transistor is connected to a word line, and the first memory cell transistor is connected to a word line. The insulating film is used as a charge storage film, and the second insulating film has a dielectric constant higher than that of the silicon oxide film, and the first memory cell is used during the write operation and read operation of the memory cell. An inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed on the surface of the semiconductor substrate between the gate of the transistor and the gate of the second memory cell transistor, and the inversion layer forms the first and second memory cells. A semiconductor memory device in which a transistor operates.

(Supplementary note 2) The semiconductor memory device according to supplementary note 1, wherein an end portion of the second insulating film is provided outside the first insulating film and the gate electrode film.

(Supplementary Note 3) The second insulating film includes an Al ₂ O ₃ film, an MgO film, an SrO film, a SiN film, a BaO film, a TiO film, a Ta ₂ O ₅ film, a BaTiO ₃ film, a BaZrO film, a ZrO ₂ film, It is a laminated film including a high dielectric constant insulating film which is an HfO ₂ film, a Y ₂ O ₃ film, a ZrSiO film, an HfSiO film, or a LaAlO film, and the laminated film is formed from an SiO ₂ film / High dielectric constant insulating film / SiO ₂ film, SiO ₂ film / high dielectric constant insulating film, high dielectric constant insulating film / SiO ₂ film, or high dielectric constant insulating film / SiO ₂ film / high dielectric constant insulating The semiconductor memory device according to appendix 1 or 2, which is a film.

(Supplementary Note 4) The first insulating film includes an Al ₂ O ₃ film, an MgO film, a SrO film, a BaO film, a TiO film, a Ta ₂ O ₅ film, a BaTiO ₃ film, a BaZrO film, a ZrO ₂ film, and an HfO ₂ film. , Y ₂ O ₃ film, ZrSiO film, HfSiO film, or LaAlO film, a laminated film including a high dielectric constant insulating film, and the laminated film is formed from the gate insulating film side from the SiN film / the high dielectric constant insulating film. Supplementary notes 1 to 3 are: / SiN film, HfAlO film / high dielectric constant insulating film / SiN film, SiN film / high dielectric constant insulating film / HfAlO film, or HfAlO film / high dielectric constant insulating film / HfAlO film. Any one of the semiconductor memory devices.

(Supplementary Note 5) The gate insulating film is a SiO ₂ film or a laminated film including a SiO ₂ film, and in the case of the laminated film, from the semiconductor substrate side, a SiN film / SiO ₂ film, a SiO ₂ film / SiN film / SiO 2 ₂ film, a semiconductor memory device according to any one of SiO ₂ film / high dielectric constant insulating film / SiO ₂ film Supplementary Notes 1 to 4 or a high dielectric constant insulating film / SiO ₂ film.

FIG. 1A is a circuit diagram illustrating a semiconductor memory device, and FIG. 1B is a plan view illustrating the semiconductor memory device. FIG. 2 is a cross-sectional view of the semiconductor memory device taken along line AA in FIG. The figure which shows the relationship of the fringe electric field with respect to the word line space | interval of the memory cell transistor which concerns on Example 1 of this invention, The solid line (a) in a figure is a figure in case a high dielectric constant insulating film has trapezoid shape, The broken line (b) in a figure ) Is a diagram when the high dielectric constant insulating film has a vertical shape. FIGS. 4A and 4B illustrate a write operation of the semiconductor memory device according to the first embodiment of the invention, FIG. 4A illustrates a memory cell block, and FIG. 4B illustrates a write operation condition. FIG. 5A is a diagram illustrating a read operation of the semiconductor memory device according to the first embodiment of the invention, FIG. 5A is a diagram illustrating a memory cell block, and FIG. 5B is a diagram illustrating a read operation condition. 6A and 6B are diagrams for explaining an erasing operation of the semiconductor memory device according to the first embodiment of the invention, FIG. 6A is a diagram showing a memory cell block, and FIG. 6B is a diagram showing an erasing operation condition. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. 1 is a cross-sectional view illustrating a semiconductor memory device in which a gap is generated on a gate side surface according to Embodiment 1 of the present invention. Sectional drawing which shows the semiconductor memory device based on Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 2 of this invention. Sectional drawing which shows the semiconductor memory device based on Example 3 of this invention. Sectional drawing which shows the semiconductor memory device based on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 4 of this invention. Sectional drawing which shows the semiconductor memory device based on Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Charge storage film 4 High dielectric constant insulating film 5 Gate electrode film 6 Insulating film 7 Side wall insulating film 8 Interlayer insulating film 21 Resist film 22 N ⁺ layer 31 Inversion layer 41 Void 51 First gate electrode Film 52 Second gate electrode film 53 Resist film 70 to 74 Semiconductor memory device BL1 to 3 Bit line BLC Bit line contact L _DC charge storage film length L _HK high dielectric constant insulating film length MTR Memory cell transistor SDG, SGS Control line SL source line SLC source line contact Vbl precharge voltage Vdd high-potential-side power supply voltage Vm intermediate voltage Vpgm write voltage Vread pass voltage Vsg1, Vsg2 control voltage _WL 1 to 4, WL _n word lines

Claims (5)

A semiconductor substrate;
A first memory cell transistor having a gate in which a gate insulating film, a first insulating film, a second insulating film, and a gate electrode film are stacked on the semiconductor substrate;
The gate insulating film, the first insulating film, the second insulating film, and the gate electrode film are stacked on the semiconductor substrate, and are disposed adjacent to the first memory cell transistor. A second memory cell transistor,
The first insulating film is used as a charge storage film, the second insulating film has a dielectric constant higher than that of the silicon oxide film, and the first insulating film is used for the memory cell write operation and read operation. An inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed on a surface of the semiconductor substrate between a gate of the memory cell transistor and a gate of the second memory cell transistor.   The semiconductor memory device according to claim 1, wherein an end portion of the first insulating film is provided on an inner side than the second insulating film. A semiconductor substrate;
A first memory cell transistor having a gate in which a gate insulating film, a first insulating film, a second insulating film, and a gate electrode film are stacked on the semiconductor substrate;
The gate insulating film, the first insulating film, the second insulating film, and the gate electrode film are stacked on the semiconductor substrate, and are disposed adjacent to the first memory cell transistor. A second memory cell transistor,
A semiconductor layer having a conductivity type opposite to that of the semiconductor substrate formed on the surface of the semiconductor substrate between a gate of the first memory cell transistor and a gate of the second memory cell transistor;
The first insulating film is used as a charge storage film, the second insulating film has a higher dielectric constant than the silicon oxide film, and the bottom of the second insulating film is wider than the top. The first insulating film is provided on the inner side of the bottom end of the second insulating film, and the gate of the first memory cell transistor and the second memory cell during the write operation and read operation of the memory cell. An inversion layer opposite to the semiconductor substrate is formed on the surface of the semiconductor substrate between the portion of the first insulating film between the gates of the memory cell transistor and the semiconductor layer having a conductivity type opposite to that of the semiconductor substrate. A semiconductor memory device, wherein the inversion layer and the semiconductor substrate are connected by a semiconductor layer having a reverse conductivity type. A semiconductor substrate;
A first memory cell transistor having a gate in which a gate insulating film, a first insulating film, a second insulating film, and a gate electrode film are stacked on the semiconductor substrate;
The gate insulating film, the first insulating film, the second insulating film, and the gate electrode film are stacked on the semiconductor substrate, and are disposed adjacent to the first memory cell transistor. A second memory cell transistor,
Provided on the surface of the semiconductor substrate so as to overlap the first insulating film between the first memory cell transistor and the second memory cell transistor when viewed from the top to the bottom of the semiconductor substrate. A semiconductor layer having a conductivity type opposite to that of the semiconductor substrate,
The first insulating film is used as a charge storage film, the second insulating film has a higher dielectric constant than the silicon oxide film, and has an end portion that is more than the first insulating film and the gate electrode film. A semiconductor memory device which is provided outside. The second insulating film is an Al ₂ O ₃ film, MgO film, SrO film, SiN film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a Y ₂ O ₃ film, a ZrSiO film, a HfSiO film, or a LaAlO film.

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